1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1994 Linus Torvalds
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/api.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
39 static void __init spectre_v1_select_mitigation(void);
40 static void __init spectre_v2_select_mitigation(void);
41 static void __init retbleed_select_mitigation(void);
42 static void __init spectre_v2_user_select_mitigation(void);
43 static void __init ssb_select_mitigation(void);
44 static void __init l1tf_select_mitigation(void);
45 static void __init mds_select_mitigation(void);
46 static void __init md_clear_update_mitigation(void);
47 static void __init md_clear_select_mitigation(void);
48 static void __init taa_select_mitigation(void);
49 static void __init mmio_select_mitigation(void);
50 static void __init srbds_select_mitigation(void);
51 static void __init l1d_flush_select_mitigation(void);
53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
54 u64 x86_spec_ctrl_base;
55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
61 static DEFINE_MUTEX(spec_ctrl_mutex);
64 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
65 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
67 void write_spec_ctrl_current(u64 val, bool force)
69 if (this_cpu_read(x86_spec_ctrl_current) == val)
72 this_cpu_write(x86_spec_ctrl_current, val);
75 * When KERNEL_IBRS this MSR is written on return-to-user, unless
76 * forced the update can be delayed until that time.
78 if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
79 wrmsrl(MSR_IA32_SPEC_CTRL, val);
82 u64 spec_ctrl_current(void)
84 return this_cpu_read(x86_spec_ctrl_current);
86 EXPORT_SYMBOL_GPL(spec_ctrl_current);
89 * AMD specific MSR info for Speculative Store Bypass control.
90 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
92 u64 __ro_after_init x86_amd_ls_cfg_base;
93 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
95 /* Control conditional STIBP in switch_to() */
96 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
97 /* Control conditional IBPB in switch_mm() */
98 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
99 /* Control unconditional IBPB in switch_mm() */
100 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
102 /* Control MDS CPU buffer clear before returning to user space */
103 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
104 EXPORT_SYMBOL_GPL(mds_user_clear);
105 /* Control MDS CPU buffer clear before idling (halt, mwait) */
106 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
107 EXPORT_SYMBOL_GPL(mds_idle_clear);
110 * Controls whether l1d flush based mitigations are enabled,
111 * based on hw features and admin setting via boot parameter
114 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
116 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
117 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
118 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
120 void __init check_bugs(void)
125 * identify_boot_cpu() initialized SMT support information, let the
128 cpu_smt_check_topology();
130 if (!IS_ENABLED(CONFIG_SMP)) {
132 print_cpu_info(&boot_cpu_data);
136 * Read the SPEC_CTRL MSR to account for reserved bits which may
137 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
138 * init code as it is not enumerated and depends on the family.
140 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
141 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
143 /* Select the proper CPU mitigations before patching alternatives: */
144 spectre_v1_select_mitigation();
145 spectre_v2_select_mitigation();
147 * retbleed_select_mitigation() relies on the state set by
148 * spectre_v2_select_mitigation(); specifically it wants to know about
151 retbleed_select_mitigation();
153 * spectre_v2_user_select_mitigation() relies on the state set by
154 * retbleed_select_mitigation(); specifically the STIBP selection is
157 spectre_v2_user_select_mitigation();
158 ssb_select_mitigation();
159 l1tf_select_mitigation();
160 md_clear_select_mitigation();
161 srbds_select_mitigation();
162 l1d_flush_select_mitigation();
168 * Check whether we are able to run this kernel safely on SMP.
170 * - i386 is no longer supported.
171 * - In order to run on anything without a TSC, we need to be
172 * compiled for a i486.
174 if (boot_cpu_data.x86 < 4)
175 panic("Kernel requires i486+ for 'invlpg' and other features");
177 init_utsname()->machine[1] =
178 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
179 alternative_instructions();
181 fpu__init_check_bugs();
182 #else /* CONFIG_X86_64 */
183 alternative_instructions();
186 * Make sure the first 2MB area is not mapped by huge pages
187 * There are typically fixed size MTRRs in there and overlapping
188 * MTRRs into large pages causes slow downs.
190 * Right now we don't do that with gbpages because there seems
191 * very little benefit for that case.
194 set_memory_4k((unsigned long)__va(0), 1);
199 * NOTE: This function is *only* called for SVM. VMX spec_ctrl handling is
203 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
205 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
206 struct thread_info *ti = current_thread_info();
208 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
209 if (hostval != guestval) {
210 msrval = setguest ? guestval : hostval;
211 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
216 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
217 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
219 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
220 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
224 * If the host has SSBD mitigation enabled, force it in the host's
225 * virtual MSR value. If its not permanently enabled, evaluate
226 * current's TIF_SSBD thread flag.
228 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
229 hostval = SPEC_CTRL_SSBD;
231 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
233 /* Sanitize the guest value */
234 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
236 if (hostval != guestval) {
239 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
240 ssbd_spec_ctrl_to_tif(hostval);
242 speculation_ctrl_update(tif);
245 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
247 static void x86_amd_ssb_disable(void)
249 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
251 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
252 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
253 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
254 wrmsrl(MSR_AMD64_LS_CFG, msrval);
258 #define pr_fmt(fmt) "MDS: " fmt
260 /* Default mitigation for MDS-affected CPUs */
261 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
262 static bool mds_nosmt __ro_after_init = false;
264 static const char * const mds_strings[] = {
265 [MDS_MITIGATION_OFF] = "Vulnerable",
266 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
267 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
270 static void __init mds_select_mitigation(void)
272 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
273 mds_mitigation = MDS_MITIGATION_OFF;
277 if (mds_mitigation == MDS_MITIGATION_FULL) {
278 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
279 mds_mitigation = MDS_MITIGATION_VMWERV;
281 static_branch_enable(&mds_user_clear);
283 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
284 (mds_nosmt || cpu_mitigations_auto_nosmt()))
285 cpu_smt_disable(false);
289 static int __init mds_cmdline(char *str)
291 if (!boot_cpu_has_bug(X86_BUG_MDS))
297 if (!strcmp(str, "off"))
298 mds_mitigation = MDS_MITIGATION_OFF;
299 else if (!strcmp(str, "full"))
300 mds_mitigation = MDS_MITIGATION_FULL;
301 else if (!strcmp(str, "full,nosmt")) {
302 mds_mitigation = MDS_MITIGATION_FULL;
308 early_param("mds", mds_cmdline);
311 #define pr_fmt(fmt) "TAA: " fmt
313 enum taa_mitigations {
315 TAA_MITIGATION_UCODE_NEEDED,
317 TAA_MITIGATION_TSX_DISABLED,
320 /* Default mitigation for TAA-affected CPUs */
321 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
322 static bool taa_nosmt __ro_after_init;
324 static const char * const taa_strings[] = {
325 [TAA_MITIGATION_OFF] = "Vulnerable",
326 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
327 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
328 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
331 static void __init taa_select_mitigation(void)
335 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
336 taa_mitigation = TAA_MITIGATION_OFF;
340 /* TSX previously disabled by tsx=off */
341 if (!boot_cpu_has(X86_FEATURE_RTM)) {
342 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
346 if (cpu_mitigations_off()) {
347 taa_mitigation = TAA_MITIGATION_OFF;
352 * TAA mitigation via VERW is turned off if both
353 * tsx_async_abort=off and mds=off are specified.
355 if (taa_mitigation == TAA_MITIGATION_OFF &&
356 mds_mitigation == MDS_MITIGATION_OFF)
359 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
360 taa_mitigation = TAA_MITIGATION_VERW;
362 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
365 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
366 * A microcode update fixes this behavior to clear CPU buffers. It also
367 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
368 * ARCH_CAP_TSX_CTRL_MSR bit.
370 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
371 * update is required.
373 ia32_cap = x86_read_arch_cap_msr();
374 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
375 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
376 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
379 * TSX is enabled, select alternate mitigation for TAA which is
380 * the same as MDS. Enable MDS static branch to clear CPU buffers.
382 * For guests that can't determine whether the correct microcode is
383 * present on host, enable the mitigation for UCODE_NEEDED as well.
385 static_branch_enable(&mds_user_clear);
387 if (taa_nosmt || cpu_mitigations_auto_nosmt())
388 cpu_smt_disable(false);
391 static int __init tsx_async_abort_parse_cmdline(char *str)
393 if (!boot_cpu_has_bug(X86_BUG_TAA))
399 if (!strcmp(str, "off")) {
400 taa_mitigation = TAA_MITIGATION_OFF;
401 } else if (!strcmp(str, "full")) {
402 taa_mitigation = TAA_MITIGATION_VERW;
403 } else if (!strcmp(str, "full,nosmt")) {
404 taa_mitigation = TAA_MITIGATION_VERW;
410 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
413 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
415 enum mmio_mitigations {
417 MMIO_MITIGATION_UCODE_NEEDED,
418 MMIO_MITIGATION_VERW,
421 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
422 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
423 static bool mmio_nosmt __ro_after_init = false;
425 static const char * const mmio_strings[] = {
426 [MMIO_MITIGATION_OFF] = "Vulnerable",
427 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
428 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
431 static void __init mmio_select_mitigation(void)
435 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
436 cpu_mitigations_off()) {
437 mmio_mitigation = MMIO_MITIGATION_OFF;
441 if (mmio_mitigation == MMIO_MITIGATION_OFF)
444 ia32_cap = x86_read_arch_cap_msr();
447 * Enable CPU buffer clear mitigation for host and VMM, if also affected
448 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
450 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
451 boot_cpu_has(X86_FEATURE_RTM)))
452 static_branch_enable(&mds_user_clear);
454 static_branch_enable(&mmio_stale_data_clear);
457 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
458 * be propagated to uncore buffers, clearing the Fill buffers on idle
459 * is required irrespective of SMT state.
461 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
462 static_branch_enable(&mds_idle_clear);
465 * Check if the system has the right microcode.
467 * CPU Fill buffer clear mitigation is enumerated by either an explicit
468 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
471 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
472 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
473 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
474 !(ia32_cap & ARCH_CAP_MDS_NO)))
475 mmio_mitigation = MMIO_MITIGATION_VERW;
477 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
479 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
480 cpu_smt_disable(false);
483 static int __init mmio_stale_data_parse_cmdline(char *str)
485 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
491 if (!strcmp(str, "off")) {
492 mmio_mitigation = MMIO_MITIGATION_OFF;
493 } else if (!strcmp(str, "full")) {
494 mmio_mitigation = MMIO_MITIGATION_VERW;
495 } else if (!strcmp(str, "full,nosmt")) {
496 mmio_mitigation = MMIO_MITIGATION_VERW;
502 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
505 #define pr_fmt(fmt) "" fmt
507 static void __init md_clear_update_mitigation(void)
509 if (cpu_mitigations_off())
512 if (!static_key_enabled(&mds_user_clear))
516 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
517 * mitigation, if necessary.
519 if (mds_mitigation == MDS_MITIGATION_OFF &&
520 boot_cpu_has_bug(X86_BUG_MDS)) {
521 mds_mitigation = MDS_MITIGATION_FULL;
522 mds_select_mitigation();
524 if (taa_mitigation == TAA_MITIGATION_OFF &&
525 boot_cpu_has_bug(X86_BUG_TAA)) {
526 taa_mitigation = TAA_MITIGATION_VERW;
527 taa_select_mitigation();
529 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
530 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
531 mmio_mitigation = MMIO_MITIGATION_VERW;
532 mmio_select_mitigation();
535 if (boot_cpu_has_bug(X86_BUG_MDS))
536 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
537 if (boot_cpu_has_bug(X86_BUG_TAA))
538 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
539 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
540 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
543 static void __init md_clear_select_mitigation(void)
545 mds_select_mitigation();
546 taa_select_mitigation();
547 mmio_select_mitigation();
550 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
551 * and print their mitigation after MDS, TAA and MMIO Stale Data
552 * mitigation selection is done.
554 md_clear_update_mitigation();
558 #define pr_fmt(fmt) "SRBDS: " fmt
560 enum srbds_mitigations {
561 SRBDS_MITIGATION_OFF,
562 SRBDS_MITIGATION_UCODE_NEEDED,
563 SRBDS_MITIGATION_FULL,
564 SRBDS_MITIGATION_TSX_OFF,
565 SRBDS_MITIGATION_HYPERVISOR,
568 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
570 static const char * const srbds_strings[] = {
571 [SRBDS_MITIGATION_OFF] = "Vulnerable",
572 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
573 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
574 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
575 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
578 static bool srbds_off;
580 void update_srbds_msr(void)
584 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
587 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
590 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
594 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
595 * being disabled and it hasn't received the SRBDS MSR microcode.
597 if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
600 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
602 switch (srbds_mitigation) {
603 case SRBDS_MITIGATION_OFF:
604 case SRBDS_MITIGATION_TSX_OFF:
605 mcu_ctrl |= RNGDS_MITG_DIS;
607 case SRBDS_MITIGATION_FULL:
608 mcu_ctrl &= ~RNGDS_MITG_DIS;
614 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
617 static void __init srbds_select_mitigation(void)
621 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
625 * Check to see if this is one of the MDS_NO systems supporting TSX that
626 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
627 * by Processor MMIO Stale Data vulnerability.
629 ia32_cap = x86_read_arch_cap_msr();
630 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
631 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
632 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
633 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
634 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
635 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
636 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
637 else if (cpu_mitigations_off() || srbds_off)
638 srbds_mitigation = SRBDS_MITIGATION_OFF;
641 pr_info("%s\n", srbds_strings[srbds_mitigation]);
644 static int __init srbds_parse_cmdline(char *str)
649 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
652 srbds_off = !strcmp(str, "off");
655 early_param("srbds", srbds_parse_cmdline);
658 #define pr_fmt(fmt) "L1D Flush : " fmt
660 enum l1d_flush_mitigations {
665 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
667 static void __init l1d_flush_select_mitigation(void)
669 if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
672 static_branch_enable(&switch_mm_cond_l1d_flush);
673 pr_info("Conditional flush on switch_mm() enabled\n");
676 static int __init l1d_flush_parse_cmdline(char *str)
678 if (!strcmp(str, "on"))
679 l1d_flush_mitigation = L1D_FLUSH_ON;
683 early_param("l1d_flush", l1d_flush_parse_cmdline);
686 #define pr_fmt(fmt) "Spectre V1 : " fmt
688 enum spectre_v1_mitigation {
689 SPECTRE_V1_MITIGATION_NONE,
690 SPECTRE_V1_MITIGATION_AUTO,
693 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
694 SPECTRE_V1_MITIGATION_AUTO;
696 static const char * const spectre_v1_strings[] = {
697 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
698 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
702 * Does SMAP provide full mitigation against speculative kernel access to
705 static bool smap_works_speculatively(void)
707 if (!boot_cpu_has(X86_FEATURE_SMAP))
711 * On CPUs which are vulnerable to Meltdown, SMAP does not
712 * prevent speculative access to user data in the L1 cache.
713 * Consider SMAP to be non-functional as a mitigation on these
716 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
722 static void __init spectre_v1_select_mitigation(void)
724 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
725 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
729 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
731 * With Spectre v1, a user can speculatively control either
732 * path of a conditional swapgs with a user-controlled GS
733 * value. The mitigation is to add lfences to both code paths.
735 * If FSGSBASE is enabled, the user can put a kernel address in
736 * GS, in which case SMAP provides no protection.
738 * If FSGSBASE is disabled, the user can only put a user space
739 * address in GS. That makes an attack harder, but still
740 * possible if there's no SMAP protection.
742 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
743 !smap_works_speculatively()) {
745 * Mitigation can be provided from SWAPGS itself or
746 * PTI as the CR3 write in the Meltdown mitigation
749 * If neither is there, mitigate with an LFENCE to
750 * stop speculation through swapgs.
752 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
753 !boot_cpu_has(X86_FEATURE_PTI))
754 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
757 * Enable lfences in the kernel entry (non-swapgs)
758 * paths, to prevent user entry from speculatively
761 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
765 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
768 static int __init nospectre_v1_cmdline(char *str)
770 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
773 early_param("nospectre_v1", nospectre_v1_cmdline);
775 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
779 #define pr_fmt(fmt) "RETBleed: " fmt
781 enum retbleed_mitigation {
782 RETBLEED_MITIGATION_NONE,
783 RETBLEED_MITIGATION_UNRET,
784 RETBLEED_MITIGATION_IBPB,
785 RETBLEED_MITIGATION_IBRS,
786 RETBLEED_MITIGATION_EIBRS,
789 enum retbleed_mitigation_cmd {
796 static const char * const retbleed_strings[] = {
797 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
798 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
799 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
800 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
801 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
804 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
805 RETBLEED_MITIGATION_NONE;
806 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
809 static int __ro_after_init retbleed_nosmt = false;
811 static int __init retbleed_parse_cmdline(char *str)
817 char *next = strchr(str, ',');
823 if (!strcmp(str, "off")) {
824 retbleed_cmd = RETBLEED_CMD_OFF;
825 } else if (!strcmp(str, "auto")) {
826 retbleed_cmd = RETBLEED_CMD_AUTO;
827 } else if (!strcmp(str, "unret")) {
828 retbleed_cmd = RETBLEED_CMD_UNRET;
829 } else if (!strcmp(str, "ibpb")) {
830 retbleed_cmd = RETBLEED_CMD_IBPB;
831 } else if (!strcmp(str, "nosmt")) {
832 retbleed_nosmt = true;
834 pr_err("Ignoring unknown retbleed option (%s).", str);
842 early_param("retbleed", retbleed_parse_cmdline);
844 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
845 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
847 static void __init retbleed_select_mitigation(void)
849 bool mitigate_smt = false;
851 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
854 switch (retbleed_cmd) {
855 case RETBLEED_CMD_OFF:
858 case RETBLEED_CMD_UNRET:
859 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
860 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
862 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
867 case RETBLEED_CMD_IBPB:
868 if (!boot_cpu_has(X86_FEATURE_IBPB)) {
869 pr_err("WARNING: CPU does not support IBPB.\n");
871 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
872 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
874 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
880 case RETBLEED_CMD_AUTO:
882 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
883 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
884 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
885 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
886 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
887 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
891 * The Intel mitigation (IBRS or eIBRS) was already selected in
892 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
893 * be set accordingly below.
899 switch (retbleed_mitigation) {
900 case RETBLEED_MITIGATION_UNRET:
901 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
902 setup_force_cpu_cap(X86_FEATURE_UNRET);
904 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
905 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
906 pr_err(RETBLEED_UNTRAIN_MSG);
911 case RETBLEED_MITIGATION_IBPB:
912 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
920 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
921 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
922 cpu_smt_disable(false);
925 * Let IBRS trump all on Intel without affecting the effects of the
926 * retbleed= cmdline option.
928 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
929 switch (spectre_v2_enabled) {
930 case SPECTRE_V2_IBRS:
931 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
933 case SPECTRE_V2_EIBRS:
934 case SPECTRE_V2_EIBRS_RETPOLINE:
935 case SPECTRE_V2_EIBRS_LFENCE:
936 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
939 pr_err(RETBLEED_INTEL_MSG);
943 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
947 #define pr_fmt(fmt) "Spectre V2 : " fmt
949 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
950 SPECTRE_V2_USER_NONE;
951 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
952 SPECTRE_V2_USER_NONE;
954 #ifdef CONFIG_RETPOLINE
955 static bool spectre_v2_bad_module;
957 bool retpoline_module_ok(bool has_retpoline)
959 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
962 pr_err("System may be vulnerable to spectre v2\n");
963 spectre_v2_bad_module = true;
967 static inline const char *spectre_v2_module_string(void)
969 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
972 static inline const char *spectre_v2_module_string(void) { return ""; }
975 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
976 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
977 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
978 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
980 #ifdef CONFIG_BPF_SYSCALL
981 void unpriv_ebpf_notify(int new_state)
986 /* Unprivileged eBPF is enabled */
988 switch (spectre_v2_enabled) {
989 case SPECTRE_V2_EIBRS:
990 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
992 case SPECTRE_V2_EIBRS_LFENCE:
993 if (sched_smt_active())
994 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1002 static inline bool match_option(const char *arg, int arglen, const char *opt)
1004 int len = strlen(opt);
1006 return len == arglen && !strncmp(arg, opt, len);
1009 /* The kernel command line selection for spectre v2 */
1010 enum spectre_v2_mitigation_cmd {
1011 SPECTRE_V2_CMD_NONE,
1012 SPECTRE_V2_CMD_AUTO,
1013 SPECTRE_V2_CMD_FORCE,
1014 SPECTRE_V2_CMD_RETPOLINE,
1015 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1016 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1017 SPECTRE_V2_CMD_EIBRS,
1018 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1019 SPECTRE_V2_CMD_EIBRS_LFENCE,
1020 SPECTRE_V2_CMD_IBRS,
1023 enum spectre_v2_user_cmd {
1024 SPECTRE_V2_USER_CMD_NONE,
1025 SPECTRE_V2_USER_CMD_AUTO,
1026 SPECTRE_V2_USER_CMD_FORCE,
1027 SPECTRE_V2_USER_CMD_PRCTL,
1028 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1029 SPECTRE_V2_USER_CMD_SECCOMP,
1030 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1033 static const char * const spectre_v2_user_strings[] = {
1034 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1035 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1036 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1037 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1038 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1041 static const struct {
1043 enum spectre_v2_user_cmd cmd;
1045 } v2_user_options[] __initconst = {
1046 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1047 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1048 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1049 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1050 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1051 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1052 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1055 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1057 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1058 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1061 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1063 static enum spectre_v2_user_cmd __init
1064 spectre_v2_parse_user_cmdline(void)
1069 switch (spectre_v2_cmd) {
1070 case SPECTRE_V2_CMD_NONE:
1071 return SPECTRE_V2_USER_CMD_NONE;
1072 case SPECTRE_V2_CMD_FORCE:
1073 return SPECTRE_V2_USER_CMD_FORCE;
1078 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1081 return SPECTRE_V2_USER_CMD_AUTO;
1083 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1084 if (match_option(arg, ret, v2_user_options[i].option)) {
1085 spec_v2_user_print_cond(v2_user_options[i].option,
1086 v2_user_options[i].secure);
1087 return v2_user_options[i].cmd;
1091 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1092 return SPECTRE_V2_USER_CMD_AUTO;
1095 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1097 return mode == SPECTRE_V2_IBRS ||
1098 mode == SPECTRE_V2_EIBRS ||
1099 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1100 mode == SPECTRE_V2_EIBRS_LFENCE;
1104 spectre_v2_user_select_mitigation(void)
1106 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1107 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1108 enum spectre_v2_user_cmd cmd;
1110 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1113 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1114 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1115 smt_possible = false;
1117 cmd = spectre_v2_parse_user_cmdline();
1119 case SPECTRE_V2_USER_CMD_NONE:
1121 case SPECTRE_V2_USER_CMD_FORCE:
1122 mode = SPECTRE_V2_USER_STRICT;
1124 case SPECTRE_V2_USER_CMD_AUTO:
1125 case SPECTRE_V2_USER_CMD_PRCTL:
1126 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1127 mode = SPECTRE_V2_USER_PRCTL;
1129 case SPECTRE_V2_USER_CMD_SECCOMP:
1130 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1131 if (IS_ENABLED(CONFIG_SECCOMP))
1132 mode = SPECTRE_V2_USER_SECCOMP;
1134 mode = SPECTRE_V2_USER_PRCTL;
1138 /* Initialize Indirect Branch Prediction Barrier */
1139 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1140 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1142 spectre_v2_user_ibpb = mode;
1144 case SPECTRE_V2_USER_CMD_FORCE:
1145 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1146 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1147 static_branch_enable(&switch_mm_always_ibpb);
1148 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1150 case SPECTRE_V2_USER_CMD_PRCTL:
1151 case SPECTRE_V2_USER_CMD_AUTO:
1152 case SPECTRE_V2_USER_CMD_SECCOMP:
1153 static_branch_enable(&switch_mm_cond_ibpb);
1159 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1160 static_key_enabled(&switch_mm_always_ibpb) ?
1161 "always-on" : "conditional");
1165 * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible,
1166 * STIBP is not required.
1168 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1170 spectre_v2_in_ibrs_mode(spectre_v2_enabled))
1174 * At this point, an STIBP mode other than "off" has been set.
1175 * If STIBP support is not being forced, check if STIBP always-on
1178 if (mode != SPECTRE_V2_USER_STRICT &&
1179 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1180 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1182 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
1183 if (mode != SPECTRE_V2_USER_STRICT &&
1184 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1185 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1186 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1189 spectre_v2_user_stibp = mode;
1192 pr_info("%s\n", spectre_v2_user_strings[mode]);
1195 static const char * const spectre_v2_strings[] = {
1196 [SPECTRE_V2_NONE] = "Vulnerable",
1197 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1198 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1199 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
1200 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
1201 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
1202 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1205 static const struct {
1207 enum spectre_v2_mitigation_cmd cmd;
1209 } mitigation_options[] __initconst = {
1210 { "off", SPECTRE_V2_CMD_NONE, false },
1211 { "on", SPECTRE_V2_CMD_FORCE, true },
1212 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1213 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1214 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1215 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1216 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1217 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1218 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1219 { "auto", SPECTRE_V2_CMD_AUTO, false },
1220 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1223 static void __init spec_v2_print_cond(const char *reason, bool secure)
1225 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1226 pr_info("%s selected on command line.\n", reason);
1229 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1231 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1235 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1236 cpu_mitigations_off())
1237 return SPECTRE_V2_CMD_NONE;
1239 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1241 return SPECTRE_V2_CMD_AUTO;
1243 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1244 if (!match_option(arg, ret, mitigation_options[i].option))
1246 cmd = mitigation_options[i].cmd;
1250 if (i >= ARRAY_SIZE(mitigation_options)) {
1251 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1252 return SPECTRE_V2_CMD_AUTO;
1255 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1256 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1257 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1258 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1259 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1260 !IS_ENABLED(CONFIG_RETPOLINE)) {
1261 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1262 mitigation_options[i].option);
1263 return SPECTRE_V2_CMD_AUTO;
1266 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1267 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1268 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1269 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1270 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1271 mitigation_options[i].option);
1272 return SPECTRE_V2_CMD_AUTO;
1275 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1276 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1277 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1278 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1279 mitigation_options[i].option);
1280 return SPECTRE_V2_CMD_AUTO;
1283 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1284 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1285 mitigation_options[i].option);
1286 return SPECTRE_V2_CMD_AUTO;
1289 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1290 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1291 mitigation_options[i].option);
1292 return SPECTRE_V2_CMD_AUTO;
1295 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1296 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1297 mitigation_options[i].option);
1298 return SPECTRE_V2_CMD_AUTO;
1301 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1302 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1303 mitigation_options[i].option);
1304 return SPECTRE_V2_CMD_AUTO;
1307 spec_v2_print_cond(mitigation_options[i].option,
1308 mitigation_options[i].secure);
1312 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1314 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1315 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1316 return SPECTRE_V2_NONE;
1319 return SPECTRE_V2_RETPOLINE;
1322 /* Disable in-kernel use of non-RSB RET predictors */
1323 static void __init spec_ctrl_disable_kernel_rrsba(void)
1327 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1330 ia32_cap = x86_read_arch_cap_msr();
1332 if (ia32_cap & ARCH_CAP_RRSBA) {
1333 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1334 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1338 static void __init spectre_v2_select_mitigation(void)
1340 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1341 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1344 * If the CPU is not affected and the command line mode is NONE or AUTO
1345 * then nothing to do.
1347 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1348 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1352 case SPECTRE_V2_CMD_NONE:
1355 case SPECTRE_V2_CMD_FORCE:
1356 case SPECTRE_V2_CMD_AUTO:
1357 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1358 mode = SPECTRE_V2_EIBRS;
1362 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1363 boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1364 retbleed_cmd != RETBLEED_CMD_OFF &&
1365 boot_cpu_has(X86_FEATURE_IBRS) &&
1366 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1367 mode = SPECTRE_V2_IBRS;
1371 mode = spectre_v2_select_retpoline();
1374 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1375 pr_err(SPECTRE_V2_LFENCE_MSG);
1376 mode = SPECTRE_V2_LFENCE;
1379 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1380 mode = SPECTRE_V2_RETPOLINE;
1383 case SPECTRE_V2_CMD_RETPOLINE:
1384 mode = spectre_v2_select_retpoline();
1387 case SPECTRE_V2_CMD_IBRS:
1388 mode = SPECTRE_V2_IBRS;
1391 case SPECTRE_V2_CMD_EIBRS:
1392 mode = SPECTRE_V2_EIBRS;
1395 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1396 mode = SPECTRE_V2_EIBRS_LFENCE;
1399 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1400 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1404 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1405 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1407 if (spectre_v2_in_ibrs_mode(mode)) {
1408 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1409 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1413 case SPECTRE_V2_NONE:
1414 case SPECTRE_V2_EIBRS:
1417 case SPECTRE_V2_IBRS:
1418 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1419 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1420 pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1423 case SPECTRE_V2_LFENCE:
1424 case SPECTRE_V2_EIBRS_LFENCE:
1425 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1428 case SPECTRE_V2_RETPOLINE:
1429 case SPECTRE_V2_EIBRS_RETPOLINE:
1430 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1435 * Disable alternate RSB predictions in kernel when indirect CALLs and
1436 * JMPs gets protection against BHI and Intramode-BTI, but RET
1437 * prediction from a non-RSB predictor is still a risk.
1439 if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1440 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1441 mode == SPECTRE_V2_RETPOLINE)
1442 spec_ctrl_disable_kernel_rrsba();
1444 spectre_v2_enabled = mode;
1445 pr_info("%s\n", spectre_v2_strings[mode]);
1448 * If Spectre v2 protection has been enabled, fill the RSB during a
1449 * context switch. In general there are two types of RSB attacks
1450 * across context switches, for which the CALLs/RETs may be unbalanced.
1454 * Some Intel parts have "bottomless RSB". When the RSB is empty,
1455 * speculated return targets may come from the branch predictor,
1456 * which could have a user-poisoned BTB or BHB entry.
1458 * AMD has it even worse: *all* returns are speculated from the BTB,
1459 * regardless of the state of the RSB.
1461 * When IBRS or eIBRS is enabled, the "user -> kernel" attack
1462 * scenario is mitigated by the IBRS branch prediction isolation
1463 * properties, so the RSB buffer filling wouldn't be necessary to
1464 * protect against this type of attack.
1466 * The "user -> user" attack scenario is mitigated by RSB filling.
1468 * 2) Poisoned RSB entry
1470 * If the 'next' in-kernel return stack is shorter than 'prev',
1471 * 'next' could be tricked into speculating with a user-poisoned RSB
1474 * The "user -> kernel" attack scenario is mitigated by SMEP and
1477 * The "user -> user" scenario, also known as SpectreBHB, requires
1480 * So to mitigate all cases, unconditionally fill RSB on context
1483 * FIXME: Is this pointless for retbleed-affected AMD?
1485 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1486 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1489 * Similar to context switches, there are two types of RSB attacks
1494 * 2) Poisoned RSB entry
1496 * When retpoline is enabled, both are mitigated by filling/clearing
1499 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1500 * prediction isolation protections, RSB still needs to be cleared
1501 * because of #2. Note that SMEP provides no protection here, unlike
1502 * user-space-poisoned RSB entries.
1504 * eIBRS, on the other hand, has RSB-poisoning protections, so it
1505 * doesn't need RSB clearing after vmexit.
1507 if (boot_cpu_has(X86_FEATURE_RETPOLINE) ||
1508 boot_cpu_has(X86_FEATURE_KERNEL_IBRS))
1509 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1512 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1513 * and Enhanced IBRS protect firmware too, so enable IBRS around
1514 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1517 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1518 * the user might select retpoline on the kernel command line and if
1519 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1520 * enable IBRS around firmware calls.
1522 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1523 boot_cpu_has(X86_FEATURE_IBPB) &&
1524 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1525 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1527 if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1528 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1529 pr_info("Enabling Speculation Barrier for firmware calls\n");
1532 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1533 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1534 pr_info("Enabling Restricted Speculation for firmware calls\n");
1537 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1538 spectre_v2_cmd = cmd;
1541 static void update_stibp_msr(void * __unused)
1543 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1544 write_spec_ctrl_current(val, true);
1547 /* Update x86_spec_ctrl_base in case SMT state changed. */
1548 static void update_stibp_strict(void)
1550 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1552 if (sched_smt_active())
1553 mask |= SPEC_CTRL_STIBP;
1555 if (mask == x86_spec_ctrl_base)
1558 pr_info("Update user space SMT mitigation: STIBP %s\n",
1559 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1560 x86_spec_ctrl_base = mask;
1561 on_each_cpu(update_stibp_msr, NULL, 1);
1564 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1565 static void update_indir_branch_cond(void)
1567 if (sched_smt_active())
1568 static_branch_enable(&switch_to_cond_stibp);
1570 static_branch_disable(&switch_to_cond_stibp);
1574 #define pr_fmt(fmt) fmt
1576 /* Update the static key controlling the MDS CPU buffer clear in idle */
1577 static void update_mds_branch_idle(void)
1579 u64 ia32_cap = x86_read_arch_cap_msr();
1582 * Enable the idle clearing if SMT is active on CPUs which are
1583 * affected only by MSBDS and not any other MDS variant.
1585 * The other variants cannot be mitigated when SMT is enabled, so
1586 * clearing the buffers on idle just to prevent the Store Buffer
1587 * repartitioning leak would be a window dressing exercise.
1589 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1592 if (sched_smt_active()) {
1593 static_branch_enable(&mds_idle_clear);
1594 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1595 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1596 static_branch_disable(&mds_idle_clear);
1600 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1601 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1602 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1604 void cpu_bugs_smt_update(void)
1606 mutex_lock(&spec_ctrl_mutex);
1608 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1609 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1610 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1612 switch (spectre_v2_user_stibp) {
1613 case SPECTRE_V2_USER_NONE:
1615 case SPECTRE_V2_USER_STRICT:
1616 case SPECTRE_V2_USER_STRICT_PREFERRED:
1617 update_stibp_strict();
1619 case SPECTRE_V2_USER_PRCTL:
1620 case SPECTRE_V2_USER_SECCOMP:
1621 update_indir_branch_cond();
1625 switch (mds_mitigation) {
1626 case MDS_MITIGATION_FULL:
1627 case MDS_MITIGATION_VMWERV:
1628 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1629 pr_warn_once(MDS_MSG_SMT);
1630 update_mds_branch_idle();
1632 case MDS_MITIGATION_OFF:
1636 switch (taa_mitigation) {
1637 case TAA_MITIGATION_VERW:
1638 case TAA_MITIGATION_UCODE_NEEDED:
1639 if (sched_smt_active())
1640 pr_warn_once(TAA_MSG_SMT);
1642 case TAA_MITIGATION_TSX_DISABLED:
1643 case TAA_MITIGATION_OFF:
1647 switch (mmio_mitigation) {
1648 case MMIO_MITIGATION_VERW:
1649 case MMIO_MITIGATION_UCODE_NEEDED:
1650 if (sched_smt_active())
1651 pr_warn_once(MMIO_MSG_SMT);
1653 case MMIO_MITIGATION_OFF:
1657 mutex_unlock(&spec_ctrl_mutex);
1661 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1663 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1665 /* The kernel command line selection */
1666 enum ssb_mitigation_cmd {
1667 SPEC_STORE_BYPASS_CMD_NONE,
1668 SPEC_STORE_BYPASS_CMD_AUTO,
1669 SPEC_STORE_BYPASS_CMD_ON,
1670 SPEC_STORE_BYPASS_CMD_PRCTL,
1671 SPEC_STORE_BYPASS_CMD_SECCOMP,
1674 static const char * const ssb_strings[] = {
1675 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1676 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1677 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1678 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1681 static const struct {
1683 enum ssb_mitigation_cmd cmd;
1684 } ssb_mitigation_options[] __initconst = {
1685 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1686 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1687 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1688 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1689 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1692 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1694 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1698 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1699 cpu_mitigations_off()) {
1700 return SPEC_STORE_BYPASS_CMD_NONE;
1702 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1705 return SPEC_STORE_BYPASS_CMD_AUTO;
1707 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1708 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1711 cmd = ssb_mitigation_options[i].cmd;
1715 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1716 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1717 return SPEC_STORE_BYPASS_CMD_AUTO;
1724 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1726 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1727 enum ssb_mitigation_cmd cmd;
1729 if (!boot_cpu_has(X86_FEATURE_SSBD))
1732 cmd = ssb_parse_cmdline();
1733 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1734 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1735 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1739 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1741 * Choose prctl+seccomp as the default mode if seccomp is
1744 if (IS_ENABLED(CONFIG_SECCOMP))
1745 mode = SPEC_STORE_BYPASS_SECCOMP;
1747 mode = SPEC_STORE_BYPASS_PRCTL;
1749 case SPEC_STORE_BYPASS_CMD_ON:
1750 mode = SPEC_STORE_BYPASS_DISABLE;
1752 case SPEC_STORE_BYPASS_CMD_AUTO:
1753 case SPEC_STORE_BYPASS_CMD_PRCTL:
1754 mode = SPEC_STORE_BYPASS_PRCTL;
1756 case SPEC_STORE_BYPASS_CMD_NONE:
1761 * We have three CPU feature flags that are in play here:
1762 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1763 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1764 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1766 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1767 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1769 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1770 * use a completely different MSR and bit dependent on family.
1772 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1773 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1774 x86_amd_ssb_disable();
1776 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1777 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1784 static void ssb_select_mitigation(void)
1786 ssb_mode = __ssb_select_mitigation();
1788 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1789 pr_info("%s\n", ssb_strings[ssb_mode]);
1793 #define pr_fmt(fmt) "Speculation prctl: " fmt
1795 static void task_update_spec_tif(struct task_struct *tsk)
1797 /* Force the update of the real TIF bits */
1798 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1801 * Immediately update the speculation control MSRs for the current
1802 * task, but for a non-current task delay setting the CPU
1803 * mitigation until it is scheduled next.
1805 * This can only happen for SECCOMP mitigation. For PRCTL it's
1806 * always the current task.
1809 speculation_ctrl_update_current();
1812 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
1815 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1819 case PR_SPEC_ENABLE:
1820 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1822 case PR_SPEC_DISABLE:
1823 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1830 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1832 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1833 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1837 case PR_SPEC_ENABLE:
1838 /* If speculation is force disabled, enable is not allowed */
1839 if (task_spec_ssb_force_disable(task))
1841 task_clear_spec_ssb_disable(task);
1842 task_clear_spec_ssb_noexec(task);
1843 task_update_spec_tif(task);
1845 case PR_SPEC_DISABLE:
1846 task_set_spec_ssb_disable(task);
1847 task_clear_spec_ssb_noexec(task);
1848 task_update_spec_tif(task);
1850 case PR_SPEC_FORCE_DISABLE:
1851 task_set_spec_ssb_disable(task);
1852 task_set_spec_ssb_force_disable(task);
1853 task_clear_spec_ssb_noexec(task);
1854 task_update_spec_tif(task);
1856 case PR_SPEC_DISABLE_NOEXEC:
1857 if (task_spec_ssb_force_disable(task))
1859 task_set_spec_ssb_disable(task);
1860 task_set_spec_ssb_noexec(task);
1861 task_update_spec_tif(task);
1869 static bool is_spec_ib_user_controlled(void)
1871 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1872 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1873 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1874 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1877 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1880 case PR_SPEC_ENABLE:
1881 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1882 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1886 * With strict mode for both IBPB and STIBP, the instruction
1887 * code paths avoid checking this task flag and instead,
1888 * unconditionally run the instruction. However, STIBP and IBPB
1889 * are independent and either can be set to conditionally
1890 * enabled regardless of the mode of the other.
1892 * If either is set to conditional, allow the task flag to be
1893 * updated, unless it was force-disabled by a previous prctl
1894 * call. Currently, this is possible on an AMD CPU which has the
1895 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1896 * kernel is booted with 'spectre_v2_user=seccomp', then
1897 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1898 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1900 if (!is_spec_ib_user_controlled() ||
1901 task_spec_ib_force_disable(task))
1904 task_clear_spec_ib_disable(task);
1905 task_update_spec_tif(task);
1907 case PR_SPEC_DISABLE:
1908 case PR_SPEC_FORCE_DISABLE:
1910 * Indirect branch speculation is always allowed when
1911 * mitigation is force disabled.
1913 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1914 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1917 if (!is_spec_ib_user_controlled())
1920 task_set_spec_ib_disable(task);
1921 if (ctrl == PR_SPEC_FORCE_DISABLE)
1922 task_set_spec_ib_force_disable(task);
1923 task_update_spec_tif(task);
1931 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1935 case PR_SPEC_STORE_BYPASS:
1936 return ssb_prctl_set(task, ctrl);
1937 case PR_SPEC_INDIRECT_BRANCH:
1938 return ib_prctl_set(task, ctrl);
1939 case PR_SPEC_L1D_FLUSH:
1940 return l1d_flush_prctl_set(task, ctrl);
1946 #ifdef CONFIG_SECCOMP
1947 void arch_seccomp_spec_mitigate(struct task_struct *task)
1949 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1950 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1951 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1952 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1953 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1957 static int l1d_flush_prctl_get(struct task_struct *task)
1959 if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1960 return PR_SPEC_FORCE_DISABLE;
1962 if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
1963 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1965 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1968 static int ssb_prctl_get(struct task_struct *task)
1971 case SPEC_STORE_BYPASS_DISABLE:
1972 return PR_SPEC_DISABLE;
1973 case SPEC_STORE_BYPASS_SECCOMP:
1974 case SPEC_STORE_BYPASS_PRCTL:
1975 if (task_spec_ssb_force_disable(task))
1976 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1977 if (task_spec_ssb_noexec(task))
1978 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1979 if (task_spec_ssb_disable(task))
1980 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1981 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1983 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1984 return PR_SPEC_ENABLE;
1985 return PR_SPEC_NOT_AFFECTED;
1989 static int ib_prctl_get(struct task_struct *task)
1991 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1992 return PR_SPEC_NOT_AFFECTED;
1994 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1995 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1996 return PR_SPEC_ENABLE;
1997 else if (is_spec_ib_user_controlled()) {
1998 if (task_spec_ib_force_disable(task))
1999 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2000 if (task_spec_ib_disable(task))
2001 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2002 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2003 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
2004 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2005 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
2006 return PR_SPEC_DISABLE;
2008 return PR_SPEC_NOT_AFFECTED;
2011 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2014 case PR_SPEC_STORE_BYPASS:
2015 return ssb_prctl_get(task);
2016 case PR_SPEC_INDIRECT_BRANCH:
2017 return ib_prctl_get(task);
2018 case PR_SPEC_L1D_FLUSH:
2019 return l1d_flush_prctl_get(task);
2025 void x86_spec_ctrl_setup_ap(void)
2027 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2028 write_spec_ctrl_current(x86_spec_ctrl_base, true);
2030 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2031 x86_amd_ssb_disable();
2034 bool itlb_multihit_kvm_mitigation;
2035 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2038 #define pr_fmt(fmt) "L1TF: " fmt
2040 /* Default mitigation for L1TF-affected CPUs */
2041 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2042 #if IS_ENABLED(CONFIG_KVM_INTEL)
2043 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2045 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2046 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2049 * These CPUs all support 44bits physical address space internally in the
2050 * cache but CPUID can report a smaller number of physical address bits.
2052 * The L1TF mitigation uses the top most address bit for the inversion of
2053 * non present PTEs. When the installed memory reaches into the top most
2054 * address bit due to memory holes, which has been observed on machines
2055 * which report 36bits physical address bits and have 32G RAM installed,
2056 * then the mitigation range check in l1tf_select_mitigation() triggers.
2057 * This is a false positive because the mitigation is still possible due to
2058 * the fact that the cache uses 44bit internally. Use the cache bits
2059 * instead of the reported physical bits and adjust them on the affected
2060 * machines to 44bit if the reported bits are less than 44.
2062 static void override_cache_bits(struct cpuinfo_x86 *c)
2067 switch (c->x86_model) {
2068 case INTEL_FAM6_NEHALEM:
2069 case INTEL_FAM6_WESTMERE:
2070 case INTEL_FAM6_SANDYBRIDGE:
2071 case INTEL_FAM6_IVYBRIDGE:
2072 case INTEL_FAM6_HASWELL:
2073 case INTEL_FAM6_HASWELL_L:
2074 case INTEL_FAM6_HASWELL_G:
2075 case INTEL_FAM6_BROADWELL:
2076 case INTEL_FAM6_BROADWELL_G:
2077 case INTEL_FAM6_SKYLAKE_L:
2078 case INTEL_FAM6_SKYLAKE:
2079 case INTEL_FAM6_KABYLAKE_L:
2080 case INTEL_FAM6_KABYLAKE:
2081 if (c->x86_cache_bits < 44)
2082 c->x86_cache_bits = 44;
2087 static void __init l1tf_select_mitigation(void)
2091 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2094 if (cpu_mitigations_off())
2095 l1tf_mitigation = L1TF_MITIGATION_OFF;
2096 else if (cpu_mitigations_auto_nosmt())
2097 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2099 override_cache_bits(&boot_cpu_data);
2101 switch (l1tf_mitigation) {
2102 case L1TF_MITIGATION_OFF:
2103 case L1TF_MITIGATION_FLUSH_NOWARN:
2104 case L1TF_MITIGATION_FLUSH:
2106 case L1TF_MITIGATION_FLUSH_NOSMT:
2107 case L1TF_MITIGATION_FULL:
2108 cpu_smt_disable(false);
2110 case L1TF_MITIGATION_FULL_FORCE:
2111 cpu_smt_disable(true);
2115 #if CONFIG_PGTABLE_LEVELS == 2
2116 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2120 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2121 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2122 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2123 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2124 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2126 pr_info("However, doing so will make a part of your RAM unusable.\n");
2127 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2131 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2134 static int __init l1tf_cmdline(char *str)
2136 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2142 if (!strcmp(str, "off"))
2143 l1tf_mitigation = L1TF_MITIGATION_OFF;
2144 else if (!strcmp(str, "flush,nowarn"))
2145 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2146 else if (!strcmp(str, "flush"))
2147 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2148 else if (!strcmp(str, "flush,nosmt"))
2149 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2150 else if (!strcmp(str, "full"))
2151 l1tf_mitigation = L1TF_MITIGATION_FULL;
2152 else if (!strcmp(str, "full,force"))
2153 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2157 early_param("l1tf", l1tf_cmdline);
2160 #define pr_fmt(fmt) fmt
2164 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2166 #if IS_ENABLED(CONFIG_KVM_INTEL)
2167 static const char * const l1tf_vmx_states[] = {
2168 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2169 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2170 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2171 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2172 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2173 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2176 static ssize_t l1tf_show_state(char *buf)
2178 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2179 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2181 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2182 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2183 sched_smt_active())) {
2184 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2185 l1tf_vmx_states[l1tf_vmx_mitigation]);
2188 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2189 l1tf_vmx_states[l1tf_vmx_mitigation],
2190 sched_smt_active() ? "vulnerable" : "disabled");
2193 static ssize_t itlb_multihit_show_state(char *buf)
2195 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2196 !boot_cpu_has(X86_FEATURE_VMX))
2197 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2198 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2199 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2200 else if (itlb_multihit_kvm_mitigation)
2201 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2203 return sprintf(buf, "KVM: Vulnerable\n");
2206 static ssize_t l1tf_show_state(char *buf)
2208 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2211 static ssize_t itlb_multihit_show_state(char *buf)
2213 return sprintf(buf, "Processor vulnerable\n");
2217 static ssize_t mds_show_state(char *buf)
2219 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2220 return sprintf(buf, "%s; SMT Host state unknown\n",
2221 mds_strings[mds_mitigation]);
2224 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2225 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2226 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2227 sched_smt_active() ? "mitigated" : "disabled"));
2230 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2231 sched_smt_active() ? "vulnerable" : "disabled");
2234 static ssize_t tsx_async_abort_show_state(char *buf)
2236 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2237 (taa_mitigation == TAA_MITIGATION_OFF))
2238 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2240 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2241 return sprintf(buf, "%s; SMT Host state unknown\n",
2242 taa_strings[taa_mitigation]);
2245 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2246 sched_smt_active() ? "vulnerable" : "disabled");
2249 static ssize_t mmio_stale_data_show_state(char *buf)
2251 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2252 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2254 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2255 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2256 mmio_strings[mmio_mitigation]);
2259 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2260 sched_smt_active() ? "vulnerable" : "disabled");
2263 static char *stibp_state(void)
2265 if (spectre_v2_in_ibrs_mode(spectre_v2_enabled))
2268 switch (spectre_v2_user_stibp) {
2269 case SPECTRE_V2_USER_NONE:
2270 return ", STIBP: disabled";
2271 case SPECTRE_V2_USER_STRICT:
2272 return ", STIBP: forced";
2273 case SPECTRE_V2_USER_STRICT_PREFERRED:
2274 return ", STIBP: always-on";
2275 case SPECTRE_V2_USER_PRCTL:
2276 case SPECTRE_V2_USER_SECCOMP:
2277 if (static_key_enabled(&switch_to_cond_stibp))
2278 return ", STIBP: conditional";
2283 static char *ibpb_state(void)
2285 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2286 if (static_key_enabled(&switch_mm_always_ibpb))
2287 return ", IBPB: always-on";
2288 if (static_key_enabled(&switch_mm_cond_ibpb))
2289 return ", IBPB: conditional";
2290 return ", IBPB: disabled";
2295 static ssize_t spectre_v2_show_state(char *buf)
2297 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2298 return sprintf(buf, "Vulnerable: LFENCE\n");
2300 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2301 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2303 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2304 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2305 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2307 return sprintf(buf, "%s%s%s%s%s%s\n",
2308 spectre_v2_strings[spectre_v2_enabled],
2310 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2312 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2313 spectre_v2_module_string());
2316 static ssize_t srbds_show_state(char *buf)
2318 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2321 static ssize_t retbleed_show_state(char *buf)
2323 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
2324 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2325 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2326 return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen uarch\n");
2328 return sprintf(buf, "%s; SMT %s\n",
2329 retbleed_strings[retbleed_mitigation],
2330 !sched_smt_active() ? "disabled" :
2331 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2332 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2333 "enabled with STIBP protection" : "vulnerable");
2336 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2339 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2340 char *buf, unsigned int bug)
2342 if (!boot_cpu_has_bug(bug))
2343 return sprintf(buf, "Not affected\n");
2346 case X86_BUG_CPU_MELTDOWN:
2347 if (boot_cpu_has(X86_FEATURE_PTI))
2348 return sprintf(buf, "Mitigation: PTI\n");
2350 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2351 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2355 case X86_BUG_SPECTRE_V1:
2356 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2358 case X86_BUG_SPECTRE_V2:
2359 return spectre_v2_show_state(buf);
2361 case X86_BUG_SPEC_STORE_BYPASS:
2362 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2365 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2366 return l1tf_show_state(buf);
2370 return mds_show_state(buf);
2373 return tsx_async_abort_show_state(buf);
2375 case X86_BUG_ITLB_MULTIHIT:
2376 return itlb_multihit_show_state(buf);
2379 return srbds_show_state(buf);
2381 case X86_BUG_MMIO_STALE_DATA:
2382 return mmio_stale_data_show_state(buf);
2384 case X86_BUG_RETBLEED:
2385 return retbleed_show_state(buf);
2391 return sprintf(buf, "Vulnerable\n");
2394 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2396 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2399 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2401 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2404 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2406 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2409 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2411 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2414 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2416 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2419 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2421 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2424 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2426 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2429 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2431 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2434 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2436 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2439 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2441 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2444 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2446 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);