arch/x86/kernel/cpu/bugs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1994  Linus Torvalds
   4  *
   5  *  Cyrix stuff, June 1998 by:
   6  *      - Rafael R. Reilova (moved everything from head.S),
   7  *        <rreilova@ececs.uc.edu>
   8  *      - Channing Corn (tests & fixes),
   9  *      - Andrew D. Balsa (code cleanup).
  10  */
  11 #include <linux/init.h>
  12 #include <linux/utsname.h>
  13 #include <linux/cpu.h>
  14 #include <linux/module.h>
  15 #include <linux/nospec.h>
  16 #include <linux/prctl.h>
  17 #include <linux/sched/smt.h>
  18 #include <linux/pgtable.h>
  19 #include <linux/bpf.h>
  20
  21 #include <asm/spec-ctrl.h>
  22 #include <asm/cmdline.h>
  23 #include <asm/bugs.h>
  24 #include <asm/processor.h>
  25 #include <asm/processor-flags.h>
  26 #include <asm/fpu/api.h>
  27 #include <asm/msr.h>
  28 #include <asm/vmx.h>
  29 #include <asm/paravirt.h>
  30 #include <asm/alternative.h>
  31 #include <asm/set_memory.h>
  32 #include <asm/intel-family.h>
  33 #include <asm/e820/api.h>
  34 #include <asm/hypervisor.h>
  35 #include <asm/tlbflush.h>
  36
  37 #include "cpu.h"
  38
  39 static void __init spectre_v1_select_mitigation(void);
  40 static void __init spectre_v2_select_mitigation(void);
  41 static void __init retbleed_select_mitigation(void);
  42 static void __init spectre_v2_user_select_mitigation(void);
  43 static void __init ssb_select_mitigation(void);
  44 static void __init l1tf_select_mitigation(void);
  45 static void __init mds_select_mitigation(void);
  46 static void __init md_clear_update_mitigation(void);
  47 static void __init md_clear_select_mitigation(void);
  48 static void __init taa_select_mitigation(void);
  49 static void __init mmio_select_mitigation(void);
  50 static void __init srbds_select_mitigation(void);
  51 static void __init l1d_flush_select_mitigation(void);
  52
  53 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
  54 u64 x86_spec_ctrl_base;
  55 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
  56
  57 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
  58 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
  59 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
  60
  61 static DEFINE_MUTEX(spec_ctrl_mutex);
  62
  63 /*
  64  * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
  65  * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
  66  */
  67 void write_spec_ctrl_current(u64 val, bool force)
  68 {
  69         if (this_cpu_read(x86_spec_ctrl_current) == val)
  70                 return;
  71
  72         this_cpu_write(x86_spec_ctrl_current, val);
  73
  74         /*
  75          * When KERNEL_IBRS this MSR is written on return-to-user, unless
  76          * forced the update can be delayed until that time.
  77          */
  78         if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
  79                 wrmsrl(MSR_IA32_SPEC_CTRL, val);
  80 }
  81
  82 u64 spec_ctrl_current(void)
  83 {
  84         return this_cpu_read(x86_spec_ctrl_current);
  85 }
  86 EXPORT_SYMBOL_GPL(spec_ctrl_current);
  87
  88 /*
  89  * The vendor and possibly platform specific bits which can be modified in
  90  * x86_spec_ctrl_base.
  91  */
  92 static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
  93
  94 /*
  95  * AMD specific MSR info for Speculative Store Bypass control.
  96  * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
  97  */
  98 u64 __ro_after_init x86_amd_ls_cfg_base;
  99 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
 100
 101 /* Control conditional STIBP in switch_to() */
 102 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 103 /* Control conditional IBPB in switch_mm() */
 104 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 105 /* Control unconditional IBPB in switch_mm() */
 106 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 107
 108 /* Control MDS CPU buffer clear before returning to user space */
 109 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
 110 EXPORT_SYMBOL_GPL(mds_user_clear);
 111 /* Control MDS CPU buffer clear before idling (halt, mwait) */
 112 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
 113 EXPORT_SYMBOL_GPL(mds_idle_clear);
 114
 115 /*
 116  * Controls whether l1d flush based mitigations are enabled,
 117  * based on hw features and admin setting via boot parameter
 118  * defaults to false
 119  */
 120 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 121
 122 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
 123 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 124 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
 125
 126 void __init check_bugs(void)
 127 {
 128         identify_boot_cpu();
 129
 130         /*
 131          * identify_boot_cpu() initialized SMT support information, let the
 132          * core code know.
 133          */
 134         cpu_smt_check_topology();
 135
 136         if (!IS_ENABLED(CONFIG_SMP)) {
 137                 pr_info("CPU: ");
 138                 print_cpu_info(&boot_cpu_data);
 139         }
 140
 141         /*
 142          * Read the SPEC_CTRL MSR to account for reserved bits which may
 143          * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
 144          * init code as it is not enumerated and depends on the family.
 145          */
 146         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
 147                 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
 148
 149         /* Allow STIBP in MSR_SPEC_CTRL if supported */
 150         if (boot_cpu_has(X86_FEATURE_STIBP))
 151                 x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
 152
 153         /* Select the proper CPU mitigations before patching alternatives: */
 154         spectre_v1_select_mitigation();
 155         spectre_v2_select_mitigation();
 156         /*
 157          * retbleed_select_mitigation() relies on the state set by
 158          * spectre_v2_select_mitigation(); specifically it wants to know about
 159          * spectre_v2=ibrs.
 160          */
 161         retbleed_select_mitigation();
 162         /*
 163          * spectre_v2_user_select_mitigation() relies on the state set by
 164          * retbleed_select_mitigation(); specifically the STIBP selection is
 165          * forced for UNRET.
 166          */
 167         spectre_v2_user_select_mitigation();
 168         ssb_select_mitigation();
 169         l1tf_select_mitigation();
 170         md_clear_select_mitigation();
 171         srbds_select_mitigation();
 172         l1d_flush_select_mitigation();
 173
 174         arch_smt_update();
 175
 176 #ifdef CONFIG_X86_32
 177         /*
 178          * Check whether we are able to run this kernel safely on SMP.
 179          *
 180          * - i386 is no longer supported.
 181          * - In order to run on anything without a TSC, we need to be
 182          *   compiled for a i486.
 183          */
 184         if (boot_cpu_data.x86 < 4)
 185                 panic("Kernel requires i486+ for 'invlpg' and other features");
 186
 187         init_utsname()->machine[1] =
 188                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
 189         alternative_instructions();
 190
 191         fpu__init_check_bugs();
 192 #else /* CONFIG_X86_64 */
 193         alternative_instructions();
 194
 195         /*
 196          * Make sure the first 2MB area is not mapped by huge pages
 197          * There are typically fixed size MTRRs in there and overlapping
 198          * MTRRs into large pages causes slow downs.
 199          *
 200          * Right now we don't do that with gbpages because there seems
 201          * very little benefit for that case.
 202          */
 203         if (!direct_gbpages)
 204                 set_memory_4k((unsigned long)__va(0), 1);
 205 #endif
 206 }
 207
 208 void
 209 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
 210 {
 211         u64 msrval, guestval, hostval = x86_spec_ctrl_base;
 212         struct thread_info *ti = current_thread_info();
 213
 214         /* Is MSR_SPEC_CTRL implemented ? */
 215         if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
 216                 /*
 217                  * Restrict guest_spec_ctrl to supported values. Clear the
 218                  * modifiable bits in the host base value and or the
 219                  * modifiable bits from the guest value.
 220                  */
 221                 guestval = hostval & ~x86_spec_ctrl_mask;
 222                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
 223
 224                 /* SSBD controlled in MSR_SPEC_CTRL */
 225                 if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 226                     static_cpu_has(X86_FEATURE_AMD_SSBD))
 227                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
 228
 229                 /* Conditional STIBP enabled? */
 230                 if (static_branch_unlikely(&switch_to_cond_stibp))
 231                         hostval |= stibp_tif_to_spec_ctrl(ti->flags);
 232
 233                 if (hostval != guestval) {
 234                         msrval = setguest ? guestval : hostval;
 235                         wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
 236                 }
 237         }
 238
 239         /*
 240          * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
 241          * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
 242          */
 243         if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
 244             !static_cpu_has(X86_FEATURE_VIRT_SSBD))
 245                 return;
 246
 247         /*
 248          * If the host has SSBD mitigation enabled, force it in the host's
 249          * virtual MSR value. If its not permanently enabled, evaluate
 250          * current's TIF_SSBD thread flag.
 251          */
 252         if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
 253                 hostval = SPEC_CTRL_SSBD;
 254         else
 255                 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
 256
 257         /* Sanitize the guest value */
 258         guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
 259
 260         if (hostval != guestval) {
 261                 unsigned long tif;
 262
 263                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
 264                                  ssbd_spec_ctrl_to_tif(hostval);
 265
 266                 speculation_ctrl_update(tif);
 267         }
 268 }
 269 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
 270
 271 static void x86_amd_ssb_disable(void)
 272 {
 273         u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
 274
 275         if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
 276                 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
 277         else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 278                 wrmsrl(MSR_AMD64_LS_CFG, msrval);
 279 }
 280
 281 #undef pr_fmt
 282 #define pr_fmt(fmt)     "MDS: " fmt
 283
 284 /* Default mitigation for MDS-affected CPUs */
 285 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
 286 static bool mds_nosmt __ro_after_init = false;
 287
 288 static const char * const mds_strings[] = {
 289         [MDS_MITIGATION_OFF]    = "Vulnerable",
 290         [MDS_MITIGATION_FULL]   = "Mitigation: Clear CPU buffers",
 291         [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
 292 };
 293
 294 static void __init mds_select_mitigation(void)
 295 {
 296         if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
 297                 mds_mitigation = MDS_MITIGATION_OFF;
 298                 return;
 299         }
 300
 301         if (mds_mitigation == MDS_MITIGATION_FULL) {
 302                 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
 303                         mds_mitigation = MDS_MITIGATION_VMWERV;
 304
 305                 static_branch_enable(&mds_user_clear);
 306
 307                 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
 308                     (mds_nosmt || cpu_mitigations_auto_nosmt()))
 309                         cpu_smt_disable(false);
 310         }
 311 }
 312
 313 static int __init mds_cmdline(char *str)
 314 {
 315         if (!boot_cpu_has_bug(X86_BUG_MDS))
 316                 return 0;
 317
 318         if (!str)
 319                 return -EINVAL;
 320
 321         if (!strcmp(str, "off"))
 322                 mds_mitigation = MDS_MITIGATION_OFF;
 323         else if (!strcmp(str, "full"))
 324                 mds_mitigation = MDS_MITIGATION_FULL;
 325         else if (!strcmp(str, "full,nosmt")) {
 326                 mds_mitigation = MDS_MITIGATION_FULL;
 327                 mds_nosmt = true;
 328         }
 329
 330         return 0;
 331 }
 332 early_param("mds", mds_cmdline);
 333
 334 #undef pr_fmt
 335 #define pr_fmt(fmt)     "TAA: " fmt
 336
 337 enum taa_mitigations {
 338         TAA_MITIGATION_OFF,
 339         TAA_MITIGATION_UCODE_NEEDED,
 340         TAA_MITIGATION_VERW,
 341         TAA_MITIGATION_TSX_DISABLED,
 342 };
 343
 344 /* Default mitigation for TAA-affected CPUs */
 345 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
 346 static bool taa_nosmt __ro_after_init;
 347
 348 static const char * const taa_strings[] = {
 349         [TAA_MITIGATION_OFF]            = "Vulnerable",
 350         [TAA_MITIGATION_UCODE_NEEDED]   = "Vulnerable: Clear CPU buffers attempted, no microcode",
 351         [TAA_MITIGATION_VERW]           = "Mitigation: Clear CPU buffers",
 352         [TAA_MITIGATION_TSX_DISABLED]   = "Mitigation: TSX disabled",
 353 };
 354
 355 static void __init taa_select_mitigation(void)
 356 {
 357         u64 ia32_cap;
 358
 359         if (!boot_cpu_has_bug(X86_BUG_TAA)) {
 360                 taa_mitigation = TAA_MITIGATION_OFF;
 361                 return;
 362         }
 363
 364         /* TSX previously disabled by tsx=off */
 365         if (!boot_cpu_has(X86_FEATURE_RTM)) {
 366                 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
 367                 return;
 368         }
 369
 370         if (cpu_mitigations_off()) {
 371                 taa_mitigation = TAA_MITIGATION_OFF;
 372                 return;
 373         }
 374
 375         /*
 376          * TAA mitigation via VERW is turned off if both
 377          * tsx_async_abort=off and mds=off are specified.
 378          */
 379         if (taa_mitigation == TAA_MITIGATION_OFF &&
 380             mds_mitigation == MDS_MITIGATION_OFF)
 381                 return;
 382
 383         if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
 384                 taa_mitigation = TAA_MITIGATION_VERW;
 385         else
 386                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 387
 388         /*
 389          * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
 390          * A microcode update fixes this behavior to clear CPU buffers. It also
 391          * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
 392          * ARCH_CAP_TSX_CTRL_MSR bit.
 393          *
 394          * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
 395          * update is required.
 396          */
 397         ia32_cap = x86_read_arch_cap_msr();
 398         if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
 399             !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
 400                 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
 401
 402         /*
 403          * TSX is enabled, select alternate mitigation for TAA which is
 404          * the same as MDS. Enable MDS static branch to clear CPU buffers.
 405          *
 406          * For guests that can't determine whether the correct microcode is
 407          * present on host, enable the mitigation for UCODE_NEEDED as well.
 408          */
 409         static_branch_enable(&mds_user_clear);
 410
 411         if (taa_nosmt || cpu_mitigations_auto_nosmt())
 412                 cpu_smt_disable(false);
 413 }
 414
 415 static int __init tsx_async_abort_parse_cmdline(char *str)
 416 {
 417         if (!boot_cpu_has_bug(X86_BUG_TAA))
 418                 return 0;
 419
 420         if (!str)
 421                 return -EINVAL;
 422
 423         if (!strcmp(str, "off")) {
 424                 taa_mitigation = TAA_MITIGATION_OFF;
 425         } else if (!strcmp(str, "full")) {
 426                 taa_mitigation = TAA_MITIGATION_VERW;
 427         } else if (!strcmp(str, "full,nosmt")) {
 428                 taa_mitigation = TAA_MITIGATION_VERW;
 429                 taa_nosmt = true;
 430         }
 431
 432         return 0;
 433 }
 434 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
 435
 436 #undef pr_fmt
 437 #define pr_fmt(fmt)     "MMIO Stale Data: " fmt
 438
 439 enum mmio_mitigations {
 440         MMIO_MITIGATION_OFF,
 441         MMIO_MITIGATION_UCODE_NEEDED,
 442         MMIO_MITIGATION_VERW,
 443 };
 444
 445 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
 446 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
 447 static bool mmio_nosmt __ro_after_init = false;
 448
 449 static const char * const mmio_strings[] = {
 450         [MMIO_MITIGATION_OFF]           = "Vulnerable",
 451         [MMIO_MITIGATION_UCODE_NEEDED]  = "Vulnerable: Clear CPU buffers attempted, no microcode",
 452         [MMIO_MITIGATION_VERW]          = "Mitigation: Clear CPU buffers",
 453 };
 454
 455 static void __init mmio_select_mitigation(void)
 456 {
 457         u64 ia32_cap;
 458
 459         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
 460             cpu_mitigations_off()) {
 461                 mmio_mitigation = MMIO_MITIGATION_OFF;
 462                 return;
 463         }
 464
 465         if (mmio_mitigation == MMIO_MITIGATION_OFF)
 466                 return;
 467
 468         ia32_cap = x86_read_arch_cap_msr();
 469
 470         /*
 471          * Enable CPU buffer clear mitigation for host and VMM, if also affected
 472          * by MDS or TAA. Otherwise, enable mitigation for VMM only.
 473          */
 474         if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
 475                                               boot_cpu_has(X86_FEATURE_RTM)))
 476                 static_branch_enable(&mds_user_clear);
 477         else
 478                 static_branch_enable(&mmio_stale_data_clear);
 479
 480         /*
 481          * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
 482          * be propagated to uncore buffers, clearing the Fill buffers on idle
 483          * is required irrespective of SMT state.
 484          */
 485         if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
 486                 static_branch_enable(&mds_idle_clear);
 487
 488         /*
 489          * Check if the system has the right microcode.
 490          *
 491          * CPU Fill buffer clear mitigation is enumerated by either an explicit
 492          * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
 493          * affected systems.
 494          */
 495         if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
 496             (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
 497              boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
 498              !(ia32_cap & ARCH_CAP_MDS_NO)))
 499                 mmio_mitigation = MMIO_MITIGATION_VERW;
 500         else
 501                 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
 502
 503         if (mmio_nosmt || cpu_mitigations_auto_nosmt())
 504                 cpu_smt_disable(false);
 505 }
 506
 507 static int __init mmio_stale_data_parse_cmdline(char *str)
 508 {
 509         if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 510                 return 0;
 511
 512         if (!str)
 513                 return -EINVAL;
 514
 515         if (!strcmp(str, "off")) {
 516                 mmio_mitigation = MMIO_MITIGATION_OFF;
 517         } else if (!strcmp(str, "full")) {
 518                 mmio_mitigation = MMIO_MITIGATION_VERW;
 519         } else if (!strcmp(str, "full,nosmt")) {
 520                 mmio_mitigation = MMIO_MITIGATION_VERW;
 521                 mmio_nosmt = true;
 522         }
 523
 524         return 0;
 525 }
 526 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
 527
 528 #undef pr_fmt
 529 #define pr_fmt(fmt)     "" fmt
 530
 531 static void __init md_clear_update_mitigation(void)
 532 {
 533         if (cpu_mitigations_off())
 534                 return;
 535
 536         if (!static_key_enabled(&mds_user_clear))
 537                 goto out;
 538
 539         /*
 540          * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
 541          * mitigation, if necessary.
 542          */
 543         if (mds_mitigation == MDS_MITIGATION_OFF &&
 544             boot_cpu_has_bug(X86_BUG_MDS)) {
 545                 mds_mitigation = MDS_MITIGATION_FULL;
 546                 mds_select_mitigation();
 547         }
 548         if (taa_mitigation == TAA_MITIGATION_OFF &&
 549             boot_cpu_has_bug(X86_BUG_TAA)) {
 550                 taa_mitigation = TAA_MITIGATION_VERW;
 551                 taa_select_mitigation();
 552         }
 553         if (mmio_mitigation == MMIO_MITIGATION_OFF &&
 554             boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
 555                 mmio_mitigation = MMIO_MITIGATION_VERW;
 556                 mmio_select_mitigation();
 557         }
 558 out:
 559         if (boot_cpu_has_bug(X86_BUG_MDS))
 560                 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
 561         if (boot_cpu_has_bug(X86_BUG_TAA))
 562                 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
 563         if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 564                 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
 565 }
 566
 567 static void __init md_clear_select_mitigation(void)
 568 {
 569         mds_select_mitigation();
 570         taa_select_mitigation();
 571         mmio_select_mitigation();
 572
 573         /*
 574          * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
 575          * and print their mitigation after MDS, TAA and MMIO Stale Data
 576          * mitigation selection is done.
 577          */
 578         md_clear_update_mitigation();
 579 }
 580
 581 #undef pr_fmt
 582 #define pr_fmt(fmt)     "SRBDS: " fmt
 583
 584 enum srbds_mitigations {
 585         SRBDS_MITIGATION_OFF,
 586         SRBDS_MITIGATION_UCODE_NEEDED,
 587         SRBDS_MITIGATION_FULL,
 588         SRBDS_MITIGATION_TSX_OFF,
 589         SRBDS_MITIGATION_HYPERVISOR,
 590 };
 591
 592 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 593
 594 static const char * const srbds_strings[] = {
 595         [SRBDS_MITIGATION_OFF]          = "Vulnerable",
 596         [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
 597         [SRBDS_MITIGATION_FULL]         = "Mitigation: Microcode",
 598         [SRBDS_MITIGATION_TSX_OFF]      = "Mitigation: TSX disabled",
 599         [SRBDS_MITIGATION_HYPERVISOR]   = "Unknown: Dependent on hypervisor status",
 600 };
 601
 602 static bool srbds_off;
 603
 604 void update_srbds_msr(void)
 605 {
 606         u64 mcu_ctrl;
 607
 608         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 609                 return;
 610
 611         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 612                 return;
 613
 614         if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
 615                 return;
 616
 617         /*
 618          * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
 619          * being disabled and it hasn't received the SRBDS MSR microcode.
 620          */
 621         if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 622                 return;
 623
 624         rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 625
 626         switch (srbds_mitigation) {
 627         case SRBDS_MITIGATION_OFF:
 628         case SRBDS_MITIGATION_TSX_OFF:
 629                 mcu_ctrl |= RNGDS_MITG_DIS;
 630                 break;
 631         case SRBDS_MITIGATION_FULL:
 632                 mcu_ctrl &= ~RNGDS_MITG_DIS;
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
 639 }
 640
 641 static void __init srbds_select_mitigation(void)
 642 {
 643         u64 ia32_cap;
 644
 645         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 646                 return;
 647
 648         /*
 649          * Check to see if this is one of the MDS_NO systems supporting TSX that
 650          * are only exposed to SRBDS when TSX is enabled or when CPU is affected
 651          * by Processor MMIO Stale Data vulnerability.
 652          */
 653         ia32_cap = x86_read_arch_cap_msr();
 654         if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
 655             !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
 656                 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
 657         else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 658                 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
 659         else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 660                 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
 661         else if (cpu_mitigations_off() || srbds_off)
 662                 srbds_mitigation = SRBDS_MITIGATION_OFF;
 663
 664         update_srbds_msr();
 665         pr_info("%s\n", srbds_strings[srbds_mitigation]);
 666 }
 667
 668 static int __init srbds_parse_cmdline(char *str)
 669 {
 670         if (!str)
 671                 return -EINVAL;
 672
 673         if (!boot_cpu_has_bug(X86_BUG_SRBDS))
 674                 return 0;
 675
 676         srbds_off = !strcmp(str, "off");
 677         return 0;
 678 }
 679 early_param("srbds", srbds_parse_cmdline);
 680
 681 #undef pr_fmt
 682 #define pr_fmt(fmt)     "L1D Flush : " fmt
 683
 684 enum l1d_flush_mitigations {
 685         L1D_FLUSH_OFF = 0,
 686         L1D_FLUSH_ON,
 687 };
 688
 689 static enum l1d_flush_mitigations l1d_flush_mitigation __initdata = L1D_FLUSH_OFF;
 690
 691 static void __init l1d_flush_select_mitigation(void)
 692 {
 693         if (!l1d_flush_mitigation || !boot_cpu_has(X86_FEATURE_FLUSH_L1D))
 694                 return;
 695
 696         static_branch_enable(&switch_mm_cond_l1d_flush);
 697         pr_info("Conditional flush on switch_mm() enabled\n");
 698 }
 699
 700 static int __init l1d_flush_parse_cmdline(char *str)
 701 {
 702         if (!strcmp(str, "on"))
 703                 l1d_flush_mitigation = L1D_FLUSH_ON;
 704
 705         return 0;
 706 }
 707 early_param("l1d_flush", l1d_flush_parse_cmdline);
 708
 709 #undef pr_fmt
 710 #define pr_fmt(fmt)     "Spectre V1 : " fmt
 711
 712 enum spectre_v1_mitigation {
 713         SPECTRE_V1_MITIGATION_NONE,
 714         SPECTRE_V1_MITIGATION_AUTO,
 715 };
 716
 717 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
 718         SPECTRE_V1_MITIGATION_AUTO;
 719
 720 static const char * const spectre_v1_strings[] = {
 721         [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
 722         [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
 723 };
 724
 725 /*
 726  * Does SMAP provide full mitigation against speculative kernel access to
 727  * userspace?
 728  */
 729 static bool smap_works_speculatively(void)
 730 {
 731         if (!boot_cpu_has(X86_FEATURE_SMAP))
 732                 return false;
 733
 734         /*
 735          * On CPUs which are vulnerable to Meltdown, SMAP does not
 736          * prevent speculative access to user data in the L1 cache.
 737          * Consider SMAP to be non-functional as a mitigation on these
 738          * CPUs.
 739          */
 740         if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
 741                 return false;
 742
 743         return true;
 744 }
 745
 746 static void __init spectre_v1_select_mitigation(void)
 747 {
 748         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
 749                 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 750                 return;
 751         }
 752
 753         if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
 754                 /*
 755                  * With Spectre v1, a user can speculatively control either
 756                  * path of a conditional swapgs with a user-controlled GS
 757                  * value.  The mitigation is to add lfences to both code paths.
 758                  *
 759                  * If FSGSBASE is enabled, the user can put a kernel address in
 760                  * GS, in which case SMAP provides no protection.
 761                  *
 762                  * If FSGSBASE is disabled, the user can only put a user space
 763                  * address in GS.  That makes an attack harder, but still
 764                  * possible if there's no SMAP protection.
 765                  */
 766                 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
 767                     !smap_works_speculatively()) {
 768                         /*
 769                          * Mitigation can be provided from SWAPGS itself or
 770                          * PTI as the CR3 write in the Meltdown mitigation
 771                          * is serializing.
 772                          *
 773                          * If neither is there, mitigate with an LFENCE to
 774                          * stop speculation through swapgs.
 775                          */
 776                         if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
 777                             !boot_cpu_has(X86_FEATURE_PTI))
 778                                 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
 779
 780                         /*
 781                          * Enable lfences in the kernel entry (non-swapgs)
 782                          * paths, to prevent user entry from speculatively
 783                          * skipping swapgs.
 784                          */
 785                         setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
 786                 }
 787         }
 788
 789         pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
 790 }
 791
 792 static int __init nospectre_v1_cmdline(char *str)
 793 {
 794         spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
 795         return 0;
 796 }
 797 early_param("nospectre_v1", nospectre_v1_cmdline);
 798
 799 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
 800         SPECTRE_V2_NONE;
 801
 802 #undef pr_fmt
 803 #define pr_fmt(fmt)     "RETBleed: " fmt
 804
 805 enum retbleed_mitigation {
 806         RETBLEED_MITIGATION_NONE,
 807         RETBLEED_MITIGATION_UNRET,
 808         RETBLEED_MITIGATION_IBPB,
 809         RETBLEED_MITIGATION_IBRS,
 810         RETBLEED_MITIGATION_EIBRS,
 811 };
 812
 813 enum retbleed_mitigation_cmd {
 814         RETBLEED_CMD_OFF,
 815         RETBLEED_CMD_AUTO,
 816         RETBLEED_CMD_UNRET,
 817         RETBLEED_CMD_IBPB,
 818 };
 819
 820 const char * const retbleed_strings[] = {
 821         [RETBLEED_MITIGATION_NONE]      = "Vulnerable",
 822         [RETBLEED_MITIGATION_UNRET]     = "Mitigation: untrained return thunk",
 823         [RETBLEED_MITIGATION_IBPB]      = "Mitigation: IBPB",
 824         [RETBLEED_MITIGATION_IBRS]      = "Mitigation: IBRS",
 825         [RETBLEED_MITIGATION_EIBRS]     = "Mitigation: Enhanced IBRS",
 826 };
 827
 828 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
 829         RETBLEED_MITIGATION_NONE;
 830 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
 831         RETBLEED_CMD_AUTO;
 832
 833 static int __ro_after_init retbleed_nosmt = false;
 834
 835 static int __init retbleed_parse_cmdline(char *str)
 836 {
 837         if (!str)
 838                 return -EINVAL;
 839
 840         while (str) {
 841                 char *next = strchr(str, ',');
 842                 if (next) {
 843                         *next = 0;
 844                         next++;
 845                 }
 846
 847                 if (!strcmp(str, "off")) {
 848                         retbleed_cmd = RETBLEED_CMD_OFF;
 849                 } else if (!strcmp(str, "auto")) {
 850                         retbleed_cmd = RETBLEED_CMD_AUTO;
 851                 } else if (!strcmp(str, "unret")) {
 852                         retbleed_cmd = RETBLEED_CMD_UNRET;
 853                 } else if (!strcmp(str, "ibpb")) {
 854                         retbleed_cmd = RETBLEED_CMD_IBPB;
 855                 } else if (!strcmp(str, "nosmt")) {
 856                         retbleed_nosmt = true;
 857                 } else {
 858                         pr_err("Ignoring unknown retbleed option (%s).", str);
 859                 }
 860
 861                 str = next;
 862         }
 863
 864         return 0;
 865 }
 866 early_param("retbleed", retbleed_parse_cmdline);
 867
 868 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
 869 #define RETBLEED_COMPILER_MSG "WARNING: kernel not compiled with RETPOLINE or -mfunction-return capable compiler; falling back to IBPB!\n"
 870 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
 871
 872 static void __init retbleed_select_mitigation(void)
 873 {
 874         bool mitigate_smt = false;
 875
 876         if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
 877                 return;
 878
 879         switch (retbleed_cmd) {
 880         case RETBLEED_CMD_OFF:
 881                 return;
 882
 883         case RETBLEED_CMD_UNRET:
 884                 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
 885                 break;
 886
 887         case RETBLEED_CMD_IBPB:
 888                 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
 889                 break;
 890
 891         case RETBLEED_CMD_AUTO:
 892         default:
 893                 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
 894                     boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
 895                         retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
 896
 897                 /*
 898                  * The Intel mitigation (IBRS or eIBRS) was already selected in
 899                  * spectre_v2_select_mitigation().  'retbleed_mitigation' will
 900                  * be set accordingly below.
 901                  */
 902
 903                 break;
 904         }
 905
 906         switch (retbleed_mitigation) {
 907         case RETBLEED_MITIGATION_UNRET:
 908
 909                 if (!IS_ENABLED(CONFIG_RETPOLINE) ||
 910                     !IS_ENABLED(CONFIG_CC_HAS_RETURN_THUNK)) {
 911                         pr_err(RETBLEED_COMPILER_MSG);
 912                         retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
 913                         goto retbleed_force_ibpb;
 914                 }
 915
 916                 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
 917                 setup_force_cpu_cap(X86_FEATURE_UNRET);
 918
 919                 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
 920                     boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
 921                         pr_err(RETBLEED_UNTRAIN_MSG);
 922
 923                 mitigate_smt = true;
 924                 break;
 925
 926         case RETBLEED_MITIGATION_IBPB:
 927 retbleed_force_ibpb:
 928                 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
 929                 mitigate_smt = true;
 930                 break;
 931
 932         default:
 933                 break;
 934         }
 935
 936         if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
 937             (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
 938                 cpu_smt_disable(false);
 939
 940         /*
 941          * Let IBRS trump all on Intel without affecting the effects of the
 942          * retbleed= cmdline option.
 943          */
 944         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
 945                 switch (spectre_v2_enabled) {
 946                 case SPECTRE_V2_IBRS:
 947                         retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
 948                         break;
 949                 case SPECTRE_V2_EIBRS:
 950                 case SPECTRE_V2_EIBRS_RETPOLINE:
 951                 case SPECTRE_V2_EIBRS_LFENCE:
 952                         retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
 953                         break;
 954                 default:
 955                         pr_err(RETBLEED_INTEL_MSG);
 956                 }
 957         }
 958
 959         pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
 960 }
 961
 962 #undef pr_fmt
 963 #define pr_fmt(fmt)     "Spectre V2 : " fmt
 964
 965 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
 966         SPECTRE_V2_USER_NONE;
 967 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
 968         SPECTRE_V2_USER_NONE;
 969
 970 #ifdef CONFIG_RETPOLINE
 971 static bool spectre_v2_bad_module;
 972
 973 bool retpoline_module_ok(bool has_retpoline)
 974 {
 975         if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
 976                 return true;
 977
 978         pr_err("System may be vulnerable to spectre v2\n");
 979         spectre_v2_bad_module = true;
 980         return false;
 981 }
 982
 983 static inline const char *spectre_v2_module_string(void)
 984 {
 985         return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
 986 }
 987 #else
 988 static inline const char *spectre_v2_module_string(void) { return ""; }
 989 #endif
 990
 991 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
 992 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
 993 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
 994
 995 #ifdef CONFIG_BPF_SYSCALL
 996 void unpriv_ebpf_notify(int new_state)
 997 {
 998         if (new_state)
 999                 return;
1000
1001         /* Unprivileged eBPF is enabled */
1002
1003         switch (spectre_v2_enabled) {
1004         case SPECTRE_V2_EIBRS:
1005                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1006                 break;
1007         case SPECTRE_V2_EIBRS_LFENCE:
1008                 if (sched_smt_active())
1009                         pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1010                 break;
1011         default:
1012                 break;
1013         }
1014 }
1015 #endif
1016
1017 static inline bool match_option(const char *arg, int arglen, const char *opt)
1018 {
1019         int len = strlen(opt);
1020
1021         return len == arglen && !strncmp(arg, opt, len);
1022 }
1023
1024 /* The kernel command line selection for spectre v2 */
1025 enum spectre_v2_mitigation_cmd {
1026         SPECTRE_V2_CMD_NONE,
1027         SPECTRE_V2_CMD_AUTO,
1028         SPECTRE_V2_CMD_FORCE,
1029         SPECTRE_V2_CMD_RETPOLINE,
1030         SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1031         SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1032         SPECTRE_V2_CMD_EIBRS,
1033         SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1034         SPECTRE_V2_CMD_EIBRS_LFENCE,
1035         SPECTRE_V2_CMD_IBRS,
1036 };
1037
1038 enum spectre_v2_user_cmd {
1039         SPECTRE_V2_USER_CMD_NONE,
1040         SPECTRE_V2_USER_CMD_AUTO,
1041         SPECTRE_V2_USER_CMD_FORCE,
1042         SPECTRE_V2_USER_CMD_PRCTL,
1043         SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1044         SPECTRE_V2_USER_CMD_SECCOMP,
1045         SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1046 };
1047
1048 static const char * const spectre_v2_user_strings[] = {
1049         [SPECTRE_V2_USER_NONE]                  = "User space: Vulnerable",
1050         [SPECTRE_V2_USER_STRICT]                = "User space: Mitigation: STIBP protection",
1051         [SPECTRE_V2_USER_STRICT_PREFERRED]      = "User space: Mitigation: STIBP always-on protection",
1052         [SPECTRE_V2_USER_PRCTL]                 = "User space: Mitigation: STIBP via prctl",
1053         [SPECTRE_V2_USER_SECCOMP]               = "User space: Mitigation: STIBP via seccomp and prctl",
1054 };
1055
1056 static const struct {
1057         const char                      *option;
1058         enum spectre_v2_user_cmd        cmd;
1059         bool                            secure;
1060 } v2_user_options[] __initconst = {
1061         { "auto",               SPECTRE_V2_USER_CMD_AUTO,               false },
1062         { "off",                SPECTRE_V2_USER_CMD_NONE,               false },
1063         { "on",                 SPECTRE_V2_USER_CMD_FORCE,              true  },
1064         { "prctl",              SPECTRE_V2_USER_CMD_PRCTL,              false },
1065         { "prctl,ibpb",         SPECTRE_V2_USER_CMD_PRCTL_IBPB,         false },
1066         { "seccomp",            SPECTRE_V2_USER_CMD_SECCOMP,            false },
1067         { "seccomp,ibpb",       SPECTRE_V2_USER_CMD_SECCOMP_IBPB,       false },
1068 };
1069
1070 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1071 {
1072         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1073                 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1074 }
1075
1076 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1077
1078 static enum spectre_v2_user_cmd __init
1079 spectre_v2_parse_user_cmdline(void)
1080 {
1081         char arg[20];
1082         int ret, i;
1083
1084         switch (spectre_v2_cmd) {
1085         case SPECTRE_V2_CMD_NONE:
1086                 return SPECTRE_V2_USER_CMD_NONE;
1087         case SPECTRE_V2_CMD_FORCE:
1088                 return SPECTRE_V2_USER_CMD_FORCE;
1089         default:
1090                 break;
1091         }
1092
1093         ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1094                                   arg, sizeof(arg));
1095         if (ret < 0)
1096                 return SPECTRE_V2_USER_CMD_AUTO;
1097
1098         for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1099                 if (match_option(arg, ret, v2_user_options[i].option)) {
1100                         spec_v2_user_print_cond(v2_user_options[i].option,
1101                                                 v2_user_options[i].secure);
1102                         return v2_user_options[i].cmd;
1103                 }
1104         }
1105
1106         pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1107         return SPECTRE_V2_USER_CMD_AUTO;
1108 }
1109
1110 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1111 {
1112         return mode == SPECTRE_V2_IBRS ||
1113                mode == SPECTRE_V2_EIBRS ||
1114                mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1115                mode == SPECTRE_V2_EIBRS_LFENCE;
1116 }
1117
1118 static void __init
1119 spectre_v2_user_select_mitigation(void)
1120 {
1121         enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1122         bool smt_possible = IS_ENABLED(CONFIG_SMP);
1123         enum spectre_v2_user_cmd cmd;
1124
1125         if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1126                 return;
1127
1128         if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1129             cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1130                 smt_possible = false;
1131
1132         cmd = spectre_v2_parse_user_cmdline();
1133         switch (cmd) {
1134         case SPECTRE_V2_USER_CMD_NONE:
1135                 goto set_mode;
1136         case SPECTRE_V2_USER_CMD_FORCE:
1137                 mode = SPECTRE_V2_USER_STRICT;
1138                 break;
1139         case SPECTRE_V2_USER_CMD_AUTO:
1140         case SPECTRE_V2_USER_CMD_PRCTL:
1141         case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1142                 mode = SPECTRE_V2_USER_PRCTL;
1143                 break;
1144         case SPECTRE_V2_USER_CMD_SECCOMP:
1145         case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1146                 if (IS_ENABLED(CONFIG_SECCOMP))
1147                         mode = SPECTRE_V2_USER_SECCOMP;
1148                 else
1149                         mode = SPECTRE_V2_USER_PRCTL;
1150                 break;
1151         }
1152
1153         /* Initialize Indirect Branch Prediction Barrier */
1154         if (boot_cpu_has(X86_FEATURE_IBPB)) {
1155                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1156
1157                 spectre_v2_user_ibpb = mode;
1158                 switch (cmd) {
1159                 case SPECTRE_V2_USER_CMD_FORCE:
1160                 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1161                 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1162                         static_branch_enable(&switch_mm_always_ibpb);
1163                         spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1164                         break;
1165                 case SPECTRE_V2_USER_CMD_PRCTL:
1166                 case SPECTRE_V2_USER_CMD_AUTO:
1167                 case SPECTRE_V2_USER_CMD_SECCOMP:
1168                         static_branch_enable(&switch_mm_cond_ibpb);
1169                         break;
1170                 default:
1171                         break;
1172                 }
1173
1174                 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1175                         static_key_enabled(&switch_mm_always_ibpb) ?
1176                         "always-on" : "conditional");
1177         }
1178
1179         /*
1180          * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible,
1181          * STIBP is not required.
1182          */
1183         if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1184             !smt_possible ||
1185             spectre_v2_in_ibrs_mode(spectre_v2_enabled))
1186                 return;
1187
1188         /*
1189          * At this point, an STIBP mode other than "off" has been set.
1190          * If STIBP support is not being forced, check if STIBP always-on
1191          * is preferred.
1192          */
1193         if (mode != SPECTRE_V2_USER_STRICT &&
1194             boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1195                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1196
1197         if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
1198                 if (mode != SPECTRE_V2_USER_STRICT &&
1199                     mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1200                         pr_info("Selecting STIBP always-on mode to complement retbleed mitigation'\n");
1201                 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1202         }
1203
1204         spectre_v2_user_stibp = mode;
1205
1206 set_mode:
1207         pr_info("%s\n", spectre_v2_user_strings[mode]);
1208 }
1209
1210 static const char * const spectre_v2_strings[] = {
1211         [SPECTRE_V2_NONE]                       = "Vulnerable",
1212         [SPECTRE_V2_RETPOLINE]                  = "Mitigation: Retpolines",
1213         [SPECTRE_V2_LFENCE]                     = "Mitigation: LFENCE",
1214         [SPECTRE_V2_EIBRS]                      = "Mitigation: Enhanced IBRS",
1215         [SPECTRE_V2_EIBRS_LFENCE]               = "Mitigation: Enhanced IBRS + LFENCE",
1216         [SPECTRE_V2_EIBRS_RETPOLINE]            = "Mitigation: Enhanced IBRS + Retpolines",
1217         [SPECTRE_V2_IBRS]                       = "Mitigation: IBRS",
1218 };
1219
1220 static const struct {
1221         const char *option;
1222         enum spectre_v2_mitigation_cmd cmd;
1223         bool secure;
1224 } mitigation_options[] __initconst = {
1225         { "off",                SPECTRE_V2_CMD_NONE,              false },
1226         { "on",                 SPECTRE_V2_CMD_FORCE,             true  },
1227         { "retpoline",          SPECTRE_V2_CMD_RETPOLINE,         false },
1228         { "retpoline,amd",      SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1229         { "retpoline,lfence",   SPECTRE_V2_CMD_RETPOLINE_LFENCE,  false },
1230         { "retpoline,generic",  SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1231         { "eibrs",              SPECTRE_V2_CMD_EIBRS,             false },
1232         { "eibrs,lfence",       SPECTRE_V2_CMD_EIBRS_LFENCE,      false },
1233         { "eibrs,retpoline",    SPECTRE_V2_CMD_EIBRS_RETPOLINE,   false },
1234         { "auto",               SPECTRE_V2_CMD_AUTO,              false },
1235         { "ibrs",               SPECTRE_V2_CMD_IBRS,              false },
1236 };
1237
1238 static void __init spec_v2_print_cond(const char *reason, bool secure)
1239 {
1240         if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1241                 pr_info("%s selected on command line.\n", reason);
1242 }
1243
1244 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1245 {
1246         enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1247         char arg[20];
1248         int ret, i;
1249
1250         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1251             cpu_mitigations_off())
1252                 return SPECTRE_V2_CMD_NONE;
1253
1254         ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1255         if (ret < 0)
1256                 return SPECTRE_V2_CMD_AUTO;
1257
1258         for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1259                 if (!match_option(arg, ret, mitigation_options[i].option))
1260                         continue;
1261                 cmd = mitigation_options[i].cmd;
1262                 break;
1263         }
1264
1265         if (i >= ARRAY_SIZE(mitigation_options)) {
1266                 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1267                 return SPECTRE_V2_CMD_AUTO;
1268         }
1269
1270         if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1271              cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1272              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1273              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1274              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1275             !IS_ENABLED(CONFIG_RETPOLINE)) {
1276                 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1277                        mitigation_options[i].option);
1278                 return SPECTRE_V2_CMD_AUTO;
1279         }
1280
1281         if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1282              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1283              cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1284             !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1285                 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1286                        mitigation_options[i].option);
1287                 return SPECTRE_V2_CMD_AUTO;
1288         }
1289
1290         if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1291              cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1292             !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1293                 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1294                        mitigation_options[i].option);
1295                 return SPECTRE_V2_CMD_AUTO;
1296         }
1297
1298         if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1299                 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1300                        mitigation_options[i].option);
1301                 return SPECTRE_V2_CMD_AUTO;
1302         }
1303
1304         if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1305                 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1306                        mitigation_options[i].option);
1307                 return SPECTRE_V2_CMD_AUTO;
1308         }
1309
1310         if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1311                 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1312                        mitigation_options[i].option);
1313                 return SPECTRE_V2_CMD_AUTO;
1314         }
1315
1316         spec_v2_print_cond(mitigation_options[i].option,
1317                            mitigation_options[i].secure);
1318         return cmd;
1319 }
1320
1321 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1322 {
1323         if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1324                 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1325                 return SPECTRE_V2_NONE;
1326         }
1327
1328         return SPECTRE_V2_RETPOLINE;
1329 }
1330
1331 static void __init spectre_v2_select_mitigation(void)
1332 {
1333         enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1334         enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1335
1336         /*
1337          * If the CPU is not affected and the command line mode is NONE or AUTO
1338          * then nothing to do.
1339          */
1340         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1341             (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1342                 return;
1343
1344         switch (cmd) {
1345         case SPECTRE_V2_CMD_NONE:
1346                 return;
1347
1348         case SPECTRE_V2_CMD_FORCE:
1349         case SPECTRE_V2_CMD_AUTO:
1350                 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1351                         mode = SPECTRE_V2_EIBRS;
1352                         break;
1353                 }
1354
1355                 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1356                     retbleed_cmd != RETBLEED_CMD_OFF &&
1357                     boot_cpu_has(X86_FEATURE_IBRS) &&
1358                     boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1359                         mode = SPECTRE_V2_IBRS;
1360                         break;
1361                 }
1362
1363                 mode = spectre_v2_select_retpoline();
1364                 break;
1365
1366         case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1367                 pr_err(SPECTRE_V2_LFENCE_MSG);
1368                 mode = SPECTRE_V2_LFENCE;
1369                 break;
1370
1371         case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1372                 mode = SPECTRE_V2_RETPOLINE;
1373                 break;
1374
1375         case SPECTRE_V2_CMD_RETPOLINE:
1376                 mode = spectre_v2_select_retpoline();
1377                 break;
1378
1379         case SPECTRE_V2_CMD_IBRS:
1380                 mode = SPECTRE_V2_IBRS;
1381                 break;
1382
1383         case SPECTRE_V2_CMD_EIBRS:
1384                 mode = SPECTRE_V2_EIBRS;
1385                 break;
1386
1387         case SPECTRE_V2_CMD_EIBRS_LFENCE:
1388                 mode = SPECTRE_V2_EIBRS_LFENCE;
1389                 break;
1390
1391         case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1392                 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1393                 break;
1394         }
1395
1396         if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1397                 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1398
1399         if (spectre_v2_in_ibrs_mode(mode)) {
1400                 /* Force it so VMEXIT will restore correctly */
1401                 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1402                 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1403         }
1404
1405         switch (mode) {
1406         case SPECTRE_V2_NONE:
1407         case SPECTRE_V2_EIBRS:
1408                 break;
1409
1410         case SPECTRE_V2_IBRS:
1411                 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1412                 break;
1413
1414         case SPECTRE_V2_LFENCE:
1415         case SPECTRE_V2_EIBRS_LFENCE:
1416                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1417                 fallthrough;
1418
1419         case SPECTRE_V2_RETPOLINE:
1420         case SPECTRE_V2_EIBRS_RETPOLINE:
1421                 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1422                 break;
1423         }
1424
1425         spectre_v2_enabled = mode;
1426         pr_info("%s\n", spectre_v2_strings[mode]);
1427
1428         /*
1429          * If spectre v2 protection has been enabled, unconditionally fill
1430          * RSB during a context switch; this protects against two independent
1431          * issues:
1432          *
1433          *      - RSB underflow (and switch to BTB) on Skylake+
1434          *      - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
1435          */
1436         setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1437         pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1438
1439         /*
1440          * Retpoline protects the kernel, but doesn't protect firmware.  IBRS
1441          * and Enhanced IBRS protect firmware too, so enable IBRS around
1442          * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1443          * enabled.
1444          *
1445          * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1446          * the user might select retpoline on the kernel command line and if
1447          * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1448          * enable IBRS around firmware calls.
1449          */
1450         if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1451                 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1452                 pr_info("Enabling Restricted Speculation for firmware calls\n");
1453         }
1454
1455         /* Set up IBPB and STIBP depending on the general spectre V2 command */
1456         spectre_v2_cmd = cmd;
1457 }
1458
1459 static void update_stibp_msr(void * __unused)
1460 {
1461         write_spec_ctrl_current(x86_spec_ctrl_base, true);
1462 }
1463
1464 /* Update x86_spec_ctrl_base in case SMT state changed. */
1465 static void update_stibp_strict(void)
1466 {
1467         u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1468
1469         if (sched_smt_active())
1470                 mask |= SPEC_CTRL_STIBP;
1471
1472         if (mask == x86_spec_ctrl_base)
1473                 return;
1474
1475         pr_info("Update user space SMT mitigation: STIBP %s\n",
1476                 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1477         x86_spec_ctrl_base = mask;
1478         on_each_cpu(update_stibp_msr, NULL, 1);
1479 }
1480
1481 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
1482 static void update_indir_branch_cond(void)
1483 {
1484         if (sched_smt_active())
1485                 static_branch_enable(&switch_to_cond_stibp);
1486         else
1487                 static_branch_disable(&switch_to_cond_stibp);
1488 }
1489
1490 #undef pr_fmt
1491 #define pr_fmt(fmt) fmt
1492
1493 /* Update the static key controlling the MDS CPU buffer clear in idle */
1494 static void update_mds_branch_idle(void)
1495 {
1496         u64 ia32_cap = x86_read_arch_cap_msr();
1497
1498         /*
1499          * Enable the idle clearing if SMT is active on CPUs which are
1500          * affected only by MSBDS and not any other MDS variant.
1501          *
1502          * The other variants cannot be mitigated when SMT is enabled, so
1503          * clearing the buffers on idle just to prevent the Store Buffer
1504          * repartitioning leak would be a window dressing exercise.
1505          */
1506         if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1507                 return;
1508
1509         if (sched_smt_active()) {
1510                 static_branch_enable(&mds_idle_clear);
1511         } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1512                    (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1513                 static_branch_disable(&mds_idle_clear);
1514         }
1515 }
1516
1517 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1518 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1519 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1520
1521 void cpu_bugs_smt_update(void)
1522 {
1523         mutex_lock(&spec_ctrl_mutex);
1524
1525         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1526             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1527                 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1528
1529         switch (spectre_v2_user_stibp) {
1530         case SPECTRE_V2_USER_NONE:
1531                 break;
1532         case SPECTRE_V2_USER_STRICT:
1533         case SPECTRE_V2_USER_STRICT_PREFERRED:
1534                 update_stibp_strict();
1535                 break;
1536         case SPECTRE_V2_USER_PRCTL:
1537         case SPECTRE_V2_USER_SECCOMP:
1538                 update_indir_branch_cond();
1539                 break;
1540         }
1541
1542         switch (mds_mitigation) {
1543         case MDS_MITIGATION_FULL:
1544         case MDS_MITIGATION_VMWERV:
1545                 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1546                         pr_warn_once(MDS_MSG_SMT);
1547                 update_mds_branch_idle();
1548                 break;
1549         case MDS_MITIGATION_OFF:
1550                 break;
1551         }
1552
1553         switch (taa_mitigation) {
1554         case TAA_MITIGATION_VERW:
1555         case TAA_MITIGATION_UCODE_NEEDED:
1556                 if (sched_smt_active())
1557                         pr_warn_once(TAA_MSG_SMT);
1558                 break;
1559         case TAA_MITIGATION_TSX_DISABLED:
1560         case TAA_MITIGATION_OFF:
1561                 break;
1562         }
1563
1564         switch (mmio_mitigation) {
1565         case MMIO_MITIGATION_VERW:
1566         case MMIO_MITIGATION_UCODE_NEEDED:
1567                 if (sched_smt_active())
1568                         pr_warn_once(MMIO_MSG_SMT);
1569                 break;
1570         case MMIO_MITIGATION_OFF:
1571                 break;
1572         }
1573
1574         mutex_unlock(&spec_ctrl_mutex);
1575 }
1576
1577 #undef pr_fmt
1578 #define pr_fmt(fmt)     "Speculative Store Bypass: " fmt
1579
1580 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1581
1582 /* The kernel command line selection */
1583 enum ssb_mitigation_cmd {
1584         SPEC_STORE_BYPASS_CMD_NONE,
1585         SPEC_STORE_BYPASS_CMD_AUTO,
1586         SPEC_STORE_BYPASS_CMD_ON,
1587         SPEC_STORE_BYPASS_CMD_PRCTL,
1588         SPEC_STORE_BYPASS_CMD_SECCOMP,
1589 };
1590
1591 static const char * const ssb_strings[] = {
1592         [SPEC_STORE_BYPASS_NONE]        = "Vulnerable",
1593         [SPEC_STORE_BYPASS_DISABLE]     = "Mitigation: Speculative Store Bypass disabled",
1594         [SPEC_STORE_BYPASS_PRCTL]       = "Mitigation: Speculative Store Bypass disabled via prctl",
1595         [SPEC_STORE_BYPASS_SECCOMP]     = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1596 };
1597
1598 static const struct {
1599         const char *option;
1600         enum ssb_mitigation_cmd cmd;
1601 } ssb_mitigation_options[]  __initconst = {
1602         { "auto",       SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
1603         { "on",         SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
1604         { "off",        SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
1605         { "prctl",      SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
1606         { "seccomp",    SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1607 };
1608
1609 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1610 {
1611         enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1612         char arg[20];
1613         int ret, i;
1614
1615         if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1616             cpu_mitigations_off()) {
1617                 return SPEC_STORE_BYPASS_CMD_NONE;
1618         } else {
1619                 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1620                                           arg, sizeof(arg));
1621                 if (ret < 0)
1622                         return SPEC_STORE_BYPASS_CMD_AUTO;
1623
1624                 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1625                         if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1626                                 continue;
1627
1628                         cmd = ssb_mitigation_options[i].cmd;
1629                         break;
1630                 }
1631
1632                 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1633                         pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1634                         return SPEC_STORE_BYPASS_CMD_AUTO;
1635                 }
1636         }
1637
1638         return cmd;
1639 }
1640
1641 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1642 {
1643         enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1644         enum ssb_mitigation_cmd cmd;
1645
1646         if (!boot_cpu_has(X86_FEATURE_SSBD))
1647                 return mode;
1648
1649         cmd = ssb_parse_cmdline();
1650         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1651             (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1652              cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1653                 return mode;
1654
1655         switch (cmd) {
1656         case SPEC_STORE_BYPASS_CMD_SECCOMP:
1657                 /*
1658                  * Choose prctl+seccomp as the default mode if seccomp is
1659                  * enabled.
1660                  */
1661                 if (IS_ENABLED(CONFIG_SECCOMP))
1662                         mode = SPEC_STORE_BYPASS_SECCOMP;
1663                 else
1664                         mode = SPEC_STORE_BYPASS_PRCTL;
1665                 break;
1666         case SPEC_STORE_BYPASS_CMD_ON:
1667                 mode = SPEC_STORE_BYPASS_DISABLE;
1668                 break;
1669         case SPEC_STORE_BYPASS_CMD_AUTO:
1670         case SPEC_STORE_BYPASS_CMD_PRCTL:
1671                 mode = SPEC_STORE_BYPASS_PRCTL;
1672                 break;
1673         case SPEC_STORE_BYPASS_CMD_NONE:
1674                 break;
1675         }
1676
1677         /*
1678          * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
1679          * bit in the mask to allow guests to use the mitigation even in the
1680          * case where the host does not enable it.
1681          */
1682         if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
1683             static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1684                 x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
1685         }
1686
1687         /*
1688          * We have three CPU feature flags that are in play here:
1689          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1690          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1691          *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1692          */
1693         if (mode == SPEC_STORE_BYPASS_DISABLE) {
1694                 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1695                 /*
1696                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1697                  * use a completely different MSR and bit dependent on family.
1698                  */
1699                 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1700                     !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1701                         x86_amd_ssb_disable();
1702                 } else {
1703                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1704                         write_spec_ctrl_current(x86_spec_ctrl_base, true);
1705                 }
1706         }
1707
1708         return mode;
1709 }
1710
1711 static void ssb_select_mitigation(void)
1712 {
1713         ssb_mode = __ssb_select_mitigation();
1714
1715         if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1716                 pr_info("%s\n", ssb_strings[ssb_mode]);
1717 }
1718
1719 #undef pr_fmt
1720 #define pr_fmt(fmt)     "Speculation prctl: " fmt
1721
1722 static void task_update_spec_tif(struct task_struct *tsk)
1723 {
1724         /* Force the update of the real TIF bits */
1725         set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1726
1727         /*
1728          * Immediately update the speculation control MSRs for the current
1729          * task, but for a non-current task delay setting the CPU
1730          * mitigation until it is scheduled next.
1731          *
1732          * This can only happen for SECCOMP mitigation. For PRCTL it's
1733          * always the current task.
1734          */
1735         if (tsk == current)
1736                 speculation_ctrl_update_current();
1737 }
1738
1739 static int l1d_flush_prctl_set(struct task_struct *task, unsigned long ctrl)
1740 {
1741
1742         if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1743                 return -EPERM;
1744
1745         switch (ctrl) {
1746         case PR_SPEC_ENABLE:
1747                 set_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1748                 return 0;
1749         case PR_SPEC_DISABLE:
1750                 clear_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH);
1751                 return 0;
1752         default:
1753                 return -ERANGE;
1754         }
1755 }
1756
1757 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1758 {
1759         if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1760             ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1761                 return -ENXIO;
1762
1763         switch (ctrl) {
1764         case PR_SPEC_ENABLE:
1765                 /* If speculation is force disabled, enable is not allowed */
1766                 if (task_spec_ssb_force_disable(task))
1767                         return -EPERM;
1768                 task_clear_spec_ssb_disable(task);
1769                 task_clear_spec_ssb_noexec(task);
1770                 task_update_spec_tif(task);
1771                 break;
1772         case PR_SPEC_DISABLE:
1773                 task_set_spec_ssb_disable(task);
1774                 task_clear_spec_ssb_noexec(task);
1775                 task_update_spec_tif(task);
1776                 break;
1777         case PR_SPEC_FORCE_DISABLE:
1778                 task_set_spec_ssb_disable(task);
1779                 task_set_spec_ssb_force_disable(task);
1780                 task_clear_spec_ssb_noexec(task);
1781                 task_update_spec_tif(task);
1782                 break;
1783         case PR_SPEC_DISABLE_NOEXEC:
1784                 if (task_spec_ssb_force_disable(task))
1785                         return -EPERM;
1786                 task_set_spec_ssb_disable(task);
1787                 task_set_spec_ssb_noexec(task);
1788                 task_update_spec_tif(task);
1789                 break;
1790         default:
1791                 return -ERANGE;
1792         }
1793         return 0;
1794 }
1795
1796 static bool is_spec_ib_user_controlled(void)
1797 {
1798         return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1799                 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1800                 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1801                 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1802 }
1803
1804 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1805 {
1806         switch (ctrl) {
1807         case PR_SPEC_ENABLE:
1808                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1809                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1810                         return 0;
1811
1812                 /*
1813                  * With strict mode for both IBPB and STIBP, the instruction
1814                  * code paths avoid checking this task flag and instead,
1815                  * unconditionally run the instruction. However, STIBP and IBPB
1816                  * are independent and either can be set to conditionally
1817                  * enabled regardless of the mode of the other.
1818                  *
1819                  * If either is set to conditional, allow the task flag to be
1820                  * updated, unless it was force-disabled by a previous prctl
1821                  * call. Currently, this is possible on an AMD CPU which has the
1822                  * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1823                  * kernel is booted with 'spectre_v2_user=seccomp', then
1824                  * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1825                  * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1826                  */
1827                 if (!is_spec_ib_user_controlled() ||
1828                     task_spec_ib_force_disable(task))
1829                         return -EPERM;
1830
1831                 task_clear_spec_ib_disable(task);
1832                 task_update_spec_tif(task);
1833                 break;
1834         case PR_SPEC_DISABLE:
1835         case PR_SPEC_FORCE_DISABLE:
1836                 /*
1837                  * Indirect branch speculation is always allowed when
1838                  * mitigation is force disabled.
1839                  */
1840                 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1841                     spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1842                         return -EPERM;
1843
1844                 if (!is_spec_ib_user_controlled())
1845                         return 0;
1846
1847                 task_set_spec_ib_disable(task);
1848                 if (ctrl == PR_SPEC_FORCE_DISABLE)
1849                         task_set_spec_ib_force_disable(task);
1850                 task_update_spec_tif(task);
1851                 break;
1852         default:
1853                 return -ERANGE;
1854         }
1855         return 0;
1856 }
1857
1858 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1859                              unsigned long ctrl)
1860 {
1861         switch (which) {
1862         case PR_SPEC_STORE_BYPASS:
1863                 return ssb_prctl_set(task, ctrl);
1864         case PR_SPEC_INDIRECT_BRANCH:
1865                 return ib_prctl_set(task, ctrl);
1866         case PR_SPEC_L1D_FLUSH:
1867                 return l1d_flush_prctl_set(task, ctrl);
1868         default:
1869                 return -ENODEV;
1870         }
1871 }
1872
1873 #ifdef CONFIG_SECCOMP
1874 void arch_seccomp_spec_mitigate(struct task_struct *task)
1875 {
1876         if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1877                 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1878         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1879             spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1880                 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1881 }
1882 #endif
1883
1884 static int l1d_flush_prctl_get(struct task_struct *task)
1885 {
1886         if (!static_branch_unlikely(&switch_mm_cond_l1d_flush))
1887                 return PR_SPEC_FORCE_DISABLE;
1888
1889         if (test_ti_thread_flag(&task->thread_info, TIF_SPEC_L1D_FLUSH))
1890                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1891         else
1892                 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1893 }
1894
1895 static int ssb_prctl_get(struct task_struct *task)
1896 {
1897         switch (ssb_mode) {
1898         case SPEC_STORE_BYPASS_DISABLE:
1899                 return PR_SPEC_DISABLE;
1900         case SPEC_STORE_BYPASS_SECCOMP:
1901         case SPEC_STORE_BYPASS_PRCTL:
1902                 if (task_spec_ssb_force_disable(task))
1903                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1904                 if (task_spec_ssb_noexec(task))
1905                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1906                 if (task_spec_ssb_disable(task))
1907                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1908                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1909         default:
1910                 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1911                         return PR_SPEC_ENABLE;
1912                 return PR_SPEC_NOT_AFFECTED;
1913         }
1914 }
1915
1916 static int ib_prctl_get(struct task_struct *task)
1917 {
1918         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1919                 return PR_SPEC_NOT_AFFECTED;
1920
1921         if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1922             spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1923                 return PR_SPEC_ENABLE;
1924         else if (is_spec_ib_user_controlled()) {
1925                 if (task_spec_ib_force_disable(task))
1926                         return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1927                 if (task_spec_ib_disable(task))
1928                         return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1929                 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1930         } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1931             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1932             spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1933                 return PR_SPEC_DISABLE;
1934         else
1935                 return PR_SPEC_NOT_AFFECTED;
1936 }
1937
1938 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1939 {
1940         switch (which) {
1941         case PR_SPEC_STORE_BYPASS:
1942                 return ssb_prctl_get(task);
1943         case PR_SPEC_INDIRECT_BRANCH:
1944                 return ib_prctl_get(task);
1945         case PR_SPEC_L1D_FLUSH:
1946                 return l1d_flush_prctl_get(task);
1947         default:
1948                 return -ENODEV;
1949         }
1950 }
1951
1952 void x86_spec_ctrl_setup_ap(void)
1953 {
1954         if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
1955                 write_spec_ctrl_current(x86_spec_ctrl_base, true);
1956
1957         if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
1958                 x86_amd_ssb_disable();
1959 }
1960
1961 bool itlb_multihit_kvm_mitigation;
1962 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
1963
1964 #undef pr_fmt
1965 #define pr_fmt(fmt)     "L1TF: " fmt
1966
1967 /* Default mitigation for L1TF-affected CPUs */
1968 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
1969 #if IS_ENABLED(CONFIG_KVM_INTEL)
1970 EXPORT_SYMBOL_GPL(l1tf_mitigation);
1971 #endif
1972 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
1973 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
1974
1975 /*
1976  * These CPUs all support 44bits physical address space internally in the
1977  * cache but CPUID can report a smaller number of physical address bits.
1978  *
1979  * The L1TF mitigation uses the top most address bit for the inversion of
1980  * non present PTEs. When the installed memory reaches into the top most
1981  * address bit due to memory holes, which has been observed on machines
1982  * which report 36bits physical address bits and have 32G RAM installed,
1983  * then the mitigation range check in l1tf_select_mitigation() triggers.
1984  * This is a false positive because the mitigation is still possible due to
1985  * the fact that the cache uses 44bit internally. Use the cache bits
1986  * instead of the reported physical bits and adjust them on the affected
1987  * machines to 44bit if the reported bits are less than 44.
1988  */
1989 static void override_cache_bits(struct cpuinfo_x86 *c)
1990 {
1991         if (c->x86 != 6)
1992                 return;
1993
1994         switch (c->x86_model) {
1995         case INTEL_FAM6_NEHALEM:
1996         case INTEL_FAM6_WESTMERE:
1997         case INTEL_FAM6_SANDYBRIDGE:
1998         case INTEL_FAM6_IVYBRIDGE:
1999         case INTEL_FAM6_HASWELL:
2000         case INTEL_FAM6_HASWELL_L:
2001         case INTEL_FAM6_HASWELL_G:
2002         case INTEL_FAM6_BROADWELL:
2003         case INTEL_FAM6_BROADWELL_G:
2004         case INTEL_FAM6_SKYLAKE_L:
2005         case INTEL_FAM6_SKYLAKE:
2006         case INTEL_FAM6_KABYLAKE_L:
2007         case INTEL_FAM6_KABYLAKE:
2008                 if (c->x86_cache_bits < 44)
2009                         c->x86_cache_bits = 44;
2010                 break;
2011         }
2012 }
2013
2014 static void __init l1tf_select_mitigation(void)
2015 {
2016         u64 half_pa;
2017
2018         if (!boot_cpu_has_bug(X86_BUG_L1TF))
2019                 return;
2020
2021         if (cpu_mitigations_off())
2022                 l1tf_mitigation = L1TF_MITIGATION_OFF;
2023         else if (cpu_mitigations_auto_nosmt())
2024                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2025
2026         override_cache_bits(&boot_cpu_data);
2027
2028         switch (l1tf_mitigation) {
2029         case L1TF_MITIGATION_OFF:
2030         case L1TF_MITIGATION_FLUSH_NOWARN:
2031         case L1TF_MITIGATION_FLUSH:
2032                 break;
2033         case L1TF_MITIGATION_FLUSH_NOSMT:
2034         case L1TF_MITIGATION_FULL:
2035                 cpu_smt_disable(false);
2036                 break;
2037         case L1TF_MITIGATION_FULL_FORCE:
2038                 cpu_smt_disable(true);
2039                 break;
2040         }
2041
2042 #if CONFIG_PGTABLE_LEVELS == 2
2043         pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2044         return;
2045 #endif
2046
2047         half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2048         if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2049                         e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2050                 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2051                 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2052                                 half_pa);
2053                 pr_info("However, doing so will make a part of your RAM unusable.\n");
2054                 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2055                 return;
2056         }
2057
2058         setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2059 }
2060
2061 static int __init l1tf_cmdline(char *str)
2062 {
2063         if (!boot_cpu_has_bug(X86_BUG_L1TF))
2064                 return 0;
2065
2066         if (!str)
2067                 return -EINVAL;
2068
2069         if (!strcmp(str, "off"))
2070                 l1tf_mitigation = L1TF_MITIGATION_OFF;
2071         else if (!strcmp(str, "flush,nowarn"))
2072                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2073         else if (!strcmp(str, "flush"))
2074                 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2075         else if (!strcmp(str, "flush,nosmt"))
2076                 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2077         else if (!strcmp(str, "full"))
2078                 l1tf_mitigation = L1TF_MITIGATION_FULL;
2079         else if (!strcmp(str, "full,force"))
2080                 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2081
2082         return 0;
2083 }
2084 early_param("l1tf", l1tf_cmdline);
2085
2086 #undef pr_fmt
2087 #define pr_fmt(fmt) fmt
2088
2089 #ifdef CONFIG_SYSFS
2090
2091 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2092
2093 #if IS_ENABLED(CONFIG_KVM_INTEL)
2094 static const char * const l1tf_vmx_states[] = {
2095         [VMENTER_L1D_FLUSH_AUTO]                = "auto",
2096         [VMENTER_L1D_FLUSH_NEVER]               = "vulnerable",
2097         [VMENTER_L1D_FLUSH_COND]                = "conditional cache flushes",
2098         [VMENTER_L1D_FLUSH_ALWAYS]              = "cache flushes",
2099         [VMENTER_L1D_FLUSH_EPT_DISABLED]        = "EPT disabled",
2100         [VMENTER_L1D_FLUSH_NOT_REQUIRED]        = "flush not necessary"
2101 };
2102
2103 static ssize_t l1tf_show_state(char *buf)
2104 {
2105         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2106                 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2107
2108         if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2109             (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2110              sched_smt_active())) {
2111                 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2112                                l1tf_vmx_states[l1tf_vmx_mitigation]);
2113         }
2114
2115         return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2116                        l1tf_vmx_states[l1tf_vmx_mitigation],
2117                        sched_smt_active() ? "vulnerable" : "disabled");
2118 }
2119
2120 static ssize_t itlb_multihit_show_state(char *buf)
2121 {
2122         if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2123             !boot_cpu_has(X86_FEATURE_VMX))
2124                 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2125         else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2126                 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2127         else if (itlb_multihit_kvm_mitigation)
2128                 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2129         else
2130                 return sprintf(buf, "KVM: Vulnerable\n");
2131 }
2132 #else
2133 static ssize_t l1tf_show_state(char *buf)
2134 {
2135         return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2136 }
2137
2138 static ssize_t itlb_multihit_show_state(char *buf)
2139 {
2140         return sprintf(buf, "Processor vulnerable\n");
2141 }
2142 #endif
2143
2144 static ssize_t mds_show_state(char *buf)
2145 {
2146         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2147                 return sprintf(buf, "%s; SMT Host state unknown\n",
2148                                mds_strings[mds_mitigation]);
2149         }
2150
2151         if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2152                 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2153                                (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2154                                 sched_smt_active() ? "mitigated" : "disabled"));
2155         }
2156
2157         return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2158                        sched_smt_active() ? "vulnerable" : "disabled");
2159 }
2160
2161 static ssize_t tsx_async_abort_show_state(char *buf)
2162 {
2163         if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2164             (taa_mitigation == TAA_MITIGATION_OFF))
2165                 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2166
2167         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2168                 return sprintf(buf, "%s; SMT Host state unknown\n",
2169                                taa_strings[taa_mitigation]);
2170         }
2171
2172         return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2173                        sched_smt_active() ? "vulnerable" : "disabled");
2174 }
2175
2176 static ssize_t mmio_stale_data_show_state(char *buf)
2177 {
2178         if (mmio_mitigation == MMIO_MITIGATION_OFF)
2179                 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2180
2181         if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2182                 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2183                                   mmio_strings[mmio_mitigation]);
2184         }
2185
2186         return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2187                           sched_smt_active() ? "vulnerable" : "disabled");
2188 }
2189
2190 static char *stibp_state(void)
2191 {
2192         if (spectre_v2_in_ibrs_mode(spectre_v2_enabled))
2193                 return "";
2194
2195         switch (spectre_v2_user_stibp) {
2196         case SPECTRE_V2_USER_NONE:
2197                 return ", STIBP: disabled";
2198         case SPECTRE_V2_USER_STRICT:
2199                 return ", STIBP: forced";
2200         case SPECTRE_V2_USER_STRICT_PREFERRED:
2201                 return ", STIBP: always-on";
2202         case SPECTRE_V2_USER_PRCTL:
2203         case SPECTRE_V2_USER_SECCOMP:
2204                 if (static_key_enabled(&switch_to_cond_stibp))
2205                         return ", STIBP: conditional";
2206         }
2207         return "";
2208 }
2209
2210 static char *ibpb_state(void)
2211 {
2212         if (boot_cpu_has(X86_FEATURE_IBPB)) {
2213                 if (static_key_enabled(&switch_mm_always_ibpb))
2214                         return ", IBPB: always-on";
2215                 if (static_key_enabled(&switch_mm_cond_ibpb))
2216                         return ", IBPB: conditional";
2217                 return ", IBPB: disabled";
2218         }
2219         return "";
2220 }
2221
2222 static ssize_t spectre_v2_show_state(char *buf)
2223 {
2224         if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2225                 return sprintf(buf, "Vulnerable: LFENCE\n");
2226
2227         if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2228                 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2229
2230         if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2231             spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2232                 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2233
2234         return sprintf(buf, "%s%s%s%s%s%s\n",
2235                        spectre_v2_strings[spectre_v2_enabled],
2236                        ibpb_state(),
2237                        boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2238                        stibp_state(),
2239                        boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2240                        spectre_v2_module_string());
2241 }
2242
2243 static ssize_t srbds_show_state(char *buf)
2244 {
2245         return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2246 }
2247
2248 static ssize_t retbleed_show_state(char *buf)
2249 {
2250         if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET) {
2251             if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2252                 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2253                     return sprintf(buf, "Vulnerable: untrained return thunk on non-Zen uarch\n");
2254
2255             return sprintf(buf, "%s; SMT %s\n",
2256                            retbleed_strings[retbleed_mitigation],
2257                            !sched_smt_active() ? "disabled" :
2258                            spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2259                            spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2260                            "enabled with STIBP protection" : "vulnerable");
2261         }
2262
2263         return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2264 }
2265
2266 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2267                                char *buf, unsigned int bug)
2268 {
2269         if (!boot_cpu_has_bug(bug))
2270                 return sprintf(buf, "Not affected\n");
2271
2272         switch (bug) {
2273         case X86_BUG_CPU_MELTDOWN:
2274                 if (boot_cpu_has(X86_FEATURE_PTI))
2275                         return sprintf(buf, "Mitigation: PTI\n");
2276
2277                 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2278                         return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2279
2280                 break;
2281
2282         case X86_BUG_SPECTRE_V1:
2283                 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2284
2285         case X86_BUG_SPECTRE_V2:
2286                 return spectre_v2_show_state(buf);
2287
2288         case X86_BUG_SPEC_STORE_BYPASS:
2289                 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2290
2291         case X86_BUG_L1TF:
2292                 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2293                         return l1tf_show_state(buf);
2294                 break;
2295
2296         case X86_BUG_MDS:
2297                 return mds_show_state(buf);
2298
2299         case X86_BUG_TAA:
2300                 return tsx_async_abort_show_state(buf);
2301
2302         case X86_BUG_ITLB_MULTIHIT:
2303                 return itlb_multihit_show_state(buf);
2304
2305         case X86_BUG_SRBDS:
2306                 return srbds_show_state(buf);
2307
2308         case X86_BUG_MMIO_STALE_DATA:
2309                 return mmio_stale_data_show_state(buf);
2310
2311         case X86_BUG_RETBLEED:
2312                 return retbleed_show_state(buf);
2313
2314         default:
2315                 break;
2316         }
2317
2318         return sprintf(buf, "Vulnerable\n");
2319 }
2320
2321 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2322 {
2323         return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2324 }
2325
2326 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2327 {
2328         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2329 }
2330
2331 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2332 {
2333         return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2334 }
2335
2336 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2337 {
2338         return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2339 }
2340
2341 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2342 {
2343         return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2344 }
2345
2346 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2347 {
2348         return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2349 }
2350
2351 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2352 {
2353         return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2354 }
2355
2356 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2357 {
2358         return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2359 }
2360
2361 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2362 {
2363         return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2364 }
2365
2366 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2367 {
2368         return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2369 }
2370
2371 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2372 {
2373         return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2374 }
2375 #endif