arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/crash_dump.h>
  11 #include <linux/cpuhotplug.h>
  12 #include <linux/cpumask.h>
  13 #include <linux/proc_fs.h>
  14 #include <linux/memory.h>
  15 #include <linux/export.h>
  16 #include <linux/pci.h>
  17 #include <linux/acpi.h>
  18 #include <linux/efi.h>
  19
  20 #include <asm/e820/api.h>
  21 #include <asm/uv/uv_mmrs.h>
  22 #include <asm/uv/uv_hub.h>
  23 #include <asm/uv/bios.h>
  24 #include <asm/uv/uv.h>
  25 #include <asm/apic.h>
  26
  27 static enum uv_system_type      uv_system_type;
  28 static int                      uv_hubbed_system;
  29 static int                      uv_hubless_system;
  30 static u64                      gru_start_paddr, gru_end_paddr;
  31 static union uvh_apicid         uvh_apicid;
  32
  33 /* Unpack OEM/TABLE ID's to be NULL terminated strings */
  34 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
  35 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  36
  37 /* Information derived from CPUID: */
  38 static struct {
  39         unsigned int apicid_shift;
  40         unsigned int apicid_mask;
  41         unsigned int socketid_shift;    /* aka pnode_shift for UV2/3 */
  42         unsigned int pnode_mask;
  43         unsigned int gpa_shift;
  44         unsigned int gnode_shift;
  45 } uv_cpuid;
  46
  47 static int uv_min_hub_revision_id;
  48
  49 static struct apic apic_x2apic_uv_x;
  50 static struct uv_hub_info_s uv_hub_info_node0;
  51
  52 /* Set this to use hardware error handler instead of kernel panic: */
  53 static int disable_uv_undefined_panic = 1;
  54
  55 unsigned long uv_undefined(char *str)
  56 {
  57         if (likely(!disable_uv_undefined_panic))
  58                 panic("UV: error: undefined MMR: %s\n", str);
  59         else
  60                 pr_crit("UV: error: undefined MMR: %s\n", str);
  61
  62         /* Cause a machine fault: */
  63         return ~0ul;
  64 }
  65 EXPORT_SYMBOL(uv_undefined);
  66
  67 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  68 {
  69         unsigned long val, *mmr;
  70
  71         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  72         val = *mmr;
  73         early_iounmap(mmr, sizeof(*mmr));
  74
  75         return val;
  76 }
  77
  78 static inline bool is_GRU_range(u64 start, u64 end)
  79 {
  80         return start >= gru_start_paddr && end <= gru_end_paddr;
  81 }
  82
  83 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  84 {
  85         return is_ISA_range(start, end) || is_GRU_range(start, end);
  86 }
  87
  88 static int __init early_get_pnodeid(void)
  89 {
  90         union uvh_node_id_u node_id;
  91         union uvh_rh_gam_config_mmr_u  m_n_config;
  92         int pnode;
  93
  94         /* Currently, all blades have same revision number */
  95         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
  96         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
  97         uv_min_hub_revision_id = node_id.s.revision;
  98
  99         switch (node_id.s.part_number) {
 100         case UV2_HUB_PART_NUMBER:
 101         case UV2_HUB_PART_NUMBER_X:
 102                 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
 103                 break;
 104         case UV3_HUB_PART_NUMBER:
 105         case UV3_HUB_PART_NUMBER_X:
 106                 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
 107                 break;
 108
 109         /* Update: UV4A has only a modified revision to indicate HUB fixes */
 110         case UV4_HUB_PART_NUMBER:
 111                 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
 112                 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
 113                 break;
 114         }
 115
 116         uv_hub_info->hub_revision = uv_min_hub_revision_id;
 117         uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
 118         pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
 119         uv_cpuid.gpa_shift = 46;        /* Default unless changed */
 120
 121         pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
 122                 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
 123                 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
 124         return pnode;
 125 }
 126
 127 static void __init uv_tsc_check_sync(void)
 128 {
 129         u64 mmr;
 130         int sync_state;
 131         int mmr_shift;
 132         char *state;
 133         bool valid;
 134
 135         /* Accommodate different UV arch BIOSes */
 136         mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
 137         mmr_shift =
 138                 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
 139         sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
 140
 141         switch (sync_state) {
 142         case UVH_TSC_SYNC_VALID:
 143                 state = "in sync";
 144                 valid = true;
 145                 break;
 146
 147         case UVH_TSC_SYNC_INVALID:
 148                 state = "unstable";
 149                 valid = false;
 150                 break;
 151         default:
 152                 state = "unknown: assuming valid";
 153                 valid = true;
 154                 break;
 155         }
 156         pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
 157
 158         /* Mark flag that says TSC != 0 is valid for socket 0 */
 159         if (valid)
 160                 mark_tsc_async_resets("UV BIOS");
 161         else
 162                 mark_tsc_unstable("UV BIOS");
 163 }
 164
 165 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 166
 167 #define SMT_LEVEL                       0       /* Leaf 0xb SMT level */
 168 #define INVALID_TYPE                    0       /* Leaf 0xb sub-leaf types */
 169 #define SMT_TYPE                        1
 170 #define CORE_TYPE                       2
 171 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 172 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 173
 174 static void set_x2apic_bits(void)
 175 {
 176         unsigned int eax, ebx, ecx, edx, sub_index;
 177         unsigned int sid_shift;
 178
 179         cpuid(0, &eax, &ebx, &ecx, &edx);
 180         if (eax < 0xb) {
 181                 pr_info("UV: CPU does not have CPUID.11\n");
 182                 return;
 183         }
 184
 185         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 186         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 187                 pr_info("UV: CPUID.11 not implemented\n");
 188                 return;
 189         }
 190
 191         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 192         sub_index = 1;
 193         do {
 194                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 195                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 196                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 197                         break;
 198                 }
 199                 sub_index++;
 200         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 201
 202         uv_cpuid.apicid_shift   = 0;
 203         uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
 204         uv_cpuid.socketid_shift = sid_shift;
 205 }
 206
 207 static void __init early_get_apic_socketid_shift(void)
 208 {
 209         if (is_uv2_hub() || is_uv3_hub())
 210                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 211
 212         set_x2apic_bits();
 213
 214         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 215         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 216 }
 217
 218 static void __init uv_stringify(int len, char *to, char *from)
 219 {
 220         /* Relies on 'to' being NULL chars so result will be NULL terminated */
 221         strncpy(to, from, len-1);
 222 }
 223
 224 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
 225 {
 226         int pnodeid;
 227         int uv_apic;
 228
 229         uv_stringify(sizeof(oem_id), oem_id, _oem_id);
 230         uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
 231
 232         if (strncmp(oem_id, "SGI", 3) != 0) {
 233                 if (strncmp(oem_id, "NSGI", 4) != 0)
 234                         return 0;
 235
 236                 /* UV4 Hubless, CH, (0x11:UV4+Any) */
 237                 if (strncmp(oem_id, "NSGI4", 5) == 0)
 238                         uv_hubless_system = 0x11;
 239
 240                 /* UV3 Hubless, UV300/MC990X w/o hub (0x9:UV3+Any) */
 241                 else
 242                         uv_hubless_system = 0x9;
 243
 244                 pr_info("UV: OEM IDs %s/%s, HUBLESS(0x%x)\n",
 245                         oem_id, oem_table_id, uv_hubless_system);
 246
 247                 return 0;
 248         }
 249
 250         if (numa_off) {
 251                 pr_err("UV: NUMA is off, disabling UV support\n");
 252                 return 0;
 253         }
 254
 255         /* Set up early hub type field in uv_hub_info for Node 0 */
 256         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 257
 258         /*
 259          * Determine UV arch type.
 260          *   SGI2: UV2000/3000
 261          *   SGI3: UV300 (truncated to 4 chars because of different varieties)
 262          *   SGI4: UV400 (truncated to 4 chars because of different varieties)
 263          */
 264         if (!strncmp(oem_id, "SGI4", 4)) {
 265                 uv_hub_info->hub_revision = UV4_HUB_REVISION_BASE;
 266                 uv_hubbed_system = 0x11;
 267
 268         } else if (!strncmp(oem_id, "SGI3", 4)) {
 269                 uv_hub_info->hub_revision = UV3_HUB_REVISION_BASE;
 270                 uv_hubbed_system = 0x9;
 271
 272         } else if (!strcmp(oem_id, "SGI2")) {
 273                 uv_hub_info->hub_revision = UV2_HUB_REVISION_BASE;
 274                 uv_hubbed_system = 0x5;
 275
 276         } else {
 277                 uv_hub_info->hub_revision = 0;
 278                 goto badbios;
 279         }
 280
 281         pnodeid = early_get_pnodeid();
 282         early_get_apic_socketid_shift();
 283
 284         x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
 285         x86_platform.nmi_init = uv_nmi_init;
 286
 287         if (!strcmp(oem_table_id, "UVX")) {
 288                 /* This is the most common hardware variant: */
 289                 uv_system_type = UV_X2APIC;
 290                 uv_apic = 0;
 291
 292         } else if (!strcmp(oem_table_id, "UVL")) {
 293                 /* Only used for very small systems:  */
 294                 uv_system_type = UV_LEGACY_APIC;
 295                 uv_apic = 0;
 296
 297         } else {
 298                 goto badbios;
 299         }
 300
 301         pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
 302         uv_tsc_check_sync();
 303
 304         return uv_apic;
 305
 306 badbios:
 307         pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
 308         pr_err("Current UV Type or BIOS not supported\n");
 309         BUG();
 310 }
 311
 312 enum uv_system_type get_uv_system_type(void)
 313 {
 314         return uv_system_type;
 315 }
 316
 317 int is_uv_system(void)
 318 {
 319         return uv_system_type != UV_NONE;
 320 }
 321 EXPORT_SYMBOL_GPL(is_uv_system);
 322
 323 int is_uv_hubbed(int uvtype)
 324 {
 325         return (uv_hubbed_system & uvtype);
 326 }
 327 EXPORT_SYMBOL_GPL(is_uv_hubbed);
 328
 329 static int is_uv_hubless(int uvtype)
 330 {
 331         return (uv_hubless_system & uvtype);
 332 }
 333
 334 void **__uv_hub_info_list;
 335 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 336
 337 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 338 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 339
 340 short uv_possible_blades;
 341 EXPORT_SYMBOL_GPL(uv_possible_blades);
 342
 343 unsigned long sn_rtc_cycles_per_second;
 344 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 345
 346 /* The following values are used for the per node hub info struct */
 347 static __initdata unsigned short                *_node_to_pnode;
 348 static __initdata unsigned short                _min_socket, _max_socket;
 349 static __initdata unsigned short                _min_pnode, _max_pnode, _gr_table_len;
 350 static __initdata struct uv_gam_range_entry     *uv_gre_table;
 351 static __initdata struct uv_gam_parameters      *uv_gp_table;
 352 static __initdata unsigned short                *_socket_to_node;
 353 static __initdata unsigned short                *_socket_to_pnode;
 354 static __initdata unsigned short                *_pnode_to_socket;
 355
 356 static __initdata struct uv_gam_range_s         *_gr_table;
 357
 358 #define SOCK_EMPTY      ((unsigned short)~0)
 359
 360 /* Default UV memory block size is 2GB */
 361 static unsigned long mem_block_size __initdata = (2UL << 30);
 362
 363 /* Kernel parameter to specify UV mem block size */
 364 static int __init parse_mem_block_size(char *ptr)
 365 {
 366         unsigned long size = memparse(ptr, NULL);
 367
 368         /* Size will be rounded down by set_block_size() below */
 369         mem_block_size = size;
 370         return 0;
 371 }
 372 early_param("uv_memblksize", parse_mem_block_size);
 373
 374 static __init int adj_blksize(u32 lgre)
 375 {
 376         unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
 377         unsigned long size;
 378
 379         for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
 380                 if (IS_ALIGNED(base, size))
 381                         break;
 382
 383         if (size >= mem_block_size)
 384                 return 0;
 385
 386         mem_block_size = size;
 387         return 1;
 388 }
 389
 390 static __init void set_block_size(void)
 391 {
 392         unsigned int order = ffs(mem_block_size);
 393
 394         if (order) {
 395                 /* adjust for ffs return of 1..64 */
 396                 set_memory_block_size_order(order - 1);
 397                 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
 398         } else {
 399                 /* bad or zero value, default to 1UL << 31 (2GB) */
 400                 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
 401                 set_memory_block_size_order(31);
 402         }
 403 }
 404
 405 /* Build GAM range lookup table: */
 406 static __init void build_uv_gr_table(void)
 407 {
 408         struct uv_gam_range_entry *gre = uv_gre_table;
 409         struct uv_gam_range_s *grt;
 410         unsigned long last_limit = 0, ram_limit = 0;
 411         int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
 412
 413         if (!gre)
 414                 return;
 415
 416         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
 417         grt = kzalloc(bytes, GFP_KERNEL);
 418         BUG_ON(!grt);
 419         _gr_table = grt;
 420
 421         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
 422                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
 423                         if (!ram_limit) {
 424                                 /* Mark hole between RAM/non-RAM: */
 425                                 ram_limit = last_limit;
 426                                 last_limit = gre->limit;
 427                                 lsid++;
 428                                 continue;
 429                         }
 430                         last_limit = gre->limit;
 431                         pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
 432                         continue;
 433                 }
 434                 if (_max_socket < gre->sockid) {
 435                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
 436                         continue;
 437                 }
 438                 sid = gre->sockid - _min_socket;
 439                 if (lsid < sid) {
 440                         /* New range: */
 441                         grt = &_gr_table[indx];
 442                         grt->base = lindx;
 443                         grt->nasid = gre->nasid;
 444                         grt->limit = last_limit = gre->limit;
 445                         lsid = sid;
 446                         lindx = indx++;
 447                         continue;
 448                 }
 449                 /* Update range: */
 450                 if (lsid == sid && !ram_limit) {
 451                         /* .. if contiguous: */
 452                         if (grt->limit == last_limit) {
 453                                 grt->limit = last_limit = gre->limit;
 454                                 continue;
 455                         }
 456                 }
 457                 /* Non-contiguous RAM range: */
 458                 if (!ram_limit) {
 459                         grt++;
 460                         grt->base = lindx;
 461                         grt->nasid = gre->nasid;
 462                         grt->limit = last_limit = gre->limit;
 463                         continue;
 464                 }
 465                 /* Non-contiguous/non-RAM: */
 466                 grt++;
 467                 /* base is this entry */
 468                 grt->base = grt - _gr_table;
 469                 grt->nasid = gre->nasid;
 470                 grt->limit = last_limit = gre->limit;
 471                 lsid++;
 472         }
 473
 474         /* Shorten table if possible */
 475         grt++;
 476         i = grt - _gr_table;
 477         if (i < _gr_table_len) {
 478                 void *ret;
 479
 480                 bytes = i * sizeof(struct uv_gam_range_s);
 481                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
 482                 if (ret) {
 483                         _gr_table = ret;
 484                         _gr_table_len = i;
 485                 }
 486         }
 487
 488         /* Display resultant GAM range table: */
 489         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
 490                 unsigned long start, end;
 491                 int gb = grt->base;
 492
 493                 start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
 494                 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
 495
 496                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
 497         }
 498 }
 499
 500 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 501 {
 502         unsigned long val;
 503         int pnode;
 504
 505         pnode = uv_apicid_to_pnode(phys_apicid);
 506
 507         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 508             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 509             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 510             APIC_DM_INIT;
 511
 512         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 513
 514         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 515             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 516             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 517             APIC_DM_STARTUP;
 518
 519         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 520
 521         return 0;
 522 }
 523
 524 static void uv_send_IPI_one(int cpu, int vector)
 525 {
 526         unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
 527         int pnode = uv_apicid_to_pnode(apicid);
 528         unsigned long dmode, val;
 529
 530         if (vector == NMI_VECTOR)
 531                 dmode = dest_NMI;
 532         else
 533                 dmode = dest_Fixed;
 534
 535         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 536                 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 537                 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
 538                 (vector << UVH_IPI_INT_VECTOR_SHFT);
 539
 540         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 541 }
 542
 543 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 544 {
 545         unsigned int cpu;
 546
 547         for_each_cpu(cpu, mask)
 548                 uv_send_IPI_one(cpu, vector);
 549 }
 550
 551 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 552 {
 553         unsigned int this_cpu = smp_processor_id();
 554         unsigned int cpu;
 555
 556         for_each_cpu(cpu, mask) {
 557                 if (cpu != this_cpu)
 558                         uv_send_IPI_one(cpu, vector);
 559         }
 560 }
 561
 562 static void uv_send_IPI_allbutself(int vector)
 563 {
 564         unsigned int this_cpu = smp_processor_id();
 565         unsigned int cpu;
 566
 567         for_each_online_cpu(cpu) {
 568                 if (cpu != this_cpu)
 569                         uv_send_IPI_one(cpu, vector);
 570         }
 571 }
 572
 573 static void uv_send_IPI_all(int vector)
 574 {
 575         uv_send_IPI_mask(cpu_online_mask, vector);
 576 }
 577
 578 static int uv_apic_id_valid(u32 apicid)
 579 {
 580         return 1;
 581 }
 582
 583 static int uv_apic_id_registered(void)
 584 {
 585         return 1;
 586 }
 587
 588 static void uv_init_apic_ldr(void)
 589 {
 590 }
 591
 592 static u32 apic_uv_calc_apicid(unsigned int cpu)
 593 {
 594         return apic_default_calc_apicid(cpu);
 595 }
 596
 597 static unsigned int x2apic_get_apic_id(unsigned long id)
 598 {
 599         return id;
 600 }
 601
 602 static u32 set_apic_id(unsigned int id)
 603 {
 604         return id;
 605 }
 606
 607 static unsigned int uv_read_apic_id(void)
 608 {
 609         return x2apic_get_apic_id(apic_read(APIC_ID));
 610 }
 611
 612 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 613 {
 614         return uv_read_apic_id() >> index_msb;
 615 }
 616
 617 static void uv_send_IPI_self(int vector)
 618 {
 619         apic_write(APIC_SELF_IPI, vector);
 620 }
 621
 622 static int uv_probe(void)
 623 {
 624         return apic == &apic_x2apic_uv_x;
 625 }
 626
 627 static struct apic apic_x2apic_uv_x __ro_after_init = {
 628
 629         .name                           = "UV large system",
 630         .probe                          = uv_probe,
 631         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 632         .apic_id_valid                  = uv_apic_id_valid,
 633         .apic_id_registered             = uv_apic_id_registered,
 634
 635         .irq_delivery_mode              = dest_Fixed,
 636         .irq_dest_mode                  = 0, /* Physical */
 637
 638         .disable_esr                    = 0,
 639         .dest_logical                   = APIC_DEST_LOGICAL,
 640         .check_apicid_used              = NULL,
 641
 642         .init_apic_ldr                  = uv_init_apic_ldr,
 643
 644         .ioapic_phys_id_map             = NULL,
 645         .setup_apic_routing             = NULL,
 646         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 647         .apicid_to_cpu_present          = NULL,
 648         .check_phys_apicid_present      = default_check_phys_apicid_present,
 649         .phys_pkg_id                    = uv_phys_pkg_id,
 650
 651         .get_apic_id                    = x2apic_get_apic_id,
 652         .set_apic_id                    = set_apic_id,
 653
 654         .calc_dest_apicid               = apic_uv_calc_apicid,
 655
 656         .send_IPI                       = uv_send_IPI_one,
 657         .send_IPI_mask                  = uv_send_IPI_mask,
 658         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 659         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 660         .send_IPI_all                   = uv_send_IPI_all,
 661         .send_IPI_self                  = uv_send_IPI_self,
 662
 663         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 664         .inquire_remote_apic            = NULL,
 665
 666         .read                           = native_apic_msr_read,
 667         .write                          = native_apic_msr_write,
 668         .eoi_write                      = native_apic_msr_eoi_write,
 669         .icr_read                       = native_x2apic_icr_read,
 670         .icr_write                      = native_x2apic_icr_write,
 671         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 672         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 673 };
 674
 675 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 676 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 677
 678 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 679 {
 680         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 681         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 682         unsigned long m_redirect;
 683         unsigned long m_overlay;
 684         int i;
 685
 686         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 687                 switch (i) {
 688                 case 0:
 689                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
 690                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
 691                         break;
 692                 case 1:
 693                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
 694                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
 695                         break;
 696                 case 2:
 697                         m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
 698                         m_overlay  = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
 699                         break;
 700                 }
 701                 alias.v = uv_read_local_mmr(m_overlay);
 702                 if (alias.s.enable && alias.s.base == 0) {
 703                         *size = (1UL << alias.s.m_alias);
 704                         redirect.v = uv_read_local_mmr(m_redirect);
 705                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 706                         return;
 707                 }
 708         }
 709         *base = *size = 0;
 710 }
 711
 712 enum map_type {map_wb, map_uc};
 713
 714 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
 715 {
 716         unsigned long bytes, paddr;
 717
 718         paddr = base << pshift;
 719         bytes = (1UL << bshift) * (max_pnode + 1);
 720         if (!paddr) {
 721                 pr_info("UV: Map %s_HI base address NULL\n", id);
 722                 return;
 723         }
 724         pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
 725         if (map_type == map_uc)
 726                 init_extra_mapping_uc(paddr, bytes);
 727         else
 728                 init_extra_mapping_wb(paddr, bytes);
 729 }
 730
 731 static __init void map_gru_high(int max_pnode)
 732 {
 733         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 734         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 735         unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
 736         unsigned long base;
 737
 738         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 739         if (!gru.s.enable) {
 740                 pr_info("UV: GRU disabled\n");
 741                 return;
 742         }
 743
 744         base = (gru.v & mask) >> shift;
 745         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 746         gru_start_paddr = ((u64)base << shift);
 747         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 748 }
 749
 750 static __init void map_mmr_high(int max_pnode)
 751 {
 752         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 753         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 754
 755         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 756         if (mmr.s.enable)
 757                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 758         else
 759                 pr_info("UV: MMR disabled\n");
 760 }
 761
 762 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
 763 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
 764 {
 765         unsigned long overlay;
 766         unsigned long mmr;
 767         unsigned long base;
 768         unsigned long nasid_mask;
 769         unsigned long m_overlay;
 770         int i, n, shift, m_io, max_io;
 771         int nasid, lnasid, fi, li;
 772         char *id;
 773
 774         if (index == 0) {
 775                 id = "MMIOH0";
 776                 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
 777                 overlay = uv_read_local_mmr(m_overlay);
 778                 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
 779                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
 780                 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
 781                         >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
 782                 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
 783                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
 784                 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
 785         } else {
 786                 id = "MMIOH1";
 787                 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
 788                 overlay = uv_read_local_mmr(m_overlay);
 789                 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
 790                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
 791                 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
 792                         >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
 793                 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
 794                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
 795                 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
 796         }
 797         pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
 798         if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
 799                 pr_info("UV: %s disabled\n", id);
 800                 return;
 801         }
 802
 803         /* Convert to NASID: */
 804         min_pnode *= 2;
 805         max_pnode *= 2;
 806         max_io = lnasid = fi = li = -1;
 807
 808         for (i = 0; i < n; i++) {
 809                 unsigned long m_redirect = mmr + i * 8;
 810                 unsigned long redirect = uv_read_local_mmr(m_redirect);
 811
 812                 nasid = redirect & nasid_mask;
 813                 if (i == 0)
 814                         pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
 815                                 id, redirect, m_redirect, nasid);
 816
 817                 /* Invalid NASID: */
 818                 if (nasid < min_pnode || max_pnode < nasid)
 819                         nasid = -1;
 820
 821                 if (nasid == lnasid) {
 822                         li = i;
 823                         /* Last entry check: */
 824                         if (i != n-1)
 825                                 continue;
 826                 }
 827
 828                 /* Check if we have a cached (or last) redirect to print: */
 829                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
 830                         unsigned long addr1, addr2;
 831                         int f, l;
 832
 833                         if (lnasid == -1) {
 834                                 f = l = i;
 835                                 lnasid = nasid;
 836                         } else {
 837                                 f = fi;
 838                                 l = li;
 839                         }
 840                         addr1 = (base << shift) + f * (1ULL << m_io);
 841                         addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
 842                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
 843                         if (max_io < l)
 844                                 max_io = l;
 845                 }
 846                 fi = li = i;
 847                 lnasid = nasid;
 848         }
 849
 850         pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
 851
 852         if (max_io >= 0)
 853                 map_high(id, base, shift, m_io, max_io, map_uc);
 854 }
 855
 856 static __init void map_mmioh_high(int min_pnode, int max_pnode)
 857 {
 858         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 859         unsigned long mmr, base;
 860         int shift, enable, m_io, n_io;
 861
 862         if (is_uv3_hub() || is_uv4_hub()) {
 863                 /* Map both MMIOH regions: */
 864                 map_mmioh_high_uv34(0, min_pnode, max_pnode);
 865                 map_mmioh_high_uv34(1, min_pnode, max_pnode);
 866                 return;
 867         }
 868
 869         if (is_uv2_hub()) {
 870                 mmr     = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
 871                 shift   = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 872                 mmioh.v = uv_read_local_mmr(mmr);
 873                 enable  = !!mmioh.s2.enable;
 874                 base    = mmioh.s2.base;
 875                 m_io    = mmioh.s2.m_io;
 876                 n_io    = mmioh.s2.n_io;
 877
 878                 if (enable) {
 879                         max_pnode &= (1 << n_io) - 1;
 880                         pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
 881                                 base, shift, m_io, n_io, max_pnode);
 882                         map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
 883                 } else {
 884                         pr_info("UV: MMIOH disabled\n");
 885                 }
 886         }
 887 }
 888
 889 static __init void map_low_mmrs(void)
 890 {
 891         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 892         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 893 }
 894
 895 static __init void uv_rtc_init(void)
 896 {
 897         long status;
 898         u64 ticks_per_sec;
 899
 900         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
 901
 902         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 903                 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
 904
 905                 /* BIOS gives wrong value for clock frequency, so guess: */
 906                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 907         } else {
 908                 sn_rtc_cycles_per_second = ticks_per_sec;
 909         }
 910 }
 911
 912 /*
 913  * percpu heartbeat timer
 914  */
 915 static void uv_heartbeat(struct timer_list *timer)
 916 {
 917         unsigned char bits = uv_scir_info->state;
 918
 919         /* Flip heartbeat bit: */
 920         bits ^= SCIR_CPU_HEARTBEAT;
 921
 922         /* Is this CPU idle? */
 923         if (idle_cpu(raw_smp_processor_id()))
 924                 bits &= ~SCIR_CPU_ACTIVITY;
 925         else
 926                 bits |= SCIR_CPU_ACTIVITY;
 927
 928         /* Update system controller interface reg: */
 929         uv_set_scir_bits(bits);
 930
 931         /* Enable next timer period: */
 932         mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 933 }
 934
 935 static int uv_heartbeat_enable(unsigned int cpu)
 936 {
 937         while (!uv_cpu_scir_info(cpu)->enabled) {
 938                 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
 939
 940                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 941                 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
 942                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 943                 add_timer_on(timer, cpu);
 944                 uv_cpu_scir_info(cpu)->enabled = 1;
 945
 946                 /* Also ensure that boot CPU is enabled: */
 947                 cpu = 0;
 948         }
 949         return 0;
 950 }
 951
 952 #ifdef CONFIG_HOTPLUG_CPU
 953 static int uv_heartbeat_disable(unsigned int cpu)
 954 {
 955         if (uv_cpu_scir_info(cpu)->enabled) {
 956                 uv_cpu_scir_info(cpu)->enabled = 0;
 957                 del_timer(&uv_cpu_scir_info(cpu)->timer);
 958         }
 959         uv_set_cpu_scir_bits(cpu, 0xff);
 960         return 0;
 961 }
 962
 963 static __init void uv_scir_register_cpu_notifier(void)
 964 {
 965         cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
 966                                   uv_heartbeat_enable, uv_heartbeat_disable);
 967 }
 968
 969 #else /* !CONFIG_HOTPLUG_CPU */
 970
 971 static __init void uv_scir_register_cpu_notifier(void)
 972 {
 973 }
 974
 975 static __init int uv_init_heartbeat(void)
 976 {
 977         int cpu;
 978
 979         if (is_uv_system()) {
 980                 for_each_online_cpu(cpu)
 981                         uv_heartbeat_enable(cpu);
 982         }
 983
 984         return 0;
 985 }
 986
 987 late_initcall(uv_init_heartbeat);
 988
 989 #endif /* !CONFIG_HOTPLUG_CPU */
 990
 991 /* Direct Legacy VGA I/O traffic to designated IOH */
 992 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
 993 {
 994         int domain, bus, rc;
 995
 996         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
 997                 return 0;
 998
 999         if ((command_bits & PCI_COMMAND_IO) == 0)
1000                 return 0;
1001
1002         domain = pci_domain_nr(pdev->bus);
1003         bus = pdev->bus->number;
1004
1005         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1006
1007         return rc;
1008 }
1009
1010 /*
1011  * Called on each CPU to initialize the per_cpu UV data area.
1012  * FIXME: hotplug not supported yet
1013  */
1014 void uv_cpu_init(void)
1015 {
1016         /* CPU 0 initialization will be done via uv_system_init. */
1017         if (smp_processor_id() == 0)
1018                 return;
1019
1020         uv_hub_info->nr_online_cpus++;
1021 }
1022
1023 struct mn {
1024         unsigned char   m_val;
1025         unsigned char   n_val;
1026         unsigned char   m_shift;
1027         unsigned char   n_lshift;
1028 };
1029
1030 static void get_mn(struct mn *mnp)
1031 {
1032         union uvh_rh_gam_config_mmr_u m_n_config;
1033         union uv3h_gr0_gam_gr_config_u m_gr_config;
1034
1035         /* Make sure the whole structure is well initialized: */
1036         memset(mnp, 0, sizeof(*mnp));
1037
1038         m_n_config.v    = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1039         mnp->n_val      = m_n_config.s.n_skt;
1040
1041         if (is_uv4_hub()) {
1042                 mnp->m_val      = 0;
1043                 mnp->n_lshift   = 0;
1044         } else if (is_uv3_hub()) {
1045                 mnp->m_val      = m_n_config.s3.m_skt;
1046                 m_gr_config.v   = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1047                 mnp->n_lshift   = m_gr_config.s3.m_skt;
1048         } else if (is_uv2_hub()) {
1049                 mnp->m_val      = m_n_config.s2.m_skt;
1050                 mnp->n_lshift   = mnp->m_val == 40 ? 40 : 39;
1051         }
1052         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1053 }
1054
1055 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1056 {
1057         union uvh_node_id_u node_id;
1058         struct mn mn;
1059
1060         get_mn(&mn);
1061         hi->gpa_mask = mn.m_val ?
1062                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1063                 (1UL << uv_cpuid.gpa_shift) - 1;
1064
1065         hi->m_val               = mn.m_val;
1066         hi->n_val               = mn.n_val;
1067         hi->m_shift             = mn.m_shift;
1068         hi->n_lshift            = mn.n_lshift ? mn.n_lshift : 0;
1069         hi->hub_revision        = uv_hub_info->hub_revision;
1070         hi->pnode_mask          = uv_cpuid.pnode_mask;
1071         hi->min_pnode           = _min_pnode;
1072         hi->min_socket          = _min_socket;
1073         hi->pnode_to_socket     = _pnode_to_socket;
1074         hi->socket_to_node      = _socket_to_node;
1075         hi->socket_to_pnode     = _socket_to_pnode;
1076         hi->gr_table_len        = _gr_table_len;
1077         hi->gr_table            = _gr_table;
1078
1079         node_id.v               = uv_read_local_mmr(UVH_NODE_ID);
1080         uv_cpuid.gnode_shift    = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1081         hi->gnode_extra         = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1082         if (mn.m_val)
1083                 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1084
1085         if (uv_gp_table) {
1086                 hi->global_mmr_base     = uv_gp_table->mmr_base;
1087                 hi->global_mmr_shift    = uv_gp_table->mmr_shift;
1088                 hi->global_gru_base     = uv_gp_table->gru_base;
1089                 hi->global_gru_shift    = uv_gp_table->gru_shift;
1090                 hi->gpa_shift           = uv_gp_table->gpa_shift;
1091                 hi->gpa_mask            = (1UL << hi->gpa_shift) - 1;
1092         } else {
1093                 hi->global_mmr_base     = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1094                 hi->global_mmr_shift    = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1095         }
1096
1097         get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1098
1099         hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1100
1101         /* Show system specific info: */
1102         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1103         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1104         pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1105         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1106 }
1107
1108 static void __init decode_gam_params(unsigned long ptr)
1109 {
1110         uv_gp_table = (struct uv_gam_parameters *)ptr;
1111
1112         pr_info("UV: GAM Params...\n");
1113         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1114                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1115                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1116                 uv_gp_table->gpa_shift);
1117 }
1118
1119 static void __init decode_gam_rng_tbl(unsigned long ptr)
1120 {
1121         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1122         unsigned long lgre = 0;
1123         int index = 0;
1124         int sock_min = 999999, pnode_min = 99999;
1125         int sock_max = -1, pnode_max = -1;
1126
1127         uv_gre_table = gre;
1128         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1129                 unsigned long size = ((unsigned long)(gre->limit - lgre)
1130                                         << UV_GAM_RANGE_SHFT);
1131                 int order = 0;
1132                 char suffix[] = " KMGTPE";
1133                 int flag = ' ';
1134
1135                 while (size > 9999 && order < sizeof(suffix)) {
1136                         size /= 1024;
1137                         order++;
1138                 }
1139
1140                 /* adjust max block size to current range start */
1141                 if (gre->type == 1 || gre->type == 2)
1142                         if (adj_blksize(lgre))
1143                                 flag = '*';
1144
1145                 if (!index) {
1146                         pr_info("UV: GAM Range Table...\n");
1147                         pr_info("UV:  # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1148                 }
1149                 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d   %04x  %02x %02x\n",
1150                         index++,
1151                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1152                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1153                         flag, size, suffix[order],
1154                         gre->type, gre->nasid, gre->sockid, gre->pnode);
1155
1156                 /* update to next range start */
1157                 lgre = gre->limit;
1158                 if (sock_min > gre->sockid)
1159                         sock_min = gre->sockid;
1160                 if (sock_max < gre->sockid)
1161                         sock_max = gre->sockid;
1162                 if (pnode_min > gre->pnode)
1163                         pnode_min = gre->pnode;
1164                 if (pnode_max < gre->pnode)
1165                         pnode_max = gre->pnode;
1166         }
1167         _min_socket     = sock_min;
1168         _max_socket     = sock_max;
1169         _min_pnode      = pnode_min;
1170         _max_pnode      = pnode_max;
1171         _gr_table_len   = index;
1172
1173         pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1174 }
1175
1176 static int __init decode_uv_systab(void)
1177 {
1178         struct uv_systab *st;
1179         int i;
1180
1181         /* If system is uv3 or lower, there is no extended UVsystab */
1182         if (is_uv_hubbed(0xfffffe) < uv(4) && is_uv_hubless(0xfffffe) < uv(4))
1183                 return 0;       /* No extended UVsystab required */
1184
1185         st = uv_systab;
1186         if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1187                 int rev = st ? st->revision : 0;
1188
1189                 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1190                 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1191                 uv_system_type = UV_NONE;
1192
1193                 return -EINVAL;
1194         }
1195
1196         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1197                 unsigned long ptr = st->entry[i].offset;
1198
1199                 if (!ptr)
1200                         continue;
1201
1202                 ptr = ptr + (unsigned long)st;
1203
1204                 switch (st->entry[i].type) {
1205                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1206                         decode_gam_params(ptr);
1207                         break;
1208
1209                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1210                         decode_gam_rng_tbl(ptr);
1211                         break;
1212                 }
1213         }
1214         return 0;
1215 }
1216
1217 /*
1218  * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1219  * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1220  * .. being replaced by GAM Range Table
1221  */
1222 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1223 {
1224         int i, uv_pb = 0;
1225
1226         pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1227         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1228                 unsigned long np;
1229
1230                 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1231                 if (np)
1232                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1233
1234                 uv_pb += hweight64(np);
1235         }
1236         if (uv_possible_blades != uv_pb)
1237                 uv_possible_blades = uv_pb;
1238 }
1239
1240 static void __init build_socket_tables(void)
1241 {
1242         struct uv_gam_range_entry *gre = uv_gre_table;
1243         int num, nump;
1244         int cpu, i, lnid;
1245         int minsock = _min_socket;
1246         int maxsock = _max_socket;
1247         int minpnode = _min_pnode;
1248         int maxpnode = _max_pnode;
1249         size_t bytes;
1250
1251         if (!gre) {
1252                 if (is_uv2_hub() || is_uv3_hub()) {
1253                         pr_info("UV: No UVsystab socket table, ignoring\n");
1254                         return;
1255                 }
1256                 pr_crit("UV: Error: UVsystab address translations not available!\n");
1257                 BUG();
1258         }
1259
1260         /* Build socket id -> node id, pnode */
1261         num = maxsock - minsock + 1;
1262         bytes = num * sizeof(_socket_to_node[0]);
1263         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1264         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1265
1266         nump = maxpnode - minpnode + 1;
1267         bytes = nump * sizeof(_pnode_to_socket[0]);
1268         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1269         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1270
1271         for (i = 0; i < num; i++)
1272                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1273
1274         for (i = 0; i < nump; i++)
1275                 _pnode_to_socket[i] = SOCK_EMPTY;
1276
1277         /* Fill in pnode/node/addr conversion list values: */
1278         pr_info("UV: GAM Building socket/pnode conversion tables\n");
1279         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1280                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1281                         continue;
1282                 i = gre->sockid - minsock;
1283                 /* Duplicate: */
1284                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1285                         continue;
1286                 _socket_to_pnode[i] = gre->pnode;
1287
1288                 i = gre->pnode - minpnode;
1289                 _pnode_to_socket[i] = gre->sockid;
1290
1291                 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1292                         gre->sockid, gre->type, gre->nasid,
1293                         _socket_to_pnode[gre->sockid - minsock],
1294                         _pnode_to_socket[gre->pnode - minpnode]);
1295         }
1296
1297         /* Set socket -> node values: */
1298         lnid = NUMA_NO_NODE;
1299         for_each_present_cpu(cpu) {
1300                 int nid = cpu_to_node(cpu);
1301                 int apicid, sockid;
1302
1303                 if (lnid == nid)
1304                         continue;
1305                 lnid = nid;
1306                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1307                 sockid = apicid >> uv_cpuid.socketid_shift;
1308                 _socket_to_node[sockid - minsock] = nid;
1309                 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1310                         sockid, apicid, nid);
1311         }
1312
1313         /* Set up physical blade to pnode translation from GAM Range Table: */
1314         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1315         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1316         BUG_ON(!_node_to_pnode);
1317
1318         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1319                 unsigned short sockid;
1320
1321                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1322                         if (lnid == _socket_to_node[sockid - minsock]) {
1323                                 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1324                                 break;
1325                         }
1326                 }
1327                 if (sockid > maxsock) {
1328                         pr_err("UV: socket for node %d not found!\n", lnid);
1329                         BUG();
1330                 }
1331         }
1332
1333         /*
1334          * If socket id == pnode or socket id == node for all nodes,
1335          *   system runs faster by removing corresponding conversion table.
1336          */
1337         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1338         if (minsock == 0) {
1339                 for (i = 0; i < num; i++)
1340                         if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1341                                 break;
1342                 if (i >= num) {
1343                         kfree(_socket_to_node);
1344                         _socket_to_node = NULL;
1345                         pr_info("UV: 1:1 socket_to_node table removed\n");
1346                 }
1347         }
1348         if (minsock == minpnode) {
1349                 for (i = 0; i < num; i++)
1350                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1351                                 _socket_to_pnode[i] != i + minpnode)
1352                                 break;
1353                 if (i >= num) {
1354                         kfree(_socket_to_pnode);
1355                         _socket_to_pnode = NULL;
1356                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1357                 }
1358         }
1359 }
1360
1361 /* Check which reboot to use */
1362 static void check_efi_reboot(void)
1363 {
1364         /* If EFI reboot not available, use ACPI reboot */
1365         if (!efi_enabled(EFI_BOOT))
1366                 reboot_type = BOOT_ACPI;
1367 }
1368
1369 /* Setup user proc fs files */
1370 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1371 {
1372         seq_printf(file, "0x%x\n", uv_hubbed_system);
1373         return 0;
1374 }
1375
1376 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1377 {
1378         seq_printf(file, "0x%x\n", uv_hubless_system);
1379         return 0;
1380 }
1381
1382 static int __maybe_unused proc_oemid_show(struct seq_file *file, void *data)
1383 {
1384         seq_printf(file, "%s/%s\n", oem_id, oem_table_id);
1385         return 0;
1386 }
1387
1388 static __init void uv_setup_proc_files(int hubless)
1389 {
1390         struct proc_dir_entry *pde;
1391
1392         pde = proc_mkdir(UV_PROC_NODE, NULL);
1393         proc_create_single("oemid", 0, pde, proc_oemid_show);
1394         if (hubless)
1395                 proc_create_single("hubless", 0, pde, proc_hubless_show);
1396         else
1397                 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1398 }
1399
1400 /* Initialize UV hubless systems */
1401 static __init int uv_system_init_hubless(void)
1402 {
1403         int rc;
1404
1405         /* Setup PCH NMI handler */
1406         uv_nmi_setup_hubless();
1407
1408         /* Init kernel/BIOS interface */
1409         rc = uv_bios_init();
1410         if (rc < 0)
1411                 return rc;
1412
1413         /* Process UVsystab */
1414         rc = decode_uv_systab();
1415         if (rc < 0)
1416                 return rc;
1417
1418         /* Create user access node */
1419         if (rc >= 0)
1420                 uv_setup_proc_files(1);
1421
1422         check_efi_reboot();
1423
1424         return rc;
1425 }
1426
1427 static void __init uv_system_init_hub(void)
1428 {
1429         struct uv_hub_info_s hub_info = {0};
1430         int bytes, cpu, nodeid;
1431         unsigned short min_pnode = 9999, max_pnode = 0;
1432         char *hub = is_uv4_hub() ? "UV400" :
1433                     is_uv3_hub() ? "UV300" :
1434                     is_uv2_hub() ? "UV2000/3000" : NULL;
1435
1436         if (!hub) {
1437                 pr_err("UV: Unknown/unsupported UV hub\n");
1438                 return;
1439         }
1440         pr_info("UV: Found %s hub\n", hub);
1441
1442         map_low_mmrs();
1443
1444         /* Get uv_systab for decoding: */
1445         uv_bios_init();
1446
1447         /* If there's an UVsystab problem then abort UV init: */
1448         if (decode_uv_systab() < 0)
1449                 return;
1450
1451         build_socket_tables();
1452         build_uv_gr_table();
1453         set_block_size();
1454         uv_init_hub_info(&hub_info);
1455         uv_possible_blades = num_possible_nodes();
1456         if (!_node_to_pnode)
1457                 boot_init_possible_blades(&hub_info);
1458
1459         /* uv_num_possible_blades() is really the hub count: */
1460         pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1461
1462         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1463         hub_info.coherency_domain_number = sn_coherency_id;
1464         uv_rtc_init();
1465
1466         bytes = sizeof(void *) * uv_num_possible_blades();
1467         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1468         BUG_ON(!__uv_hub_info_list);
1469
1470         bytes = sizeof(struct uv_hub_info_s);
1471         for_each_node(nodeid) {
1472                 struct uv_hub_info_s *new_hub;
1473
1474                 if (__uv_hub_info_list[nodeid]) {
1475                         pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1476                         BUG();
1477                 }
1478
1479                 /* Allocate new per hub info list */
1480                 new_hub = (nodeid == 0) ?  &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1481                 BUG_ON(!new_hub);
1482                 __uv_hub_info_list[nodeid] = new_hub;
1483                 new_hub = uv_hub_info_list(nodeid);
1484                 BUG_ON(!new_hub);
1485                 *new_hub = hub_info;
1486
1487                 /* Use information from GAM table if available: */
1488                 if (_node_to_pnode)
1489                         new_hub->pnode = _node_to_pnode[nodeid];
1490                 else /* Or fill in during CPU loop: */
1491                         new_hub->pnode = 0xffff;
1492
1493                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1494                 new_hub->memory_nid = NUMA_NO_NODE;
1495                 new_hub->nr_possible_cpus = 0;
1496                 new_hub->nr_online_cpus = 0;
1497         }
1498
1499         /* Initialize per CPU info: */
1500         for_each_possible_cpu(cpu) {
1501                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1502                 int numa_node_id;
1503                 unsigned short pnode;
1504
1505                 nodeid = cpu_to_node(cpu);
1506                 numa_node_id = numa_cpu_node(cpu);
1507                 pnode = uv_apicid_to_pnode(apicid);
1508
1509                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1510                 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1511                 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1512                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1513
1514                 /* Init memoryless node: */
1515                 if (nodeid != numa_node_id &&
1516                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1517                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1518                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1519                         uv_cpu_hub_info(cpu)->pnode = pnode;
1520
1521                 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1522         }
1523
1524         for_each_node(nodeid) {
1525                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1526
1527                 /* Add pnode info for pre-GAM list nodes without CPUs: */
1528                 if (pnode == 0xffff) {
1529                         unsigned long paddr;
1530
1531                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1532                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1533                         uv_hub_info_list(nodeid)->pnode = pnode;
1534                 }
1535                 min_pnode = min(pnode, min_pnode);
1536                 max_pnode = max(pnode, max_pnode);
1537                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1538                         nodeid,
1539                         uv_hub_info_list(nodeid)->pnode,
1540                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1541         }
1542
1543         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1544         map_gru_high(max_pnode);
1545         map_mmr_high(max_pnode);
1546         map_mmioh_high(min_pnode, max_pnode);
1547
1548         uv_nmi_setup();
1549         uv_cpu_init();
1550         uv_scir_register_cpu_notifier();
1551         uv_setup_proc_files(0);
1552
1553         /* Register Legacy VGA I/O redirection handler: */
1554         pci_register_set_vga_state(uv_set_vga_state);
1555
1556         check_efi_reboot();
1557 }
1558
1559 /*
1560  * There is a different code path needed to initialize a UV system that does
1561  * not have a "UV HUB" (referred to as "hubless").
1562  */
1563 void __init uv_system_init(void)
1564 {
1565         if (likely(!is_uv_system() && !is_uv_hubless(1)))
1566                 return;
1567
1568         if (is_uv_system())
1569                 uv_system_init_hub();
1570         else
1571                 uv_system_init_hubless();
1572 }
1573
1574 apic_driver(apic_x2apic_uv_x);