2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/crash_dump.h>
11 #include <linux/cpuhotplug.h>
12 #include <linux/cpumask.h>
13 #include <linux/proc_fs.h>
14 #include <linux/memory.h>
15 #include <linux/export.h>
16 #include <linux/pci.h>
17 #include <linux/acpi.h>
18 #include <linux/efi.h>
20 #include <asm/e820/api.h>
21 #include <asm/uv/uv_mmrs.h>
22 #include <asm/uv/uv_hub.h>
23 #include <asm/uv/bios.h>
24 #include <asm/uv/uv.h>
27 static enum uv_system_type uv_system_type;
28 static int uv_hubbed_system;
29 static int uv_hubless_system;
30 static u64 gru_start_paddr, gru_end_paddr;
31 static union uvh_apicid uvh_apicid;
32 static int uv_node_id;
34 /* Unpack OEM/TABLE ID's to be NULL terminated strings */
35 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
36 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
38 /* Information derived from CPUID: */
40 unsigned int apicid_shift;
41 unsigned int apicid_mask;
42 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */
43 unsigned int pnode_mask;
44 unsigned int gpa_shift;
45 unsigned int gnode_shift;
48 static int uv_min_hub_revision_id;
50 static struct apic apic_x2apic_uv_x;
51 static struct uv_hub_info_s uv_hub_info_node0;
53 /* Set this to use hardware error handler instead of kernel panic: */
54 static int disable_uv_undefined_panic = 1;
56 unsigned long uv_undefined(char *str)
58 if (likely(!disable_uv_undefined_panic))
59 panic("UV: error: undefined MMR: %s\n", str);
61 pr_crit("UV: error: undefined MMR: %s\n", str);
63 /* Cause a machine fault: */
66 EXPORT_SYMBOL(uv_undefined);
68 static unsigned long __init uv_early_read_mmr(unsigned long addr)
70 unsigned long val, *mmr;
72 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
74 early_iounmap(mmr, sizeof(*mmr));
79 static inline bool is_GRU_range(u64 start, u64 end)
81 return start >= gru_start_paddr && end <= gru_end_paddr;
84 static bool uv_is_untracked_pat_range(u64 start, u64 end)
86 return is_ISA_range(start, end) || is_GRU_range(start, end);
89 static void __init early_get_pnodeid(void)
91 union uvh_rh_gam_addr_map_config_u m_n_config;
94 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
97 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
99 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
100 pnode = (uv_node_id >> 1) & uv_cpuid.pnode_mask;
101 uv_cpuid.gpa_shift = 46; /* Default unless changed */
103 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
104 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
107 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
108 static int __init early_set_hub_type(void)
110 union uvh_node_id_u node_id;
113 * The NODE_ID MMR is always at offset 0.
114 * Contains the chip part # + revision.
115 * Node_id field started with 15 bits,
116 * ... now 7 but upper 8 are masked to 0.
117 * All blades/nodes have the same part # and hub revision.
119 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
120 uv_node_id = node_id.sx.node_id;
122 switch (node_id.s.part_number) {
124 /* UV4/4A only have a revision difference */
125 case UV4_HUB_PART_NUMBER:
126 uv_min_hub_revision_id = node_id.s.revision
127 + UV4_HUB_REVISION_BASE;
128 uv_hub_type_set(UV4);
129 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
130 uv_hub_type_set(UV4|UV4A);
133 case UV3_HUB_PART_NUMBER:
134 case UV3_HUB_PART_NUMBER_X:
135 uv_min_hub_revision_id = node_id.s.revision
136 + UV3_HUB_REVISION_BASE;
137 uv_hub_type_set(UV3);
140 case UV2_HUB_PART_NUMBER:
141 case UV2_HUB_PART_NUMBER_X:
142 uv_min_hub_revision_id = node_id.s.revision
143 + UV2_HUB_REVISION_BASE - 1;
144 uv_hub_type_set(UV2);
151 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
152 node_id.s.part_number, node_id.s.revision,
153 uv_min_hub_revision_id, is_uv(~0));
158 static void __init uv_tsc_check_sync(void)
166 /* Accommodate different UV arch BIOSes */
167 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
169 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
170 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
172 switch (sync_state) {
173 case UVH_TSC_SYNC_VALID:
178 case UVH_TSC_SYNC_INVALID:
183 state = "unknown: assuming valid";
187 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
189 /* Mark flag that says TSC != 0 is valid for socket 0 */
191 mark_tsc_async_resets("UV BIOS");
193 mark_tsc_unstable("UV BIOS");
196 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
198 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
199 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
202 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
203 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
205 static void set_x2apic_bits(void)
207 unsigned int eax, ebx, ecx, edx, sub_index;
208 unsigned int sid_shift;
210 cpuid(0, &eax, &ebx, &ecx, &edx);
212 pr_info("UV: CPU does not have CPUID.11\n");
216 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
217 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
218 pr_info("UV: CPUID.11 not implemented\n");
222 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
225 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
226 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
227 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
231 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
233 uv_cpuid.apicid_shift = 0;
234 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
235 uv_cpuid.socketid_shift = sid_shift;
238 static void __init early_get_apic_socketid_shift(void)
240 if (is_uv2_hub() || is_uv3_hub())
241 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
245 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
246 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
249 static void __init uv_stringify(int len, char *to, char *from)
251 /* Relies on 'to' being NULL chars so result will be NULL terminated */
252 strncpy(to, from, len-1);
255 static int __init uv_set_system_type(char *_oem_id)
258 uv_stringify(sizeof(oem_id), oem_id, _oem_id);
260 /* Set hubless type if true */
261 if (strncmp(oem_id, "SGI", 3) != 0) {
262 if (strncmp(oem_id, "NSGI", 4) != 0)
265 /* UV4 Hubless: CH */
266 if (strncmp(oem_id, "NSGI4", 5) == 0)
267 uv_hubless_system = 0x11;
269 /* UV3 Hubless: UV300/MC990X w/o hub */
271 uv_hubless_system = 0x9;
273 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
274 oem_id, oem_table_id, uv_system_type, uv_hubless_system);
279 pr_err("UV: NUMA is off, disabling UV support\n");
283 /* Set hubbed type if true */
284 uv_hub_info->hub_revision =
285 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
286 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
287 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
289 switch (uv_hub_info->hub_revision) {
290 case UV4_HUB_REVISION_BASE:
291 uv_hubbed_system = 0x11;
292 uv_hub_type_set(UV4);
295 case UV3_HUB_REVISION_BASE:
296 uv_hubbed_system = 0x9;
297 uv_hub_type_set(UV3);
300 case UV2_HUB_REVISION_BASE:
301 uv_hubbed_system = 0x5;
302 uv_hub_type_set(UV2);
309 /* Get UV hub chip part number & revision */
310 early_set_hub_type();
312 /* Other UV setup functions */
314 early_get_apic_socketid_shift();
315 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
316 x86_platform.nmi_init = uv_nmi_init;
322 /* Called early to probe for the correct APIC driver */
323 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
325 /* Set up early hub info fields for Node 0 */
326 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
328 /* If not UV, return. */
329 if (likely(uv_set_system_type(_oem_id) == 0))
332 /* Save and Decode OEM Table ID */
333 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
335 /* This is the most common hardware variant, x2apic mode */
336 if (!strcmp(oem_table_id, "UVX"))
337 uv_system_type = UV_X2APIC;
339 /* Only used for very small systems, usually 1 chassis, legacy mode */
340 else if (!strcmp(oem_table_id, "UVL"))
341 uv_system_type = UV_LEGACY_APIC;
346 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
347 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
348 uv_min_hub_revision_id);
353 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
354 pr_err("UV: Current UV Type or BIOS not supported\n");
358 enum uv_system_type get_uv_system_type(void)
360 return uv_system_type;
363 int is_uv_system(void)
365 return uv_system_type != UV_NONE;
367 EXPORT_SYMBOL_GPL(is_uv_system);
369 int is_uv_hubbed(int uvtype)
371 return (uv_hubbed_system & uvtype);
373 EXPORT_SYMBOL_GPL(is_uv_hubbed);
375 static int is_uv_hubless(int uvtype)
377 return (uv_hubless_system & uvtype);
380 void **__uv_hub_info_list;
381 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
383 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
384 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
386 short uv_possible_blades;
387 EXPORT_SYMBOL_GPL(uv_possible_blades);
389 unsigned long sn_rtc_cycles_per_second;
390 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
392 /* The following values are used for the per node hub info struct */
393 static __initdata unsigned short *_node_to_pnode;
394 static __initdata unsigned short _min_socket, _max_socket;
395 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
396 static __initdata struct uv_gam_range_entry *uv_gre_table;
397 static __initdata struct uv_gam_parameters *uv_gp_table;
398 static __initdata unsigned short *_socket_to_node;
399 static __initdata unsigned short *_socket_to_pnode;
400 static __initdata unsigned short *_pnode_to_socket;
402 static __initdata struct uv_gam_range_s *_gr_table;
404 #define SOCK_EMPTY ((unsigned short)~0)
406 /* Default UV memory block size is 2GB */
407 static unsigned long mem_block_size __initdata = (2UL << 30);
409 /* Kernel parameter to specify UV mem block size */
410 static int __init parse_mem_block_size(char *ptr)
412 unsigned long size = memparse(ptr, NULL);
414 /* Size will be rounded down by set_block_size() below */
415 mem_block_size = size;
418 early_param("uv_memblksize", parse_mem_block_size);
420 static __init int adj_blksize(u32 lgre)
422 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
425 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
426 if (IS_ALIGNED(base, size))
429 if (size >= mem_block_size)
432 mem_block_size = size;
436 static __init void set_block_size(void)
438 unsigned int order = ffs(mem_block_size);
441 /* adjust for ffs return of 1..64 */
442 set_memory_block_size_order(order - 1);
443 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
445 /* bad or zero value, default to 1UL << 31 (2GB) */
446 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
447 set_memory_block_size_order(31);
451 /* Build GAM range lookup table: */
452 static __init void build_uv_gr_table(void)
454 struct uv_gam_range_entry *gre = uv_gre_table;
455 struct uv_gam_range_s *grt;
456 unsigned long last_limit = 0, ram_limit = 0;
457 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
462 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
463 grt = kzalloc(bytes, GFP_KERNEL);
467 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
468 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
470 /* Mark hole between RAM/non-RAM: */
471 ram_limit = last_limit;
472 last_limit = gre->limit;
476 last_limit = gre->limit;
477 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
480 if (_max_socket < gre->sockid) {
481 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
484 sid = gre->sockid - _min_socket;
487 grt = &_gr_table[indx];
489 grt->nasid = gre->nasid;
490 grt->limit = last_limit = gre->limit;
496 if (lsid == sid && !ram_limit) {
497 /* .. if contiguous: */
498 if (grt->limit == last_limit) {
499 grt->limit = last_limit = gre->limit;
503 /* Non-contiguous RAM range: */
507 grt->nasid = gre->nasid;
508 grt->limit = last_limit = gre->limit;
511 /* Non-contiguous/non-RAM: */
513 /* base is this entry */
514 grt->base = grt - _gr_table;
515 grt->nasid = gre->nasid;
516 grt->limit = last_limit = gre->limit;
520 /* Shorten table if possible */
523 if (i < _gr_table_len) {
526 bytes = i * sizeof(struct uv_gam_range_s);
527 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
534 /* Display resultant GAM range table: */
535 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
536 unsigned long start, end;
539 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
540 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
542 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
546 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
551 pnode = uv_apicid_to_pnode(phys_apicid);
553 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
554 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
555 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
558 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
560 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
561 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
562 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
565 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
570 static void uv_send_IPI_one(int cpu, int vector)
572 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
573 int pnode = uv_apicid_to_pnode(apicid);
574 unsigned long dmode, val;
576 if (vector == NMI_VECTOR)
581 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
582 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
583 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
584 (vector << UVH_IPI_INT_VECTOR_SHFT);
586 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
589 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
593 for_each_cpu(cpu, mask)
594 uv_send_IPI_one(cpu, vector);
597 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
599 unsigned int this_cpu = smp_processor_id();
602 for_each_cpu(cpu, mask) {
604 uv_send_IPI_one(cpu, vector);
608 static void uv_send_IPI_allbutself(int vector)
610 unsigned int this_cpu = smp_processor_id();
613 for_each_online_cpu(cpu) {
615 uv_send_IPI_one(cpu, vector);
619 static void uv_send_IPI_all(int vector)
621 uv_send_IPI_mask(cpu_online_mask, vector);
624 static int uv_apic_id_valid(u32 apicid)
629 static int uv_apic_id_registered(void)
634 static void uv_init_apic_ldr(void)
638 static u32 apic_uv_calc_apicid(unsigned int cpu)
640 return apic_default_calc_apicid(cpu);
643 static unsigned int x2apic_get_apic_id(unsigned long id)
648 static u32 set_apic_id(unsigned int id)
653 static unsigned int uv_read_apic_id(void)
655 return x2apic_get_apic_id(apic_read(APIC_ID));
658 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
660 return uv_read_apic_id() >> index_msb;
663 static void uv_send_IPI_self(int vector)
665 apic_write(APIC_SELF_IPI, vector);
668 static int uv_probe(void)
670 return apic == &apic_x2apic_uv_x;
673 static struct apic apic_x2apic_uv_x __ro_after_init = {
675 .name = "UV large system",
677 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
678 .apic_id_valid = uv_apic_id_valid,
679 .apic_id_registered = uv_apic_id_registered,
681 .irq_delivery_mode = dest_Fixed,
682 .irq_dest_mode = 0, /* Physical */
685 .dest_logical = APIC_DEST_LOGICAL,
686 .check_apicid_used = NULL,
688 .init_apic_ldr = uv_init_apic_ldr,
690 .ioapic_phys_id_map = NULL,
691 .setup_apic_routing = NULL,
692 .cpu_present_to_apicid = default_cpu_present_to_apicid,
693 .apicid_to_cpu_present = NULL,
694 .check_phys_apicid_present = default_check_phys_apicid_present,
695 .phys_pkg_id = uv_phys_pkg_id,
697 .get_apic_id = x2apic_get_apic_id,
698 .set_apic_id = set_apic_id,
700 .calc_dest_apicid = apic_uv_calc_apicid,
702 .send_IPI = uv_send_IPI_one,
703 .send_IPI_mask = uv_send_IPI_mask,
704 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
705 .send_IPI_allbutself = uv_send_IPI_allbutself,
706 .send_IPI_all = uv_send_IPI_all,
707 .send_IPI_self = uv_send_IPI_self,
709 .wakeup_secondary_cpu = uv_wakeup_secondary,
710 .inquire_remote_apic = NULL,
712 .read = native_apic_msr_read,
713 .write = native_apic_msr_write,
714 .eoi_write = native_apic_msr_eoi_write,
715 .icr_read = native_x2apic_icr_read,
716 .icr_write = native_x2apic_icr_write,
717 .wait_icr_idle = native_x2apic_wait_icr_idle,
718 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
721 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
722 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
724 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
726 union uvh_rh_gam_alias_2_overlay_config_u alias;
727 union uvh_rh_gam_alias_2_redirect_config_u redirect;
728 unsigned long m_redirect;
729 unsigned long m_overlay;
732 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
735 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
736 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
739 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
740 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
743 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
744 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
747 alias.v = uv_read_local_mmr(m_overlay);
748 if (alias.s.enable && alias.s.base == 0) {
749 *size = (1UL << alias.s.m_alias);
750 redirect.v = uv_read_local_mmr(m_redirect);
751 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
758 enum map_type {map_wb, map_uc};
760 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
762 unsigned long bytes, paddr;
764 paddr = base << pshift;
765 bytes = (1UL << bshift) * (max_pnode + 1);
767 pr_info("UV: Map %s_HI base address NULL\n", id);
770 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
771 if (map_type == map_uc)
772 init_extra_mapping_uc(paddr, bytes);
774 init_extra_mapping_wb(paddr, bytes);
777 static __init void map_gru_high(int max_pnode)
779 union uvh_rh_gam_gru_overlay_config_u gru;
780 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
781 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
784 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
786 pr_info("UV: GRU disabled\n");
790 base = (gru.v & mask) >> shift;
791 map_high("GRU", base, shift, shift, max_pnode, map_wb);
792 gru_start_paddr = ((u64)base << shift);
793 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
796 static __init void map_mmr_high(int max_pnode)
798 union uvh_rh_gam_mmr_overlay_config_u mmr;
799 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
801 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
803 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
805 pr_info("UV: MMR disabled\n");
808 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
809 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
811 unsigned long overlay;
814 unsigned long nasid_mask;
815 unsigned long m_overlay;
816 int i, n, shift, m_io, max_io;
817 int nasid, lnasid, fi, li;
822 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0;
823 overlay = uv_read_local_mmr(m_overlay);
824 base = overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
825 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
826 m_io = (overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK)
827 >> UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT;
828 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT;
829 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
830 nasid_mask = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK;
833 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1;
834 overlay = uv_read_local_mmr(m_overlay);
835 base = overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
836 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
837 m_io = (overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK)
838 >> UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT;
839 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT;
840 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
841 nasid_mask = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK;
843 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
844 if (!(overlay & UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK)) {
845 pr_info("UV: %s disabled\n", id);
849 /* Convert to NASID: */
852 max_io = lnasid = fi = li = -1;
854 for (i = 0; i < n; i++) {
855 unsigned long m_redirect = mmr + i * 8;
856 unsigned long redirect = uv_read_local_mmr(m_redirect);
858 nasid = redirect & nasid_mask;
860 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
861 id, redirect, m_redirect, nasid);
864 if (nasid < min_pnode || max_pnode < nasid)
867 if (nasid == lnasid) {
869 /* Last entry check: */
874 /* Check if we have a cached (or last) redirect to print: */
875 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
876 unsigned long addr1, addr2;
886 addr1 = (base << shift) + f * (1ULL << m_io);
887 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
888 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
896 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
899 map_high(id, base, shift, m_io, max_io, map_uc);
902 static __init void map_mmioh_high(int min_pnode, int max_pnode)
904 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
905 unsigned long mmr, base;
906 int shift, enable, m_io, n_io;
908 if (is_uv3_hub() || is_uv4_hub()) {
909 /* Map both MMIOH regions: */
910 map_mmioh_high_uv34(0, min_pnode, max_pnode);
911 map_mmioh_high_uv34(1, min_pnode, max_pnode);
916 mmr = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG;
917 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT;
918 mmioh.v = uv_read_local_mmr(mmr);
919 enable = !!mmioh.s2.enable;
920 base = mmioh.s2.base;
921 m_io = mmioh.s2.m_io;
922 n_io = mmioh.s2.n_io;
925 max_pnode &= (1 << n_io) - 1;
926 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
927 base, shift, m_io, n_io, max_pnode);
928 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
930 pr_info("UV: MMIOH disabled\n");
935 static __init void map_low_mmrs(void)
937 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
938 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
941 static __init void uv_rtc_init(void)
946 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
948 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
949 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
951 /* BIOS gives wrong value for clock frequency, so guess: */
952 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
954 sn_rtc_cycles_per_second = ticks_per_sec;
958 /* Direct Legacy VGA I/O traffic to designated IOH */
959 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
963 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
966 if ((command_bits & PCI_COMMAND_IO) == 0)
969 domain = pci_domain_nr(pdev->bus);
970 bus = pdev->bus->number;
972 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
978 * Called on each CPU to initialize the per_cpu UV data area.
979 * FIXME: hotplug not supported yet
981 void uv_cpu_init(void)
983 /* CPU 0 initialization will be done via uv_system_init. */
984 if (smp_processor_id() == 0)
987 uv_hub_info->nr_online_cpus++;
993 unsigned char m_shift;
994 unsigned char n_lshift;
997 static void get_mn(struct mn *mnp)
999 union uvh_rh_gam_addr_map_config_u m_n_config;
1000 union uvyh_gr0_gam_gr_config_u m_gr_config;
1002 /* Make sure the whole structure is well initialized: */
1003 memset(mnp, 0, sizeof(*mnp));
1005 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
1006 mnp->n_val = m_n_config.s.n_skt;
1011 } else if (is_uv3_hub()) {
1012 mnp->m_val = m_n_config.s3.m_skt;
1013 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1014 mnp->n_lshift = m_gr_config.s3.m_skt;
1015 } else if (is_uv2_hub()) {
1016 mnp->m_val = m_n_config.s2.m_skt;
1017 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1019 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1022 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1027 hi->gpa_mask = mn.m_val ?
1028 (1UL << (mn.m_val + mn.n_val)) - 1 :
1029 (1UL << uv_cpuid.gpa_shift) - 1;
1031 hi->m_val = mn.m_val;
1032 hi->n_val = mn.n_val;
1033 hi->m_shift = mn.m_shift;
1034 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1035 hi->hub_revision = uv_hub_info->hub_revision;
1036 hi->hub_type = uv_hub_info->hub_type;
1037 hi->pnode_mask = uv_cpuid.pnode_mask;
1038 hi->min_pnode = _min_pnode;
1039 hi->min_socket = _min_socket;
1040 hi->pnode_to_socket = _pnode_to_socket;
1041 hi->socket_to_node = _socket_to_node;
1042 hi->socket_to_pnode = _socket_to_pnode;
1043 hi->gr_table_len = _gr_table_len;
1044 hi->gr_table = _gr_table;
1046 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1047 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1049 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1052 hi->global_mmr_base = uv_gp_table->mmr_base;
1053 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1054 hi->global_gru_base = uv_gp_table->gru_base;
1055 hi->global_gru_shift = uv_gp_table->gru_shift;
1056 hi->gpa_shift = uv_gp_table->gpa_shift;
1057 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1059 hi->global_mmr_base =
1060 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1062 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1065 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1067 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1069 /* Show system specific info: */
1070 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1071 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1072 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1073 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1076 static void __init decode_gam_params(unsigned long ptr)
1078 uv_gp_table = (struct uv_gam_parameters *)ptr;
1080 pr_info("UV: GAM Params...\n");
1081 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1082 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1083 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1084 uv_gp_table->gpa_shift);
1087 static void __init decode_gam_rng_tbl(unsigned long ptr)
1089 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1090 unsigned long lgre = 0;
1092 int sock_min = 999999, pnode_min = 99999;
1093 int sock_max = -1, pnode_max = -1;
1096 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1097 unsigned long size = ((unsigned long)(gre->limit - lgre)
1098 << UV_GAM_RANGE_SHFT);
1100 char suffix[] = " KMGTPE";
1103 while (size > 9999 && order < sizeof(suffix)) {
1108 /* adjust max block size to current range start */
1109 if (gre->type == 1 || gre->type == 2)
1110 if (adj_blksize(lgre))
1114 pr_info("UV: GAM Range Table...\n");
1115 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1117 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1119 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1120 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1121 flag, size, suffix[order],
1122 gre->type, gre->nasid, gre->sockid, gre->pnode);
1124 /* update to next range start */
1126 if (sock_min > gre->sockid)
1127 sock_min = gre->sockid;
1128 if (sock_max < gre->sockid)
1129 sock_max = gre->sockid;
1130 if (pnode_min > gre->pnode)
1131 pnode_min = gre->pnode;
1132 if (pnode_max < gre->pnode)
1133 pnode_max = gre->pnode;
1135 _min_socket = sock_min;
1136 _max_socket = sock_max;
1137 _min_pnode = pnode_min;
1138 _max_pnode = pnode_max;
1139 _gr_table_len = index;
1141 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1144 static int __init decode_uv_systab(void)
1146 struct uv_systab *st;
1149 /* If system is uv3 or lower, there is no extended UVsystab */
1150 if (is_uv_hubbed(0xfffffe) < uv(4) && is_uv_hubless(0xfffffe) < uv(4))
1151 return 0; /* No extended UVsystab required */
1154 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1155 int rev = st ? st->revision : 0;
1157 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1158 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1159 uv_system_type = UV_NONE;
1164 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1165 unsigned long ptr = st->entry[i].offset;
1170 ptr = ptr + (unsigned long)st;
1172 switch (st->entry[i].type) {
1173 case UV_SYSTAB_TYPE_GAM_PARAMS:
1174 decode_gam_params(ptr);
1177 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1178 decode_gam_rng_tbl(ptr);
1185 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
1186 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1190 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1191 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1194 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1196 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1198 uv_pb += hweight64(np);
1200 if (uv_possible_blades != uv_pb)
1201 uv_possible_blades = uv_pb;
1204 static void __init build_socket_tables(void)
1206 struct uv_gam_range_entry *gre = uv_gre_table;
1209 int minsock = _min_socket;
1210 int maxsock = _max_socket;
1211 int minpnode = _min_pnode;
1212 int maxpnode = _max_pnode;
1216 if (is_uv2_hub() || is_uv3_hub()) {
1217 pr_info("UV: No UVsystab socket table, ignoring\n");
1220 pr_crit("UV: Error: UVsystab address translations not available!\n");
1224 /* Build socket id -> node id, pnode */
1225 num = maxsock - minsock + 1;
1226 bytes = num * sizeof(_socket_to_node[0]);
1227 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1228 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1230 nump = maxpnode - minpnode + 1;
1231 bytes = nump * sizeof(_pnode_to_socket[0]);
1232 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1233 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1235 for (i = 0; i < num; i++)
1236 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1238 for (i = 0; i < nump; i++)
1239 _pnode_to_socket[i] = SOCK_EMPTY;
1241 /* Fill in pnode/node/addr conversion list values: */
1242 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1243 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1244 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1246 i = gre->sockid - minsock;
1248 if (_socket_to_pnode[i] != SOCK_EMPTY)
1250 _socket_to_pnode[i] = gre->pnode;
1252 i = gre->pnode - minpnode;
1253 _pnode_to_socket[i] = gre->sockid;
1255 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1256 gre->sockid, gre->type, gre->nasid,
1257 _socket_to_pnode[gre->sockid - minsock],
1258 _pnode_to_socket[gre->pnode - minpnode]);
1261 /* Set socket -> node values: */
1262 lnid = NUMA_NO_NODE;
1263 for_each_present_cpu(cpu) {
1264 int nid = cpu_to_node(cpu);
1270 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1271 sockid = apicid >> uv_cpuid.socketid_shift;
1272 _socket_to_node[sockid - minsock] = nid;
1273 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1274 sockid, apicid, nid);
1277 /* Set up physical blade to pnode translation from GAM Range Table: */
1278 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1279 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1280 BUG_ON(!_node_to_pnode);
1282 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1283 unsigned short sockid;
1285 for (sockid = minsock; sockid <= maxsock; sockid++) {
1286 if (lnid == _socket_to_node[sockid - minsock]) {
1287 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1291 if (sockid > maxsock) {
1292 pr_err("UV: socket for node %d not found!\n", lnid);
1298 * If socket id == pnode or socket id == node for all nodes,
1299 * system runs faster by removing corresponding conversion table.
1301 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1303 for (i = 0; i < num; i++)
1304 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1307 kfree(_socket_to_node);
1308 _socket_to_node = NULL;
1309 pr_info("UV: 1:1 socket_to_node table removed\n");
1312 if (minsock == minpnode) {
1313 for (i = 0; i < num; i++)
1314 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1315 _socket_to_pnode[i] != i + minpnode)
1318 kfree(_socket_to_pnode);
1319 _socket_to_pnode = NULL;
1320 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1325 /* Check which reboot to use */
1326 static void check_efi_reboot(void)
1328 /* If EFI reboot not available, use ACPI reboot */
1329 if (!efi_enabled(EFI_BOOT))
1330 reboot_type = BOOT_ACPI;
1333 /* Setup user proc fs files */
1334 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1336 seq_printf(file, "0x%x\n", uv_hubbed_system);
1340 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1342 seq_printf(file, "0x%x\n", uv_hubless_system);
1346 static int __maybe_unused proc_oemid_show(struct seq_file *file, void *data)
1348 seq_printf(file, "%s/%s\n", oem_id, oem_table_id);
1352 static __init void uv_setup_proc_files(int hubless)
1354 struct proc_dir_entry *pde;
1356 pde = proc_mkdir(UV_PROC_NODE, NULL);
1357 proc_create_single("oemid", 0, pde, proc_oemid_show);
1359 proc_create_single("hubless", 0, pde, proc_hubless_show);
1361 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1364 /* Initialize UV hubless systems */
1365 static __init int uv_system_init_hubless(void)
1369 /* Setup PCH NMI handler */
1370 uv_nmi_setup_hubless();
1372 /* Init kernel/BIOS interface */
1373 rc = uv_bios_init();
1377 /* Process UVsystab */
1378 rc = decode_uv_systab();
1382 /* Create user access node */
1384 uv_setup_proc_files(1);
1391 static void __init uv_system_init_hub(void)
1393 struct uv_hub_info_s hub_info = {0};
1394 int bytes, cpu, nodeid;
1395 unsigned short min_pnode = 9999, max_pnode = 0;
1396 char *hub = is_uv4_hub() ? "UV400" :
1397 is_uv3_hub() ? "UV300" :
1398 is_uv2_hub() ? "UV2000/3000" : NULL;
1401 pr_err("UV: Unknown/unsupported UV hub\n");
1404 pr_info("UV: Found %s hub\n", hub);
1408 /* Get uv_systab for decoding: */
1411 /* If there's an UVsystab problem then abort UV init: */
1412 if (decode_uv_systab() < 0)
1415 build_socket_tables();
1416 build_uv_gr_table();
1418 uv_init_hub_info(&hub_info);
1419 uv_possible_blades = num_possible_nodes();
1420 if (!_node_to_pnode)
1421 boot_init_possible_blades(&hub_info);
1423 /* uv_num_possible_blades() is really the hub count: */
1424 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1426 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1427 hub_info.coherency_domain_number = sn_coherency_id;
1430 bytes = sizeof(void *) * uv_num_possible_blades();
1431 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1432 BUG_ON(!__uv_hub_info_list);
1434 bytes = sizeof(struct uv_hub_info_s);
1435 for_each_node(nodeid) {
1436 struct uv_hub_info_s *new_hub;
1438 if (__uv_hub_info_list[nodeid]) {
1439 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1443 /* Allocate new per hub info list */
1444 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1446 __uv_hub_info_list[nodeid] = new_hub;
1447 new_hub = uv_hub_info_list(nodeid);
1449 *new_hub = hub_info;
1451 /* Use information from GAM table if available: */
1453 new_hub->pnode = _node_to_pnode[nodeid];
1454 else /* Or fill in during CPU loop: */
1455 new_hub->pnode = 0xffff;
1457 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1458 new_hub->memory_nid = NUMA_NO_NODE;
1459 new_hub->nr_possible_cpus = 0;
1460 new_hub->nr_online_cpus = 0;
1463 /* Initialize per CPU info: */
1464 for_each_possible_cpu(cpu) {
1465 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1467 unsigned short pnode;
1469 nodeid = cpu_to_node(cpu);
1470 numa_node_id = numa_cpu_node(cpu);
1471 pnode = uv_apicid_to_pnode(apicid);
1473 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1474 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1475 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1476 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1478 /* Init memoryless node: */
1479 if (nodeid != numa_node_id &&
1480 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1481 uv_hub_info_list(numa_node_id)->pnode = pnode;
1482 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1483 uv_cpu_hub_info(cpu)->pnode = pnode;
1486 for_each_node(nodeid) {
1487 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1489 /* Add pnode info for pre-GAM list nodes without CPUs: */
1490 if (pnode == 0xffff) {
1491 unsigned long paddr;
1493 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1494 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1495 uv_hub_info_list(nodeid)->pnode = pnode;
1497 min_pnode = min(pnode, min_pnode);
1498 max_pnode = max(pnode, max_pnode);
1499 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1501 uv_hub_info_list(nodeid)->pnode,
1502 uv_hub_info_list(nodeid)->nr_possible_cpus);
1505 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1506 map_gru_high(max_pnode);
1507 map_mmr_high(max_pnode);
1508 map_mmioh_high(min_pnode, max_pnode);
1512 uv_setup_proc_files(0);
1514 /* Register Legacy VGA I/O redirection handler: */
1515 pci_register_set_vga_state(uv_set_vga_state);
1521 * There is a different code path needed to initialize a UV system that does
1522 * not have a "UV HUB" (referred to as "hubless").
1524 void __init uv_system_init(void)
1526 if (likely(!is_uv_system() && !is_uv_hubless(1)))
1530 uv_system_init_hub();
1532 uv_system_init_hubless();
1535 apic_driver(apic_x2apic_uv_x);