2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/crash_dump.h>
11 #include <linux/cpuhotplug.h>
12 #include <linux/cpumask.h>
13 #include <linux/proc_fs.h>
14 #include <linux/memory.h>
15 #include <linux/export.h>
16 #include <linux/pci.h>
17 #include <linux/acpi.h>
18 #include <linux/efi.h>
20 #include <asm/e820/api.h>
21 #include <asm/uv/uv_mmrs.h>
22 #include <asm/uv/uv_hub.h>
23 #include <asm/uv/bios.h>
24 #include <asm/uv/uv.h>
27 static enum uv_system_type uv_system_type;
28 static int uv_hubbed_system;
29 static int uv_hubless_system;
30 static u64 gru_start_paddr, gru_end_paddr;
31 static union uvh_apicid uvh_apicid;
33 /* Unpack OEM/TABLE ID's to be NULL terminated strings */
34 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
35 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
37 /* Information derived from CPUID: */
39 unsigned int apicid_shift;
40 unsigned int apicid_mask;
41 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */
42 unsigned int pnode_mask;
43 unsigned int gpa_shift;
44 unsigned int gnode_shift;
47 static int uv_min_hub_revision_id;
49 static struct apic apic_x2apic_uv_x;
50 static struct uv_hub_info_s uv_hub_info_node0;
52 /* Set this to use hardware error handler instead of kernel panic: */
53 static int disable_uv_undefined_panic = 1;
55 unsigned long uv_undefined(char *str)
57 if (likely(!disable_uv_undefined_panic))
58 panic("UV: error: undefined MMR: %s\n", str);
60 pr_crit("UV: error: undefined MMR: %s\n", str);
62 /* Cause a machine fault: */
65 EXPORT_SYMBOL(uv_undefined);
67 static unsigned long __init uv_early_read_mmr(unsigned long addr)
69 unsigned long val, *mmr;
71 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
73 early_iounmap(mmr, sizeof(*mmr));
78 static inline bool is_GRU_range(u64 start, u64 end)
80 return start >= gru_start_paddr && end <= gru_end_paddr;
83 static bool uv_is_untracked_pat_range(u64 start, u64 end)
85 return is_ISA_range(start, end) || is_GRU_range(start, end);
88 static int __init early_get_pnodeid(void)
90 union uvh_node_id_u node_id;
91 union uvh_rh_gam_config_mmr_u m_n_config;
94 /* Currently, all blades have same revision number */
95 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
96 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
97 uv_min_hub_revision_id = node_id.s.revision;
99 switch (node_id.s.part_number) {
100 case UV2_HUB_PART_NUMBER:
101 case UV2_HUB_PART_NUMBER_X:
102 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
104 case UV3_HUB_PART_NUMBER:
105 case UV3_HUB_PART_NUMBER_X:
106 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
109 /* Update: UV4A has only a modified revision to indicate HUB fixes */
110 case UV4_HUB_PART_NUMBER:
111 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
112 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
116 uv_hub_info->hub_revision = uv_min_hub_revision_id;
117 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
118 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
119 uv_cpuid.gpa_shift = 46; /* Default unless changed */
121 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
122 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
123 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
127 static void __init uv_tsc_check_sync(void)
135 /* Accommodate different UV arch BIOSes */
136 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
138 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
139 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
141 switch (sync_state) {
142 case UVH_TSC_SYNC_VALID:
147 case UVH_TSC_SYNC_INVALID:
152 state = "unknown: assuming valid";
156 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
158 /* Mark flag that says TSC != 0 is valid for socket 0 */
160 mark_tsc_async_resets("UV BIOS");
162 mark_tsc_unstable("UV BIOS");
165 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
167 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
168 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
171 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
172 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
174 static void set_x2apic_bits(void)
176 unsigned int eax, ebx, ecx, edx, sub_index;
177 unsigned int sid_shift;
179 cpuid(0, &eax, &ebx, &ecx, &edx);
181 pr_info("UV: CPU does not have CPUID.11\n");
185 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
186 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
187 pr_info("UV: CPUID.11 not implemented\n");
191 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
194 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
195 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
196 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
200 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
202 uv_cpuid.apicid_shift = 0;
203 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
204 uv_cpuid.socketid_shift = sid_shift;
207 static void __init early_get_apic_socketid_shift(void)
209 if (is_uv2_hub() || is_uv3_hub())
210 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
214 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
215 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
218 static void __init uv_stringify(int len, char *to, char *from)
220 /* Relies on 'to' being NULL chars so result will be NULL terminated */
221 strncpy(to, from, len-1);
224 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
229 uv_stringify(sizeof(oem_id), oem_id, _oem_id);
230 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
232 if (strncmp(oem_id, "SGI", 3) != 0) {
233 if (strncmp(oem_id, "NSGI", 4) != 0)
236 /* UV4 Hubless, CH, (0x11:UV4+Any) */
237 if (strncmp(oem_id, "NSGI4", 5) == 0)
238 uv_hubless_system = 0x11;
240 /* UV3 Hubless, UV300/MC990X w/o hub (0x9:UV3+Any) */
242 uv_hubless_system = 0x9;
244 pr_info("UV: OEM IDs %s/%s, HUBLESS(0x%x)\n",
245 oem_id, oem_table_id, uv_hubless_system);
251 pr_err("UV: NUMA is off, disabling UV support\n");
255 /* Set up early hub type field in uv_hub_info for Node 0 */
256 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
259 * Determine UV arch type.
261 * SGI3: UV300 (truncated to 4 chars because of different varieties)
262 * SGI4: UV400 (truncated to 4 chars because of different varieties)
264 if (!strncmp(oem_id, "SGI4", 4)) {
265 uv_hub_info->hub_revision = UV4_HUB_REVISION_BASE;
266 uv_hubbed_system = 0x11;
268 } else if (!strncmp(oem_id, "SGI3", 4)) {
269 uv_hub_info->hub_revision = UV3_HUB_REVISION_BASE;
270 uv_hubbed_system = 0x9;
272 } else if (!strcmp(oem_id, "SGI2")) {
273 uv_hub_info->hub_revision = UV2_HUB_REVISION_BASE;
274 uv_hubbed_system = 0x5;
277 uv_hub_info->hub_revision = 0;
281 pnodeid = early_get_pnodeid();
282 early_get_apic_socketid_shift();
284 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
285 x86_platform.nmi_init = uv_nmi_init;
287 if (!strcmp(oem_table_id, "UVX")) {
288 /* This is the most common hardware variant: */
289 uv_system_type = UV_X2APIC;
292 } else if (!strcmp(oem_table_id, "UVL")) {
293 /* Only used for very small systems: */
294 uv_system_type = UV_LEGACY_APIC;
301 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
307 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
308 pr_err("Current UV Type or BIOS not supported\n");
312 enum uv_system_type get_uv_system_type(void)
314 return uv_system_type;
317 int is_uv_system(void)
319 return uv_system_type != UV_NONE;
321 EXPORT_SYMBOL_GPL(is_uv_system);
323 int is_uv_hubbed(int uvtype)
325 return (uv_hubbed_system & uvtype);
327 EXPORT_SYMBOL_GPL(is_uv_hubbed);
329 static int is_uv_hubless(int uvtype)
331 return (uv_hubless_system & uvtype);
334 void **__uv_hub_info_list;
335 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
337 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
338 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
340 short uv_possible_blades;
341 EXPORT_SYMBOL_GPL(uv_possible_blades);
343 unsigned long sn_rtc_cycles_per_second;
344 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
346 /* The following values are used for the per node hub info struct */
347 static __initdata unsigned short *_node_to_pnode;
348 static __initdata unsigned short _min_socket, _max_socket;
349 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
350 static __initdata struct uv_gam_range_entry *uv_gre_table;
351 static __initdata struct uv_gam_parameters *uv_gp_table;
352 static __initdata unsigned short *_socket_to_node;
353 static __initdata unsigned short *_socket_to_pnode;
354 static __initdata unsigned short *_pnode_to_socket;
356 static __initdata struct uv_gam_range_s *_gr_table;
358 #define SOCK_EMPTY ((unsigned short)~0)
360 /* Default UV memory block size is 2GB */
361 static unsigned long mem_block_size __initdata = (2UL << 30);
363 /* Kernel parameter to specify UV mem block size */
364 static int __init parse_mem_block_size(char *ptr)
366 unsigned long size = memparse(ptr, NULL);
368 /* Size will be rounded down by set_block_size() below */
369 mem_block_size = size;
372 early_param("uv_memblksize", parse_mem_block_size);
374 static __init int adj_blksize(u32 lgre)
376 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
379 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
380 if (IS_ALIGNED(base, size))
383 if (size >= mem_block_size)
386 mem_block_size = size;
390 static __init void set_block_size(void)
392 unsigned int order = ffs(mem_block_size);
395 /* adjust for ffs return of 1..64 */
396 set_memory_block_size_order(order - 1);
397 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
399 /* bad or zero value, default to 1UL << 31 (2GB) */
400 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
401 set_memory_block_size_order(31);
405 /* Build GAM range lookup table: */
406 static __init void build_uv_gr_table(void)
408 struct uv_gam_range_entry *gre = uv_gre_table;
409 struct uv_gam_range_s *grt;
410 unsigned long last_limit = 0, ram_limit = 0;
411 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
416 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
417 grt = kzalloc(bytes, GFP_KERNEL);
421 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
422 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
424 /* Mark hole between RAM/non-RAM: */
425 ram_limit = last_limit;
426 last_limit = gre->limit;
430 last_limit = gre->limit;
431 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
434 if (_max_socket < gre->sockid) {
435 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
438 sid = gre->sockid - _min_socket;
441 grt = &_gr_table[indx];
443 grt->nasid = gre->nasid;
444 grt->limit = last_limit = gre->limit;
450 if (lsid == sid && !ram_limit) {
451 /* .. if contiguous: */
452 if (grt->limit == last_limit) {
453 grt->limit = last_limit = gre->limit;
457 /* Non-contiguous RAM range: */
461 grt->nasid = gre->nasid;
462 grt->limit = last_limit = gre->limit;
465 /* Non-contiguous/non-RAM: */
467 /* base is this entry */
468 grt->base = grt - _gr_table;
469 grt->nasid = gre->nasid;
470 grt->limit = last_limit = gre->limit;
474 /* Shorten table if possible */
477 if (i < _gr_table_len) {
480 bytes = i * sizeof(struct uv_gam_range_s);
481 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
488 /* Display resultant GAM range table: */
489 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
490 unsigned long start, end;
493 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
494 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
496 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
500 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
505 pnode = uv_apicid_to_pnode(phys_apicid);
507 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
508 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
509 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
512 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
514 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
515 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
516 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
519 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
524 static void uv_send_IPI_one(int cpu, int vector)
526 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
527 int pnode = uv_apicid_to_pnode(apicid);
528 unsigned long dmode, val;
530 if (vector == NMI_VECTOR)
535 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
536 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
537 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
538 (vector << UVH_IPI_INT_VECTOR_SHFT);
540 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
543 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
547 for_each_cpu(cpu, mask)
548 uv_send_IPI_one(cpu, vector);
551 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
553 unsigned int this_cpu = smp_processor_id();
556 for_each_cpu(cpu, mask) {
558 uv_send_IPI_one(cpu, vector);
562 static void uv_send_IPI_allbutself(int vector)
564 unsigned int this_cpu = smp_processor_id();
567 for_each_online_cpu(cpu) {
569 uv_send_IPI_one(cpu, vector);
573 static void uv_send_IPI_all(int vector)
575 uv_send_IPI_mask(cpu_online_mask, vector);
578 static int uv_apic_id_valid(u32 apicid)
583 static int uv_apic_id_registered(void)
588 static void uv_init_apic_ldr(void)
592 static u32 apic_uv_calc_apicid(unsigned int cpu)
594 return apic_default_calc_apicid(cpu);
597 static unsigned int x2apic_get_apic_id(unsigned long id)
602 static u32 set_apic_id(unsigned int id)
607 static unsigned int uv_read_apic_id(void)
609 return x2apic_get_apic_id(apic_read(APIC_ID));
612 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
614 return uv_read_apic_id() >> index_msb;
617 static void uv_send_IPI_self(int vector)
619 apic_write(APIC_SELF_IPI, vector);
622 static int uv_probe(void)
624 return apic == &apic_x2apic_uv_x;
627 static struct apic apic_x2apic_uv_x __ro_after_init = {
629 .name = "UV large system",
631 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
632 .apic_id_valid = uv_apic_id_valid,
633 .apic_id_registered = uv_apic_id_registered,
635 .irq_delivery_mode = dest_Fixed,
636 .irq_dest_mode = 0, /* Physical */
639 .dest_logical = APIC_DEST_LOGICAL,
640 .check_apicid_used = NULL,
642 .init_apic_ldr = uv_init_apic_ldr,
644 .ioapic_phys_id_map = NULL,
645 .setup_apic_routing = NULL,
646 .cpu_present_to_apicid = default_cpu_present_to_apicid,
647 .apicid_to_cpu_present = NULL,
648 .check_phys_apicid_present = default_check_phys_apicid_present,
649 .phys_pkg_id = uv_phys_pkg_id,
651 .get_apic_id = x2apic_get_apic_id,
652 .set_apic_id = set_apic_id,
654 .calc_dest_apicid = apic_uv_calc_apicid,
656 .send_IPI = uv_send_IPI_one,
657 .send_IPI_mask = uv_send_IPI_mask,
658 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
659 .send_IPI_allbutself = uv_send_IPI_allbutself,
660 .send_IPI_all = uv_send_IPI_all,
661 .send_IPI_self = uv_send_IPI_self,
663 .wakeup_secondary_cpu = uv_wakeup_secondary,
664 .inquire_remote_apic = NULL,
666 .read = native_apic_msr_read,
667 .write = native_apic_msr_write,
668 .eoi_write = native_apic_msr_eoi_write,
669 .icr_read = native_x2apic_icr_read,
670 .icr_write = native_x2apic_icr_write,
671 .wait_icr_idle = native_x2apic_wait_icr_idle,
672 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
675 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
676 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
678 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
680 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
681 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
682 unsigned long m_redirect;
683 unsigned long m_overlay;
686 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
689 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
690 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
693 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
694 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
697 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
698 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
701 alias.v = uv_read_local_mmr(m_overlay);
702 if (alias.s.enable && alias.s.base == 0) {
703 *size = (1UL << alias.s.m_alias);
704 redirect.v = uv_read_local_mmr(m_redirect);
705 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
712 enum map_type {map_wb, map_uc};
714 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
716 unsigned long bytes, paddr;
718 paddr = base << pshift;
719 bytes = (1UL << bshift) * (max_pnode + 1);
721 pr_info("UV: Map %s_HI base address NULL\n", id);
724 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
725 if (map_type == map_uc)
726 init_extra_mapping_uc(paddr, bytes);
728 init_extra_mapping_wb(paddr, bytes);
731 static __init void map_gru_high(int max_pnode)
733 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
734 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
735 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
738 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
740 pr_info("UV: GRU disabled\n");
744 base = (gru.v & mask) >> shift;
745 map_high("GRU", base, shift, shift, max_pnode, map_wb);
746 gru_start_paddr = ((u64)base << shift);
747 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
750 static __init void map_mmr_high(int max_pnode)
752 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
753 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
755 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
757 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
759 pr_info("UV: MMR disabled\n");
762 /* UV3/4 have identical MMIOH overlay configs, UV4A is slightly different */
763 static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
765 unsigned long overlay;
768 unsigned long nasid_mask;
769 unsigned long m_overlay;
770 int i, n, shift, m_io, max_io;
771 int nasid, lnasid, fi, li;
776 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
777 overlay = uv_read_local_mmr(m_overlay);
778 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
779 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
780 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
781 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
782 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
783 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
784 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
787 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
788 overlay = uv_read_local_mmr(m_overlay);
789 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
790 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
791 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
792 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
793 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
794 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
795 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
797 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
798 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
799 pr_info("UV: %s disabled\n", id);
803 /* Convert to NASID: */
806 max_io = lnasid = fi = li = -1;
808 for (i = 0; i < n; i++) {
809 unsigned long m_redirect = mmr + i * 8;
810 unsigned long redirect = uv_read_local_mmr(m_redirect);
812 nasid = redirect & nasid_mask;
814 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
815 id, redirect, m_redirect, nasid);
818 if (nasid < min_pnode || max_pnode < nasid)
821 if (nasid == lnasid) {
823 /* Last entry check: */
828 /* Check if we have a cached (or last) redirect to print: */
829 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
830 unsigned long addr1, addr2;
840 addr1 = (base << shift) + f * (1ULL << m_io);
841 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
842 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
850 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
853 map_high(id, base, shift, m_io, max_io, map_uc);
856 static __init void map_mmioh_high(int min_pnode, int max_pnode)
858 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
859 unsigned long mmr, base;
860 int shift, enable, m_io, n_io;
862 if (is_uv3_hub() || is_uv4_hub()) {
863 /* Map both MMIOH regions: */
864 map_mmioh_high_uv34(0, min_pnode, max_pnode);
865 map_mmioh_high_uv34(1, min_pnode, max_pnode);
870 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
871 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
872 mmioh.v = uv_read_local_mmr(mmr);
873 enable = !!mmioh.s2.enable;
874 base = mmioh.s2.base;
875 m_io = mmioh.s2.m_io;
876 n_io = mmioh.s2.n_io;
879 max_pnode &= (1 << n_io) - 1;
880 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
881 base, shift, m_io, n_io, max_pnode);
882 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
884 pr_info("UV: MMIOH disabled\n");
889 static __init void map_low_mmrs(void)
891 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
892 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
895 static __init void uv_rtc_init(void)
900 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
902 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
903 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
905 /* BIOS gives wrong value for clock frequency, so guess: */
906 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
908 sn_rtc_cycles_per_second = ticks_per_sec;
913 * percpu heartbeat timer
915 static void uv_heartbeat(struct timer_list *timer)
917 unsigned char bits = uv_scir_info->state;
919 /* Flip heartbeat bit: */
920 bits ^= SCIR_CPU_HEARTBEAT;
922 /* Is this CPU idle? */
923 if (idle_cpu(raw_smp_processor_id()))
924 bits &= ~SCIR_CPU_ACTIVITY;
926 bits |= SCIR_CPU_ACTIVITY;
928 /* Update system controller interface reg: */
929 uv_set_scir_bits(bits);
931 /* Enable next timer period: */
932 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
935 static int uv_heartbeat_enable(unsigned int cpu)
937 while (!uv_cpu_scir_info(cpu)->enabled) {
938 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
940 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
941 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
942 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
943 add_timer_on(timer, cpu);
944 uv_cpu_scir_info(cpu)->enabled = 1;
946 /* Also ensure that boot CPU is enabled: */
952 #ifdef CONFIG_HOTPLUG_CPU
953 static int uv_heartbeat_disable(unsigned int cpu)
955 if (uv_cpu_scir_info(cpu)->enabled) {
956 uv_cpu_scir_info(cpu)->enabled = 0;
957 del_timer(&uv_cpu_scir_info(cpu)->timer);
959 uv_set_cpu_scir_bits(cpu, 0xff);
963 static __init void uv_scir_register_cpu_notifier(void)
965 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
966 uv_heartbeat_enable, uv_heartbeat_disable);
969 #else /* !CONFIG_HOTPLUG_CPU */
971 static __init void uv_scir_register_cpu_notifier(void)
975 static __init int uv_init_heartbeat(void)
979 if (is_uv_system()) {
980 for_each_online_cpu(cpu)
981 uv_heartbeat_enable(cpu);
987 late_initcall(uv_init_heartbeat);
989 #endif /* !CONFIG_HOTPLUG_CPU */
991 /* Direct Legacy VGA I/O traffic to designated IOH */
992 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
996 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
999 if ((command_bits & PCI_COMMAND_IO) == 0)
1002 domain = pci_domain_nr(pdev->bus);
1003 bus = pdev->bus->number;
1005 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1011 * Called on each CPU to initialize the per_cpu UV data area.
1012 * FIXME: hotplug not supported yet
1014 void uv_cpu_init(void)
1016 /* CPU 0 initialization will be done via uv_system_init. */
1017 if (smp_processor_id() == 0)
1020 uv_hub_info->nr_online_cpus++;
1024 unsigned char m_val;
1025 unsigned char n_val;
1026 unsigned char m_shift;
1027 unsigned char n_lshift;
1030 static void get_mn(struct mn *mnp)
1032 union uvh_rh_gam_config_mmr_u m_n_config;
1033 union uv3h_gr0_gam_gr_config_u m_gr_config;
1035 /* Make sure the whole structure is well initialized: */
1036 memset(mnp, 0, sizeof(*mnp));
1038 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1039 mnp->n_val = m_n_config.s.n_skt;
1044 } else if (is_uv3_hub()) {
1045 mnp->m_val = m_n_config.s3.m_skt;
1046 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1047 mnp->n_lshift = m_gr_config.s3.m_skt;
1048 } else if (is_uv2_hub()) {
1049 mnp->m_val = m_n_config.s2.m_skt;
1050 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1052 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1055 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1057 union uvh_node_id_u node_id;
1061 hi->gpa_mask = mn.m_val ?
1062 (1UL << (mn.m_val + mn.n_val)) - 1 :
1063 (1UL << uv_cpuid.gpa_shift) - 1;
1065 hi->m_val = mn.m_val;
1066 hi->n_val = mn.n_val;
1067 hi->m_shift = mn.m_shift;
1068 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1069 hi->hub_revision = uv_hub_info->hub_revision;
1070 hi->pnode_mask = uv_cpuid.pnode_mask;
1071 hi->min_pnode = _min_pnode;
1072 hi->min_socket = _min_socket;
1073 hi->pnode_to_socket = _pnode_to_socket;
1074 hi->socket_to_node = _socket_to_node;
1075 hi->socket_to_pnode = _socket_to_pnode;
1076 hi->gr_table_len = _gr_table_len;
1077 hi->gr_table = _gr_table;
1079 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1080 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1081 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1083 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1086 hi->global_mmr_base = uv_gp_table->mmr_base;
1087 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1088 hi->global_gru_base = uv_gp_table->gru_base;
1089 hi->global_gru_shift = uv_gp_table->gru_shift;
1090 hi->gpa_shift = uv_gp_table->gpa_shift;
1091 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1093 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1094 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1097 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1099 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1101 /* Show system specific info: */
1102 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1103 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1104 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1105 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1108 static void __init decode_gam_params(unsigned long ptr)
1110 uv_gp_table = (struct uv_gam_parameters *)ptr;
1112 pr_info("UV: GAM Params...\n");
1113 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1114 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1115 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1116 uv_gp_table->gpa_shift);
1119 static void __init decode_gam_rng_tbl(unsigned long ptr)
1121 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1122 unsigned long lgre = 0;
1124 int sock_min = 999999, pnode_min = 99999;
1125 int sock_max = -1, pnode_max = -1;
1128 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1129 unsigned long size = ((unsigned long)(gre->limit - lgre)
1130 << UV_GAM_RANGE_SHFT);
1132 char suffix[] = " KMGTPE";
1135 while (size > 9999 && order < sizeof(suffix)) {
1140 /* adjust max block size to current range start */
1141 if (gre->type == 1 || gre->type == 2)
1142 if (adj_blksize(lgre))
1146 pr_info("UV: GAM Range Table...\n");
1147 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1149 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1151 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1152 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1153 flag, size, suffix[order],
1154 gre->type, gre->nasid, gre->sockid, gre->pnode);
1156 /* update to next range start */
1158 if (sock_min > gre->sockid)
1159 sock_min = gre->sockid;
1160 if (sock_max < gre->sockid)
1161 sock_max = gre->sockid;
1162 if (pnode_min > gre->pnode)
1163 pnode_min = gre->pnode;
1164 if (pnode_max < gre->pnode)
1165 pnode_max = gre->pnode;
1167 _min_socket = sock_min;
1168 _max_socket = sock_max;
1169 _min_pnode = pnode_min;
1170 _max_pnode = pnode_max;
1171 _gr_table_len = index;
1173 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1176 static int __init decode_uv_systab(void)
1178 struct uv_systab *st;
1181 /* If system is uv3 or lower, there is no extended UVsystab */
1182 if (is_uv_hubbed(0xfffffe) < uv(4) && is_uv_hubless(0xfffffe) < uv(4))
1183 return 0; /* No extended UVsystab required */
1186 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1187 int rev = st ? st->revision : 0;
1189 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1190 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1191 uv_system_type = UV_NONE;
1196 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1197 unsigned long ptr = st->entry[i].offset;
1202 ptr = ptr + (unsigned long)st;
1204 switch (st->entry[i].type) {
1205 case UV_SYSTAB_TYPE_GAM_PARAMS:
1206 decode_gam_params(ptr);
1209 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1210 decode_gam_rng_tbl(ptr);
1218 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE
1219 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1220 * .. being replaced by GAM Range Table
1222 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1226 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1227 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1230 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1232 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1234 uv_pb += hweight64(np);
1236 if (uv_possible_blades != uv_pb)
1237 uv_possible_blades = uv_pb;
1240 static void __init build_socket_tables(void)
1242 struct uv_gam_range_entry *gre = uv_gre_table;
1245 int minsock = _min_socket;
1246 int maxsock = _max_socket;
1247 int minpnode = _min_pnode;
1248 int maxpnode = _max_pnode;
1252 if (is_uv2_hub() || is_uv3_hub()) {
1253 pr_info("UV: No UVsystab socket table, ignoring\n");
1256 pr_crit("UV: Error: UVsystab address translations not available!\n");
1260 /* Build socket id -> node id, pnode */
1261 num = maxsock - minsock + 1;
1262 bytes = num * sizeof(_socket_to_node[0]);
1263 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1264 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1266 nump = maxpnode - minpnode + 1;
1267 bytes = nump * sizeof(_pnode_to_socket[0]);
1268 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1269 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1271 for (i = 0; i < num; i++)
1272 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1274 for (i = 0; i < nump; i++)
1275 _pnode_to_socket[i] = SOCK_EMPTY;
1277 /* Fill in pnode/node/addr conversion list values: */
1278 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1279 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1280 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1282 i = gre->sockid - minsock;
1284 if (_socket_to_pnode[i] != SOCK_EMPTY)
1286 _socket_to_pnode[i] = gre->pnode;
1288 i = gre->pnode - minpnode;
1289 _pnode_to_socket[i] = gre->sockid;
1291 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1292 gre->sockid, gre->type, gre->nasid,
1293 _socket_to_pnode[gre->sockid - minsock],
1294 _pnode_to_socket[gre->pnode - minpnode]);
1297 /* Set socket -> node values: */
1298 lnid = NUMA_NO_NODE;
1299 for_each_present_cpu(cpu) {
1300 int nid = cpu_to_node(cpu);
1306 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1307 sockid = apicid >> uv_cpuid.socketid_shift;
1308 _socket_to_node[sockid - minsock] = nid;
1309 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1310 sockid, apicid, nid);
1313 /* Set up physical blade to pnode translation from GAM Range Table: */
1314 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1315 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1316 BUG_ON(!_node_to_pnode);
1318 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1319 unsigned short sockid;
1321 for (sockid = minsock; sockid <= maxsock; sockid++) {
1322 if (lnid == _socket_to_node[sockid - minsock]) {
1323 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1327 if (sockid > maxsock) {
1328 pr_err("UV: socket for node %d not found!\n", lnid);
1334 * If socket id == pnode or socket id == node for all nodes,
1335 * system runs faster by removing corresponding conversion table.
1337 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1339 for (i = 0; i < num; i++)
1340 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1343 kfree(_socket_to_node);
1344 _socket_to_node = NULL;
1345 pr_info("UV: 1:1 socket_to_node table removed\n");
1348 if (minsock == minpnode) {
1349 for (i = 0; i < num; i++)
1350 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1351 _socket_to_pnode[i] != i + minpnode)
1354 kfree(_socket_to_pnode);
1355 _socket_to_pnode = NULL;
1356 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1361 /* Check which reboot to use */
1362 static void check_efi_reboot(void)
1364 /* If EFI reboot not available, use ACPI reboot */
1365 if (!efi_enabled(EFI_BOOT))
1366 reboot_type = BOOT_ACPI;
1369 /* Setup user proc fs files */
1370 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1372 seq_printf(file, "0x%x\n", uv_hubbed_system);
1376 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1378 seq_printf(file, "0x%x\n", uv_hubless_system);
1382 static int __maybe_unused proc_oemid_show(struct seq_file *file, void *data)
1384 seq_printf(file, "%s/%s\n", oem_id, oem_table_id);
1388 static __init void uv_setup_proc_files(int hubless)
1390 struct proc_dir_entry *pde;
1392 pde = proc_mkdir(UV_PROC_NODE, NULL);
1393 proc_create_single("oemid", 0, pde, proc_oemid_show);
1395 proc_create_single("hubless", 0, pde, proc_hubless_show);
1397 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1400 /* Initialize UV hubless systems */
1401 static __init int uv_system_init_hubless(void)
1405 /* Setup PCH NMI handler */
1406 uv_nmi_setup_hubless();
1408 /* Init kernel/BIOS interface */
1409 rc = uv_bios_init();
1413 /* Process UVsystab */
1414 rc = decode_uv_systab();
1418 /* Create user access node */
1420 uv_setup_proc_files(1);
1427 static void __init uv_system_init_hub(void)
1429 struct uv_hub_info_s hub_info = {0};
1430 int bytes, cpu, nodeid;
1431 unsigned short min_pnode = 9999, max_pnode = 0;
1432 char *hub = is_uv4_hub() ? "UV400" :
1433 is_uv3_hub() ? "UV300" :
1434 is_uv2_hub() ? "UV2000/3000" : NULL;
1437 pr_err("UV: Unknown/unsupported UV hub\n");
1440 pr_info("UV: Found %s hub\n", hub);
1444 /* Get uv_systab for decoding: */
1447 /* If there's an UVsystab problem then abort UV init: */
1448 if (decode_uv_systab() < 0)
1451 build_socket_tables();
1452 build_uv_gr_table();
1454 uv_init_hub_info(&hub_info);
1455 uv_possible_blades = num_possible_nodes();
1456 if (!_node_to_pnode)
1457 boot_init_possible_blades(&hub_info);
1459 /* uv_num_possible_blades() is really the hub count: */
1460 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1462 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1463 hub_info.coherency_domain_number = sn_coherency_id;
1466 bytes = sizeof(void *) * uv_num_possible_blades();
1467 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1468 BUG_ON(!__uv_hub_info_list);
1470 bytes = sizeof(struct uv_hub_info_s);
1471 for_each_node(nodeid) {
1472 struct uv_hub_info_s *new_hub;
1474 if (__uv_hub_info_list[nodeid]) {
1475 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1479 /* Allocate new per hub info list */
1480 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1482 __uv_hub_info_list[nodeid] = new_hub;
1483 new_hub = uv_hub_info_list(nodeid);
1485 *new_hub = hub_info;
1487 /* Use information from GAM table if available: */
1489 new_hub->pnode = _node_to_pnode[nodeid];
1490 else /* Or fill in during CPU loop: */
1491 new_hub->pnode = 0xffff;
1493 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1494 new_hub->memory_nid = NUMA_NO_NODE;
1495 new_hub->nr_possible_cpus = 0;
1496 new_hub->nr_online_cpus = 0;
1499 /* Initialize per CPU info: */
1500 for_each_possible_cpu(cpu) {
1501 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1503 unsigned short pnode;
1505 nodeid = cpu_to_node(cpu);
1506 numa_node_id = numa_cpu_node(cpu);
1507 pnode = uv_apicid_to_pnode(apicid);
1509 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1510 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1511 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1512 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1514 /* Init memoryless node: */
1515 if (nodeid != numa_node_id &&
1516 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1517 uv_hub_info_list(numa_node_id)->pnode = pnode;
1518 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1519 uv_cpu_hub_info(cpu)->pnode = pnode;
1521 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1524 for_each_node(nodeid) {
1525 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1527 /* Add pnode info for pre-GAM list nodes without CPUs: */
1528 if (pnode == 0xffff) {
1529 unsigned long paddr;
1531 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1532 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1533 uv_hub_info_list(nodeid)->pnode = pnode;
1535 min_pnode = min(pnode, min_pnode);
1536 max_pnode = max(pnode, max_pnode);
1537 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1539 uv_hub_info_list(nodeid)->pnode,
1540 uv_hub_info_list(nodeid)->nr_possible_cpus);
1543 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1544 map_gru_high(max_pnode);
1545 map_mmr_high(max_pnode);
1546 map_mmioh_high(min_pnode, max_pnode);
1550 uv_scir_register_cpu_notifier();
1551 uv_setup_proc_files(0);
1553 /* Register Legacy VGA I/O redirection handler: */
1554 pci_register_set_vga_state(uv_set_vga_state);
1560 * There is a different code path needed to initialize a UV system that does
1561 * not have a "UV HUB" (referred to as "hubless").
1563 void __init uv_system_init(void)
1565 if (likely(!is_uv_system() && !is_uv_hubless(1)))
1569 uv_system_init_hub();
1571 uv_system_init_hubless();
1574 apic_driver(apic_x2apic_uv_x);