2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/crash_dump.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/cpumask.h>
14 #include <linux/proc_fs.h>
15 #include <linux/memory.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/acpi.h>
19 #include <linux/efi.h>
21 #include <asm/e820/api.h>
22 #include <asm/uv/uv_mmrs.h>
23 #include <asm/uv/uv_hub.h>
24 #include <asm/uv/bios.h>
25 #include <asm/uv/uv.h>
28 static enum uv_system_type uv_system_type;
29 static int uv_hubbed_system;
30 static int uv_hubless_system;
31 static u64 gru_start_paddr, gru_end_paddr;
32 static union uvh_apicid uvh_apicid;
33 static int uv_node_id;
35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
36 static u8 uv_archtype[UV_AT_SIZE + 1];
37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
40 /* Information derived from CPUID and some UV MMRs */
42 unsigned int apicid_shift;
43 unsigned int apicid_mask;
44 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */
45 unsigned int pnode_mask;
46 unsigned int nasid_shift;
47 unsigned int gpa_shift;
48 unsigned int gnode_shift;
53 static int uv_min_hub_revision_id;
55 static struct apic apic_x2apic_uv_x;
56 static struct uv_hub_info_s uv_hub_info_node0;
58 /* Set this to use hardware error handler instead of kernel panic: */
59 static int disable_uv_undefined_panic = 1;
61 unsigned long uv_undefined(char *str)
63 if (likely(!disable_uv_undefined_panic))
64 panic("UV: error: undefined MMR: %s\n", str);
66 pr_crit("UV: error: undefined MMR: %s\n", str);
68 /* Cause a machine fault: */
71 EXPORT_SYMBOL(uv_undefined);
73 static unsigned long __init uv_early_read_mmr(unsigned long addr)
75 unsigned long val, *mmr;
77 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
79 early_iounmap(mmr, sizeof(*mmr));
84 static inline bool is_GRU_range(u64 start, u64 end)
89 return start >= gru_start_paddr && end <= gru_end_paddr;
92 static bool uv_is_untracked_pat_range(u64 start, u64 end)
94 return is_ISA_range(start, end) || is_GRU_range(start, end);
97 static void __init early_get_pnodeid(void)
102 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
103 union uvh_rh10_gam_addr_map_config_u m_n_config;
105 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
106 uv_cpuid.n_skt = m_n_config.s.n_skt;
107 uv_cpuid.nasid_shift = 0;
108 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
109 union uvh_rh_gam_addr_map_config_u m_n_config;
111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
112 uv_cpuid.n_skt = m_n_config.s.n_skt;
114 uv_cpuid.m_skt = m_n_config.s3.m_skt;
116 uv_cpuid.m_skt = m_n_config.s2.m_skt;
117 uv_cpuid.nasid_shift = 1;
119 unsigned long GAM_ADDR_MAP_CONFIG = 0;
121 WARN(GAM_ADDR_MAP_CONFIG == 0,
122 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
124 uv_cpuid.nasid_shift = 0;
128 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
130 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
131 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
132 uv_cpuid.gpa_shift = 46; /* Default unless changed */
134 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
135 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
139 static int __init early_set_hub_type(void)
141 union uvh_node_id_u node_id;
144 * The NODE_ID MMR is always at offset 0.
145 * Contains the chip part # + revision.
146 * Node_id field started with 15 bits,
147 * ... now 7 but upper 8 are masked to 0.
148 * All blades/nodes have the same part # and hub revision.
150 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
151 uv_node_id = node_id.sx.node_id;
153 switch (node_id.s.part_number) {
155 case UV5_HUB_PART_NUMBER:
156 uv_min_hub_revision_id = node_id.s.revision
157 + UV5_HUB_REVISION_BASE;
158 uv_hub_type_set(UV5);
161 /* UV4/4A only have a revision difference */
162 case UV4_HUB_PART_NUMBER:
163 uv_min_hub_revision_id = node_id.s.revision
164 + UV4_HUB_REVISION_BASE - 1;
165 uv_hub_type_set(UV4);
166 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
167 uv_hub_type_set(UV4|UV4A);
170 case UV3_HUB_PART_NUMBER:
171 case UV3_HUB_PART_NUMBER_X:
172 uv_min_hub_revision_id = node_id.s.revision
173 + UV3_HUB_REVISION_BASE;
174 uv_hub_type_set(UV3);
177 case UV2_HUB_PART_NUMBER:
178 case UV2_HUB_PART_NUMBER_X:
179 uv_min_hub_revision_id = node_id.s.revision
180 + UV2_HUB_REVISION_BASE - 1;
181 uv_hub_type_set(UV2);
188 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
189 node_id.s.part_number, node_id.s.revision,
190 uv_min_hub_revision_id, is_uv(~0));
195 static void __init uv_tsc_check_sync(void)
202 /* Different returns from different UV BIOS versions */
203 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
205 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
206 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
208 /* Check if TSC is valid for all sockets */
209 switch (sync_state) {
210 case UVH_TSC_SYNC_VALID:
212 mark_tsc_async_resets("UV BIOS");
215 /* If BIOS state unknown, don't do anything */
216 case UVH_TSC_SYNC_UNKNOWN:
220 /* Otherwise, BIOS indicates problem with TSC */
223 mark_tsc_unstable("UV BIOS");
226 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
229 /* Selector for (4|4A|5) structs */
230 #define uvxy_field(sname, field, undef) ( \
231 is_uv(UV4A) ? sname.s4a.field : \
232 is_uv(UV4) ? sname.s4.field : \
233 is_uv(UV3) ? sname.s3.field : \
236 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
238 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */
239 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */
242 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
243 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
245 static void set_x2apic_bits(void)
247 unsigned int eax, ebx, ecx, edx, sub_index;
248 unsigned int sid_shift;
250 cpuid(0, &eax, &ebx, &ecx, &edx);
252 pr_info("UV: CPU does not have CPUID.11\n");
256 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
257 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
258 pr_info("UV: CPUID.11 not implemented\n");
262 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
265 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
266 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
267 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
271 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
273 uv_cpuid.apicid_shift = 0;
274 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
275 uv_cpuid.socketid_shift = sid_shift;
278 static void __init early_get_apic_socketid_shift(void)
280 if (is_uv2_hub() || is_uv3_hub())
281 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
285 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
286 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
289 static void __init uv_stringify(int len, char *to, char *from)
291 /* Relies on 'to' being NULL chars so result will be NULL terminated */
292 strncpy(to, from, len-1);
294 /* Trim trailing spaces */
298 /* Find UV arch type entry in UVsystab */
299 static unsigned long __init early_find_archtype(struct uv_systab *st)
303 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
304 unsigned long ptr = st->entry[i].offset;
308 ptr += (unsigned long)st;
309 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
315 /* Validate UV arch type field in UVsystab */
316 static int __init decode_arch_type(unsigned long ptr)
318 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
319 int n = strlen(uv_ate->archtype);
321 if (n > 0 && n < sizeof(uv_ate->archtype)) {
322 pr_info("UV: UVarchtype received from BIOS\n");
323 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
329 /* Determine if UV arch type entry might exist in UVsystab */
330 static int __init early_get_arch_type(void)
332 unsigned long uvst_physaddr, uvst_size, ptr;
333 struct uv_systab *st;
337 uvst_physaddr = get_uv_systab_phys(0);
341 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
343 pr_err("UV: Cannot access UVsystab, remap failed\n");
348 if (rev < UV_SYSTAB_VERSION_UV5) {
349 early_memunmap(st, sizeof(struct uv_systab));
353 uvst_size = st->size;
354 early_memunmap(st, sizeof(struct uv_systab));
355 st = early_memremap_ro(uvst_physaddr, uvst_size);
357 pr_err("UV: Cannot access UVarchtype, remap failed\n");
361 ptr = early_find_archtype(st);
363 early_memunmap(st, uvst_size);
367 ret = decode_arch_type(ptr);
368 early_memunmap(st, uvst_size);
372 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
374 /* Save OEM_ID passed from ACPI MADT */
375 uv_stringify(sizeof(oem_id), oem_id, _oem_id);
377 /* Check if BIOS sent us a UVarchtype */
378 if (!early_get_arch_type())
380 /* If not use OEM ID for UVarchtype */
381 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
383 /* Check if not hubbed */
384 if (strncmp(uv_archtype, "SGI", 3) != 0) {
386 /* (Not hubbed), check if not hubless */
387 if (strncmp(uv_archtype, "NSGI", 4) != 0)
389 /* (Not hubless), not a UV */
392 /* Is UV hubless system */
393 uv_hubless_system = 0x01;
396 if (strncmp(uv_archtype, "NSGI5", 5) == 0)
397 uv_hubless_system |= 0x20;
399 /* UV4 Hubless: CH */
400 else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
401 uv_hubless_system |= 0x10;
403 /* UV3 Hubless: UV300/MC990X w/o hub */
405 uv_hubless_system |= 0x8;
408 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
410 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
411 oem_id, oem_table_id, uv_system_type, uv_hubless_system);
416 pr_err("UV: NUMA is off, disabling UV support\n");
420 /* Set hubbed type if true */
421 uv_hub_info->hub_revision =
422 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
423 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
424 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
425 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
427 switch (uv_hub_info->hub_revision) {
428 case UV5_HUB_REVISION_BASE:
429 uv_hubbed_system = 0x21;
430 uv_hub_type_set(UV5);
433 case UV4_HUB_REVISION_BASE:
434 uv_hubbed_system = 0x11;
435 uv_hub_type_set(UV4);
438 case UV3_HUB_REVISION_BASE:
439 uv_hubbed_system = 0x9;
440 uv_hub_type_set(UV3);
443 case UV2_HUB_REVISION_BASE:
444 uv_hubbed_system = 0x5;
445 uv_hub_type_set(UV2);
452 /* Get UV hub chip part number & revision */
453 early_set_hub_type();
455 /* Other UV setup functions */
457 early_get_apic_socketid_shift();
458 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
459 x86_platform.nmi_init = uv_nmi_init;
465 /* Called early to probe for the correct APIC driver */
466 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
468 /* Set up early hub info fields for Node 0 */
469 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
471 /* If not UV, return. */
472 if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
475 /* Save and Decode OEM Table ID */
476 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
478 /* This is the most common hardware variant, x2apic mode */
479 if (!strcmp(oem_table_id, "UVX"))
480 uv_system_type = UV_X2APIC;
482 /* Only used for very small systems, usually 1 chassis, legacy mode */
483 else if (!strcmp(oem_table_id, "UVL"))
484 uv_system_type = UV_LEGACY_APIC;
489 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
490 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
491 uv_min_hub_revision_id);
496 pr_err("UV: UVarchtype:%s not supported\n", uv_archtype);
500 enum uv_system_type get_uv_system_type(void)
502 return uv_system_type;
505 int uv_get_hubless_system(void)
507 return uv_hubless_system;
509 EXPORT_SYMBOL_GPL(uv_get_hubless_system);
511 ssize_t uv_get_archtype(char *buf, int len)
513 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id);
515 EXPORT_SYMBOL_GPL(uv_get_archtype);
517 int is_uv_system(void)
519 return uv_system_type != UV_NONE;
521 EXPORT_SYMBOL_GPL(is_uv_system);
523 int is_uv_hubbed(int uvtype)
525 return (uv_hubbed_system & uvtype);
527 EXPORT_SYMBOL_GPL(is_uv_hubbed);
529 static int is_uv_hubless(int uvtype)
531 return (uv_hubless_system & uvtype);
534 void **__uv_hub_info_list;
535 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
537 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
538 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
540 short uv_possible_blades;
541 EXPORT_SYMBOL_GPL(uv_possible_blades);
543 unsigned long sn_rtc_cycles_per_second;
544 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
546 /* The following values are used for the per node hub info struct */
547 static __initdata unsigned short *_node_to_pnode;
548 static __initdata unsigned short _min_socket, _max_socket;
549 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
550 static __initdata struct uv_gam_range_entry *uv_gre_table;
551 static __initdata struct uv_gam_parameters *uv_gp_table;
552 static __initdata unsigned short *_socket_to_node;
553 static __initdata unsigned short *_socket_to_pnode;
554 static __initdata unsigned short *_pnode_to_socket;
556 static __initdata struct uv_gam_range_s *_gr_table;
558 #define SOCK_EMPTY ((unsigned short)~0)
560 /* Default UV memory block size is 2GB */
561 static unsigned long mem_block_size __initdata = (2UL << 30);
563 /* Kernel parameter to specify UV mem block size */
564 static int __init parse_mem_block_size(char *ptr)
566 unsigned long size = memparse(ptr, NULL);
568 /* Size will be rounded down by set_block_size() below */
569 mem_block_size = size;
572 early_param("uv_memblksize", parse_mem_block_size);
574 static __init int adj_blksize(u32 lgre)
576 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
579 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
580 if (IS_ALIGNED(base, size))
583 if (size >= mem_block_size)
586 mem_block_size = size;
590 static __init void set_block_size(void)
592 unsigned int order = ffs(mem_block_size);
595 /* adjust for ffs return of 1..64 */
596 set_memory_block_size_order(order - 1);
597 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
599 /* bad or zero value, default to 1UL << 31 (2GB) */
600 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
601 set_memory_block_size_order(31);
605 /* Build GAM range lookup table: */
606 static __init void build_uv_gr_table(void)
608 struct uv_gam_range_entry *gre = uv_gre_table;
609 struct uv_gam_range_s *grt;
610 unsigned long last_limit = 0, ram_limit = 0;
611 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
616 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
617 grt = kzalloc(bytes, GFP_KERNEL);
621 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
622 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
624 /* Mark hole between RAM/non-RAM: */
625 ram_limit = last_limit;
626 last_limit = gre->limit;
630 last_limit = gre->limit;
631 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
634 if (_max_socket < gre->sockid) {
635 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
638 sid = gre->sockid - _min_socket;
641 grt = &_gr_table[indx];
643 grt->nasid = gre->nasid;
644 grt->limit = last_limit = gre->limit;
650 if (lsid == sid && !ram_limit) {
651 /* .. if contiguous: */
652 if (grt->limit == last_limit) {
653 grt->limit = last_limit = gre->limit;
657 /* Non-contiguous RAM range: */
661 grt->nasid = gre->nasid;
662 grt->limit = last_limit = gre->limit;
665 /* Non-contiguous/non-RAM: */
667 /* base is this entry */
668 grt->base = grt - _gr_table;
669 grt->nasid = gre->nasid;
670 grt->limit = last_limit = gre->limit;
674 /* Shorten table if possible */
677 if (i < _gr_table_len) {
680 bytes = i * sizeof(struct uv_gam_range_s);
681 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
688 /* Display resultant GAM range table: */
689 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
690 unsigned long start, end;
693 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
694 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
696 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
700 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
705 pnode = uv_apicid_to_pnode(phys_apicid);
707 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
708 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
709 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
712 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
714 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
715 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
716 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
719 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
724 static void uv_send_IPI_one(int cpu, int vector)
726 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
727 int pnode = uv_apicid_to_pnode(apicid);
728 unsigned long dmode, val;
730 if (vector == NMI_VECTOR)
735 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
736 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
737 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
738 (vector << UVH_IPI_INT_VECTOR_SHFT);
740 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
743 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
747 for_each_cpu(cpu, mask)
748 uv_send_IPI_one(cpu, vector);
751 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
753 unsigned int this_cpu = smp_processor_id();
756 for_each_cpu(cpu, mask) {
758 uv_send_IPI_one(cpu, vector);
762 static void uv_send_IPI_allbutself(int vector)
764 unsigned int this_cpu = smp_processor_id();
767 for_each_online_cpu(cpu) {
769 uv_send_IPI_one(cpu, vector);
773 static void uv_send_IPI_all(int vector)
775 uv_send_IPI_mask(cpu_online_mask, vector);
778 static int uv_apic_id_valid(u32 apicid)
783 static int uv_apic_id_registered(void)
788 static void uv_init_apic_ldr(void)
792 static u32 apic_uv_calc_apicid(unsigned int cpu)
794 return apic_default_calc_apicid(cpu);
797 static unsigned int x2apic_get_apic_id(unsigned long id)
802 static u32 set_apic_id(unsigned int id)
807 static unsigned int uv_read_apic_id(void)
809 return x2apic_get_apic_id(apic_read(APIC_ID));
812 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
814 return uv_read_apic_id() >> index_msb;
817 static void uv_send_IPI_self(int vector)
819 apic_write(APIC_SELF_IPI, vector);
822 static int uv_probe(void)
824 return apic == &apic_x2apic_uv_x;
827 static struct apic apic_x2apic_uv_x __ro_after_init = {
829 .name = "UV large system",
831 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
832 .apic_id_valid = uv_apic_id_valid,
833 .apic_id_registered = uv_apic_id_registered,
835 .irq_delivery_mode = dest_Fixed,
836 .irq_dest_mode = 0, /* Physical */
839 .dest_logical = APIC_DEST_LOGICAL,
840 .check_apicid_used = NULL,
842 .init_apic_ldr = uv_init_apic_ldr,
844 .ioapic_phys_id_map = NULL,
845 .setup_apic_routing = NULL,
846 .cpu_present_to_apicid = default_cpu_present_to_apicid,
847 .apicid_to_cpu_present = NULL,
848 .check_phys_apicid_present = default_check_phys_apicid_present,
849 .phys_pkg_id = uv_phys_pkg_id,
851 .get_apic_id = x2apic_get_apic_id,
852 .set_apic_id = set_apic_id,
854 .calc_dest_apicid = apic_uv_calc_apicid,
856 .send_IPI = uv_send_IPI_one,
857 .send_IPI_mask = uv_send_IPI_mask,
858 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
859 .send_IPI_allbutself = uv_send_IPI_allbutself,
860 .send_IPI_all = uv_send_IPI_all,
861 .send_IPI_self = uv_send_IPI_self,
863 .wakeup_secondary_cpu = uv_wakeup_secondary,
864 .inquire_remote_apic = NULL,
866 .read = native_apic_msr_read,
867 .write = native_apic_msr_write,
868 .eoi_write = native_apic_msr_eoi_write,
869 .icr_read = native_x2apic_icr_read,
870 .icr_write = native_x2apic_icr_write,
871 .wait_icr_idle = native_x2apic_wait_icr_idle,
872 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
875 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
876 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
878 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
880 union uvh_rh_gam_alias_2_overlay_config_u alias;
881 union uvh_rh_gam_alias_2_redirect_config_u redirect;
882 unsigned long m_redirect;
883 unsigned long m_overlay;
886 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
889 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
890 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
893 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
894 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
897 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
898 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
901 alias.v = uv_read_local_mmr(m_overlay);
902 if (alias.s.enable && alias.s.base == 0) {
903 *size = (1UL << alias.s.m_alias);
904 redirect.v = uv_read_local_mmr(m_redirect);
905 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
912 enum map_type {map_wb, map_uc};
913 static const char * const mt[] = { "WB", "UC" };
915 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
917 unsigned long bytes, paddr;
919 paddr = base << pshift;
920 bytes = (1UL << bshift) * (max_pnode + 1);
922 pr_info("UV: Map %s_HI base address NULL\n", id);
925 if (map_type == map_uc)
926 init_extra_mapping_uc(paddr, bytes);
928 init_extra_mapping_wb(paddr, bytes);
930 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
931 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
934 static __init void map_gru_high(int max_pnode)
936 union uvh_rh_gam_gru_overlay_config_u gru;
937 unsigned long mask, base;
940 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
941 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
942 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
943 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
944 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
945 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
946 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
947 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
949 pr_err("UV: GRU unavailable (no MMR)\n");
954 pr_info("UV: GRU disabled (by BIOS)\n");
958 base = (gru.v & mask) >> shift;
959 map_high("GRU", base, shift, shift, max_pnode, map_wb);
960 gru_start_paddr = ((u64)base << shift);
961 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
964 static __init void map_mmr_high(int max_pnode)
970 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
971 union uvh_rh10_gam_mmr_overlay_config_u mmr;
973 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
974 enable = mmr.s.enable;
976 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
977 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
978 union uvh_rh_gam_mmr_overlay_config_u mmr;
980 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
981 enable = mmr.s.enable;
983 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
985 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
991 map_high("MMR", base, shift, shift, max_pnode, map_uc);
993 pr_info("UV: MMR disabled\n");
996 /* Arch specific ENUM cases */
999 UVY_MMIOH0, UVY_MMIOH1,
1000 UVX_MMIOH0, UVX_MMIOH1,
1003 /* Calculate and Map MMIOH Regions */
1004 static void __init calc_mmioh_map(enum mmioh_arch index,
1005 int min_pnode, int max_pnode,
1006 int shift, unsigned long base, int m_io, int n_io)
1008 unsigned long mmr, nasid_mask;
1009 int nasid, min_nasid, max_nasid, lnasid, mapped;
1010 int i, fi, li, n, max_io;
1013 /* One (UV2) mapping */
1014 if (index == UV2_MMIOH) {
1015 strncpy(id, "MMIOH", sizeof(id));
1021 /* small and large MMIOH mappings */
1024 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
1025 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1026 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1027 min_nasid = min_pnode;
1028 max_nasid = max_pnode;
1032 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
1033 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1034 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1035 min_nasid = min_pnode;
1036 max_nasid = max_pnode;
1040 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1041 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1042 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1043 min_nasid = min_pnode * 2;
1044 max_nasid = max_pnode * 2;
1048 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1049 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1050 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1051 min_nasid = min_pnode * 2;
1052 max_nasid = max_pnode * 2;
1056 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1060 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1061 snprintf(id, sizeof(id), "MMIOH%d", index%2);
1063 max_io = lnasid = fi = li = -1;
1064 for (i = 0; i < n; i++) {
1065 unsigned long m_redirect = mmr + i * 8;
1066 unsigned long redirect = uv_read_local_mmr(m_redirect);
1068 nasid = redirect & nasid_mask;
1070 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1071 id, redirect, m_redirect, nasid);
1073 /* Invalid NASID check */
1074 if (nasid < min_nasid || max_nasid < nasid) {
1075 pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
1076 __func__, index, min_nasid, max_nasid);
1080 if (nasid == lnasid) {
1082 /* Last entry check: */
1087 /* Check if we have a cached (or last) redirect to print: */
1088 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
1089 unsigned long addr1, addr2;
1099 addr1 = (base << shift) + f * (1ULL << m_io);
1100 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1101 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1102 id, fi, li, lnasid, addr1, addr2);
1111 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1112 id, base, shift, m_io, max_io, max_pnode);
1114 if (max_io >= 0 && !mapped)
1115 map_high(id, base, shift, m_io, max_io, map_uc);
1118 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1121 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1122 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1123 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1125 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1126 if (unlikely(mmioh0.s.enable == 0))
1127 pr_info("UV: MMIOH0 disabled\n");
1129 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1130 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1131 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1133 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1134 if (unlikely(mmioh1.s.enable == 0))
1135 pr_info("UV: MMIOH1 disabled\n");
1137 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1138 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1139 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1143 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1144 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1145 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1147 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1148 if (unlikely(mmioh0.s.enable == 0))
1149 pr_info("UV: MMIOH0 disabled\n");
1151 unsigned long base = uvxy_field(mmioh0, base, 0);
1152 int m_io = uvxy_field(mmioh0, m_io, 0);
1153 int n_io = uvxy_field(mmioh0, n_io, 0);
1155 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1156 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1160 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1161 if (unlikely(mmioh1.s.enable == 0))
1162 pr_info("UV: MMIOH1 disabled\n");
1164 unsigned long base = uvxy_field(mmioh1, base, 0);
1165 int m_io = uvxy_field(mmioh1, m_io, 0);
1166 int n_io = uvxy_field(mmioh1, n_io, 0);
1168 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1169 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1176 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1177 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1179 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1180 if (unlikely(mmioh.s2.enable == 0))
1181 pr_info("UV: MMIOH disabled\n");
1183 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1184 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1185 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1190 static __init void map_low_mmrs(void)
1192 if (UV_GLOBAL_MMR32_BASE)
1193 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1195 if (UV_LOCAL_MMR_BASE)
1196 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1199 static __init void uv_rtc_init(void)
1204 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1206 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1207 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1209 /* BIOS gives wrong value for clock frequency, so guess: */
1210 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1212 sn_rtc_cycles_per_second = ticks_per_sec;
1216 /* Direct Legacy VGA I/O traffic to designated IOH */
1217 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1219 int domain, bus, rc;
1221 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1224 if ((command_bits & PCI_COMMAND_IO) == 0)
1227 domain = pci_domain_nr(pdev->bus);
1228 bus = pdev->bus->number;
1230 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1236 * Called on each CPU to initialize the per_cpu UV data area.
1237 * FIXME: hotplug not supported yet
1239 void uv_cpu_init(void)
1241 /* CPU 0 initialization will be done via uv_system_init. */
1242 if (smp_processor_id() == 0)
1245 uv_hub_info->nr_online_cpus++;
1249 unsigned char m_val;
1250 unsigned char n_val;
1251 unsigned char m_shift;
1252 unsigned char n_lshift;
1255 /* Initialize caller's MN struct and fill in values */
1256 static void get_mn(struct mn *mnp)
1258 memset(mnp, 0, sizeof(*mnp));
1259 mnp->n_val = uv_cpuid.n_skt;
1260 if (is_uv(UV4|UVY)) {
1263 } else if (is_uv3_hub()) {
1264 union uvyh_gr0_gam_gr_config_u m_gr_config;
1266 mnp->m_val = uv_cpuid.m_skt;
1267 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1268 mnp->n_lshift = m_gr_config.s3.m_skt;
1269 } else if (is_uv2_hub()) {
1270 mnp->m_val = uv_cpuid.m_skt;
1271 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1273 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1276 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1281 hi->gpa_mask = mn.m_val ?
1282 (1UL << (mn.m_val + mn.n_val)) - 1 :
1283 (1UL << uv_cpuid.gpa_shift) - 1;
1285 hi->m_val = mn.m_val;
1286 hi->n_val = mn.n_val;
1287 hi->m_shift = mn.m_shift;
1288 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1289 hi->hub_revision = uv_hub_info->hub_revision;
1290 hi->hub_type = uv_hub_info->hub_type;
1291 hi->pnode_mask = uv_cpuid.pnode_mask;
1292 hi->nasid_shift = uv_cpuid.nasid_shift;
1293 hi->min_pnode = _min_pnode;
1294 hi->min_socket = _min_socket;
1295 hi->pnode_to_socket = _pnode_to_socket;
1296 hi->socket_to_node = _socket_to_node;
1297 hi->socket_to_pnode = _socket_to_pnode;
1298 hi->gr_table_len = _gr_table_len;
1299 hi->gr_table = _gr_table;
1301 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1302 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1304 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1307 hi->global_mmr_base = uv_gp_table->mmr_base;
1308 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1309 hi->global_gru_base = uv_gp_table->gru_base;
1310 hi->global_gru_shift = uv_gp_table->gru_shift;
1311 hi->gpa_shift = uv_gp_table->gpa_shift;
1312 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1314 hi->global_mmr_base =
1315 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1317 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1320 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1322 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1324 /* Show system specific info: */
1325 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1326 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1327 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1328 if (hi->global_gru_base)
1329 pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1330 hi->global_gru_base, hi->global_gru_shift);
1332 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1335 static void __init decode_gam_params(unsigned long ptr)
1337 uv_gp_table = (struct uv_gam_parameters *)ptr;
1339 pr_info("UV: GAM Params...\n");
1340 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1341 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1342 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1343 uv_gp_table->gpa_shift);
1346 static void __init decode_gam_rng_tbl(unsigned long ptr)
1348 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1349 unsigned long lgre = 0;
1351 int sock_min = 999999, pnode_min = 99999;
1352 int sock_max = -1, pnode_max = -1;
1355 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1356 unsigned long size = ((unsigned long)(gre->limit - lgre)
1357 << UV_GAM_RANGE_SHFT);
1359 char suffix[] = " KMGTPE";
1362 while (size > 9999 && order < sizeof(suffix)) {
1367 /* adjust max block size to current range start */
1368 if (gre->type == 1 || gre->type == 2)
1369 if (adj_blksize(lgre))
1373 pr_info("UV: GAM Range Table...\n");
1374 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1376 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1378 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1379 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1380 flag, size, suffix[order],
1381 gre->type, gre->nasid, gre->sockid, gre->pnode);
1383 /* update to next range start */
1385 if (sock_min > gre->sockid)
1386 sock_min = gre->sockid;
1387 if (sock_max < gre->sockid)
1388 sock_max = gre->sockid;
1389 if (pnode_min > gre->pnode)
1390 pnode_min = gre->pnode;
1391 if (pnode_max < gre->pnode)
1392 pnode_max = gre->pnode;
1394 _min_socket = sock_min;
1395 _max_socket = sock_max;
1396 _min_pnode = pnode_min;
1397 _max_pnode = pnode_max;
1398 _gr_table_len = index;
1400 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1403 /* Walk through UVsystab decoding the fields */
1404 static int __init decode_uv_systab(void)
1406 struct uv_systab *st;
1409 /* Get mapped UVsystab pointer */
1412 /* If UVsystab is version 1, there is no extended UVsystab */
1413 if (st && st->revision == UV_SYSTAB_VERSION_1)
1416 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1417 int rev = st ? st->revision : 0;
1419 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1420 rev, UV_SYSTAB_VERSION_UV4_LATEST);
1421 pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1422 uv_system_type = UV_NONE;
1427 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1428 unsigned long ptr = st->entry[i].offset;
1433 /* point to payload */
1434 ptr += (unsigned long)st;
1436 switch (st->entry[i].type) {
1437 case UV_SYSTAB_TYPE_GAM_PARAMS:
1438 decode_gam_params(ptr);
1441 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1442 decode_gam_rng_tbl(ptr);
1445 case UV_SYSTAB_TYPE_ARCH_TYPE:
1446 /* already processed in early startup */
1450 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1451 __func__, st->entry[i].type);
1458 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
1459 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1464 if (UVH_NODE_PRESENT_TABLE) {
1465 pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1466 UVH_NODE_PRESENT_TABLE_DEPTH);
1467 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1468 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1469 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1470 uv_pb += hweight64(np);
1473 if (UVH_NODE_PRESENT_0) {
1474 np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1475 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1476 uv_pb += hweight64(np);
1478 if (UVH_NODE_PRESENT_1) {
1479 np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1480 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1481 uv_pb += hweight64(np);
1483 if (uv_possible_blades != uv_pb)
1484 uv_possible_blades = uv_pb;
1486 pr_info("UV: number nodes/possible blades %d\n", uv_pb);
1489 static void __init build_socket_tables(void)
1491 struct uv_gam_range_entry *gre = uv_gre_table;
1494 int minsock = _min_socket;
1495 int maxsock = _max_socket;
1496 int minpnode = _min_pnode;
1497 int maxpnode = _max_pnode;
1501 if (is_uv2_hub() || is_uv3_hub()) {
1502 pr_info("UV: No UVsystab socket table, ignoring\n");
1505 pr_err("UV: Error: UVsystab address translations not available!\n");
1509 /* Build socket id -> node id, pnode */
1510 num = maxsock - minsock + 1;
1511 bytes = num * sizeof(_socket_to_node[0]);
1512 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1513 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1515 nump = maxpnode - minpnode + 1;
1516 bytes = nump * sizeof(_pnode_to_socket[0]);
1517 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1518 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1520 for (i = 0; i < num; i++)
1521 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1523 for (i = 0; i < nump; i++)
1524 _pnode_to_socket[i] = SOCK_EMPTY;
1526 /* Fill in pnode/node/addr conversion list values: */
1527 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1528 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1529 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1531 i = gre->sockid - minsock;
1533 if (_socket_to_pnode[i] != SOCK_EMPTY)
1535 _socket_to_pnode[i] = gre->pnode;
1537 i = gre->pnode - minpnode;
1538 _pnode_to_socket[i] = gre->sockid;
1540 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1541 gre->sockid, gre->type, gre->nasid,
1542 _socket_to_pnode[gre->sockid - minsock],
1543 _pnode_to_socket[gre->pnode - minpnode]);
1546 /* Set socket -> node values: */
1547 lnid = NUMA_NO_NODE;
1548 for_each_present_cpu(cpu) {
1549 int nid = cpu_to_node(cpu);
1555 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1556 sockid = apicid >> uv_cpuid.socketid_shift;
1557 _socket_to_node[sockid - minsock] = nid;
1558 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1559 sockid, apicid, nid);
1562 /* Set up physical blade to pnode translation from GAM Range Table: */
1563 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1564 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1565 BUG_ON(!_node_to_pnode);
1567 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1568 unsigned short sockid;
1570 for (sockid = minsock; sockid <= maxsock; sockid++) {
1571 if (lnid == _socket_to_node[sockid - minsock]) {
1572 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1576 if (sockid > maxsock) {
1577 pr_err("UV: socket for node %d not found!\n", lnid);
1583 * If socket id == pnode or socket id == node for all nodes,
1584 * system runs faster by removing corresponding conversion table.
1586 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1588 for (i = 0; i < num; i++)
1589 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1592 kfree(_socket_to_node);
1593 _socket_to_node = NULL;
1594 pr_info("UV: 1:1 socket_to_node table removed\n");
1597 if (minsock == minpnode) {
1598 for (i = 0; i < num; i++)
1599 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1600 _socket_to_pnode[i] != i + minpnode)
1603 kfree(_socket_to_pnode);
1604 _socket_to_pnode = NULL;
1605 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1610 /* Check which reboot to use */
1611 static void check_efi_reboot(void)
1613 /* If EFI reboot not available, use ACPI reboot */
1614 if (!efi_enabled(EFI_BOOT))
1615 reboot_type = BOOT_ACPI;
1619 * User proc fs file handling now deprecated.
1620 * Recommend using /sys/firmware/sgi_uv/... instead.
1622 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1624 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n",
1626 seq_printf(file, "0x%x\n", uv_hubbed_system);
1630 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1632 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n",
1634 seq_printf(file, "0x%x\n", uv_hubless_system);
1638 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1640 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n",
1642 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1646 static __init void uv_setup_proc_files(int hubless)
1648 struct proc_dir_entry *pde;
1650 pde = proc_mkdir(UV_PROC_NODE, NULL);
1651 proc_create_single("archtype", 0, pde, proc_archtype_show);
1653 proc_create_single("hubless", 0, pde, proc_hubless_show);
1655 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1658 /* Initialize UV hubless systems */
1659 static __init int uv_system_init_hubless(void)
1663 /* Setup PCH NMI handler */
1664 uv_nmi_setup_hubless();
1666 /* Init kernel/BIOS interface */
1667 rc = uv_bios_init();
1671 /* Process UVsystab */
1672 rc = decode_uv_systab();
1676 /* Create user access node */
1678 uv_setup_proc_files(1);
1685 static void __init uv_system_init_hub(void)
1687 struct uv_hub_info_s hub_info = {0};
1688 int bytes, cpu, nodeid;
1689 unsigned short min_pnode = 9999, max_pnode = 0;
1690 char *hub = is_uv5_hub() ? "UV500" :
1691 is_uv4_hub() ? "UV400" :
1692 is_uv3_hub() ? "UV300" :
1693 is_uv2_hub() ? "UV2000/3000" : NULL;
1696 pr_err("UV: Unknown/unsupported UV hub\n");
1699 pr_info("UV: Found %s hub\n", hub);
1703 /* Get uv_systab for decoding, setup UV BIOS calls */
1706 /* If there's an UVsystab problem then abort UV init: */
1707 if (decode_uv_systab() < 0) {
1708 pr_err("UV: Mangled UVsystab format\n");
1712 build_socket_tables();
1713 build_uv_gr_table();
1715 uv_init_hub_info(&hub_info);
1716 uv_possible_blades = num_possible_nodes();
1717 if (!_node_to_pnode)
1718 boot_init_possible_blades(&hub_info);
1720 /* uv_num_possible_blades() is really the hub count: */
1721 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1723 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1724 hub_info.coherency_domain_number = sn_coherency_id;
1727 bytes = sizeof(void *) * uv_num_possible_blades();
1728 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1729 BUG_ON(!__uv_hub_info_list);
1731 bytes = sizeof(struct uv_hub_info_s);
1732 for_each_node(nodeid) {
1733 struct uv_hub_info_s *new_hub;
1735 if (__uv_hub_info_list[nodeid]) {
1736 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1740 /* Allocate new per hub info list */
1741 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1743 __uv_hub_info_list[nodeid] = new_hub;
1744 new_hub = uv_hub_info_list(nodeid);
1746 *new_hub = hub_info;
1748 /* Use information from GAM table if available: */
1750 new_hub->pnode = _node_to_pnode[nodeid];
1751 else /* Or fill in during CPU loop: */
1752 new_hub->pnode = 0xffff;
1754 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1755 new_hub->memory_nid = NUMA_NO_NODE;
1756 new_hub->nr_possible_cpus = 0;
1757 new_hub->nr_online_cpus = 0;
1760 /* Initialize per CPU info: */
1761 for_each_possible_cpu(cpu) {
1762 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1764 unsigned short pnode;
1766 nodeid = cpu_to_node(cpu);
1767 numa_node_id = numa_cpu_node(cpu);
1768 pnode = uv_apicid_to_pnode(apicid);
1770 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1771 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1772 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1773 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1775 /* Init memoryless node: */
1776 if (nodeid != numa_node_id &&
1777 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1778 uv_hub_info_list(numa_node_id)->pnode = pnode;
1779 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1780 uv_cpu_hub_info(cpu)->pnode = pnode;
1783 for_each_node(nodeid) {
1784 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1786 /* Add pnode info for pre-GAM list nodes without CPUs: */
1787 if (pnode == 0xffff) {
1788 unsigned long paddr;
1790 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1791 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1792 uv_hub_info_list(nodeid)->pnode = pnode;
1794 min_pnode = min(pnode, min_pnode);
1795 max_pnode = max(pnode, max_pnode);
1796 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1798 uv_hub_info_list(nodeid)->pnode,
1799 uv_hub_info_list(nodeid)->nr_possible_cpus);
1802 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1803 map_gru_high(max_pnode);
1804 map_mmr_high(max_pnode);
1805 map_mmioh_high(min_pnode, max_pnode);
1809 uv_setup_proc_files(0);
1811 /* Register Legacy VGA I/O redirection handler: */
1812 pci_register_set_vga_state(uv_set_vga_state);
1818 * There is a different code path needed to initialize a UV system that does
1819 * not have a "UV HUB" (referred to as "hubless").
1821 void __init uv_system_init(void)
1823 if (likely(!is_uv_system() && !is_uv_hubless(1)))
1827 uv_system_init_hub();
1829 uv_system_init_hubless();
1832 apic_driver(apic_x2apic_uv_x);