2 * Local APIC related interfaces to support IOAPIC, MSI, etc.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/interrupt.h>
14 #include <linux/seq_file.h>
15 #include <linux/init.h>
16 #include <linux/compiler.h>
17 #include <linux/slab.h>
18 #include <asm/irqdomain.h>
19 #include <asm/hw_irq.h>
21 #include <asm/i8259.h>
23 #include <asm/irq_remapping.h>
25 #include <asm/trace/irq_vectors.h>
27 struct apic_chip_data {
28 struct irq_cfg hw_irq_cfg;
30 unsigned int prev_vector;
32 unsigned int prev_cpu;
34 struct hlist_node clist;
35 unsigned int move_in_progress : 1,
41 struct irq_domain *x86_vector_domain;
42 EXPORT_SYMBOL_GPL(x86_vector_domain);
43 static DEFINE_RAW_SPINLOCK(vector_lock);
44 static cpumask_var_t vector_searchmask;
45 static struct irq_chip lapic_controller;
46 static struct irq_matrix *vector_matrix;
48 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
51 void lock_vector_lock(void)
53 /* Used to the online set of cpus does not change
54 * during assign_irq_vector.
56 raw_spin_lock(&vector_lock);
59 void unlock_vector_lock(void)
61 raw_spin_unlock(&vector_lock);
64 void init_irq_alloc_info(struct irq_alloc_info *info,
65 const struct cpumask *mask)
67 memset(info, 0, sizeof(*info));
71 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
76 memset(dst, 0, sizeof(*dst));
79 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
84 while (irqd->parent_data)
85 irqd = irqd->parent_data;
87 return irqd->chip_data;
90 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
92 struct apic_chip_data *apicd = apic_chip_data(irqd);
94 return apicd ? &apicd->hw_irq_cfg : NULL;
96 EXPORT_SYMBOL_GPL(irqd_cfg);
98 struct irq_cfg *irq_cfg(unsigned int irq)
100 return irqd_cfg(irq_get_irq_data(irq));
103 static struct apic_chip_data *alloc_apic_chip_data(int node)
105 struct apic_chip_data *apicd;
107 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
109 INIT_HLIST_NODE(&apicd->clist);
113 static void free_apic_chip_data(struct apic_chip_data *apicd)
118 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
121 struct apic_chip_data *apicd = apic_chip_data(irqd);
123 lockdep_assert_held(&vector_lock);
125 apicd->hw_irq_cfg.vector = vector;
126 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
127 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
128 trace_vector_config(irqd->irq, vector, cpu,
129 apicd->hw_irq_cfg.dest_apicid);
132 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
135 struct apic_chip_data *apicd = apic_chip_data(irqd);
136 struct irq_desc *desc = irq_data_to_desc(irqd);
137 bool managed = irqd_affinity_is_managed(irqd);
139 lockdep_assert_held(&vector_lock);
141 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
145 * If there is no vector associated or if the associated vector is
146 * the shutdown vector, which is associated to make PCI/MSI
147 * shutdown mode work, then there is nothing to release. Clear out
148 * prev_vector for this and the offlined target case.
150 apicd->prev_vector = 0;
151 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
154 * If the target CPU of the previous vector is online, then mark
155 * the vector as move in progress and store it for cleanup when the
156 * first interrupt on the new vector arrives. If the target CPU is
157 * offline then the regular release mechanism via the cleanup
158 * vector is not possible and the vector can be immediately freed
159 * in the underlying matrix allocator.
161 if (cpu_online(apicd->cpu)) {
162 apicd->move_in_progress = true;
163 apicd->prev_vector = apicd->vector;
164 apicd->prev_cpu = apicd->cpu;
166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
171 apicd->vector = newvec;
173 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
174 per_cpu(vector_irq, newcpu)[newvec] = desc;
177 static void vector_assign_managed_shutdown(struct irq_data *irqd)
179 unsigned int cpu = cpumask_first(cpu_online_mask);
181 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
184 static int reserve_managed_vector(struct irq_data *irqd)
186 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
187 struct apic_chip_data *apicd = apic_chip_data(irqd);
191 raw_spin_lock_irqsave(&vector_lock, flags);
192 apicd->is_managed = true;
193 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
194 raw_spin_unlock_irqrestore(&vector_lock, flags);
195 trace_vector_reserve_managed(irqd->irq, ret);
199 static void reserve_irq_vector_locked(struct irq_data *irqd)
201 struct apic_chip_data *apicd = apic_chip_data(irqd);
203 irq_matrix_reserve(vector_matrix);
204 apicd->can_reserve = true;
205 apicd->has_reserved = true;
206 irqd_set_can_reserve(irqd);
207 trace_vector_reserve(irqd->irq, 0);
208 vector_assign_managed_shutdown(irqd);
211 static int reserve_irq_vector(struct irq_data *irqd)
215 raw_spin_lock_irqsave(&vector_lock, flags);
216 reserve_irq_vector_locked(irqd);
217 raw_spin_unlock_irqrestore(&vector_lock, flags);
222 assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest)
224 struct apic_chip_data *apicd = apic_chip_data(irqd);
225 bool resvd = apicd->has_reserved;
226 unsigned int cpu = apicd->cpu;
227 int vector = apicd->vector;
229 lockdep_assert_held(&vector_lock);
232 * If the current target CPU is online and in the new requested
233 * affinity mask, there is no point in moving the interrupt from
234 * one CPU to another.
236 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
240 * Careful here. @apicd might either have move_in_progress set or
241 * be enqueued for cleanup. Assigning a new vector would either
242 * leave a stale vector on some CPU around or in case of a pending
243 * cleanup corrupt the hlist.
245 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
248 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
249 trace_vector_alloc(irqd->irq, vector, resvd, vector);
252 apic_update_vector(irqd, vector, cpu);
253 apic_update_irq_cfg(irqd, vector, cpu);
258 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
263 raw_spin_lock_irqsave(&vector_lock, flags);
264 cpumask_and(vector_searchmask, dest, cpu_online_mask);
265 ret = assign_vector_locked(irqd, vector_searchmask);
266 raw_spin_unlock_irqrestore(&vector_lock, flags);
270 static int assign_irq_vector_any_locked(struct irq_data *irqd)
272 /* Get the affinity mask - either irq_default_affinity or (user) set */
273 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
274 int node = irq_data_get_node(irqd);
276 if (node == NUMA_NO_NODE)
278 /* Try the intersection of @affmsk and node mask */
279 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
280 if (!assign_vector_locked(irqd, vector_searchmask))
282 /* Try the node mask */
283 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
286 /* Try the full affinity mask */
287 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
288 if (!assign_vector_locked(irqd, vector_searchmask))
290 /* Try the full online mask */
291 return assign_vector_locked(irqd, cpu_online_mask);
295 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
297 if (irqd_affinity_is_managed(irqd))
298 return reserve_managed_vector(irqd);
300 return assign_irq_vector(irqd, info->mask);
302 * Make only a global reservation with no guarantee. A real vector
303 * is associated at activation time.
305 return reserve_irq_vector(irqd);
309 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
311 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
312 struct apic_chip_data *apicd = apic_chip_data(irqd);
315 cpumask_and(vector_searchmask, vector_searchmask, affmsk);
316 cpu = cpumask_first(vector_searchmask);
317 if (cpu >= nr_cpu_ids)
319 /* set_affinity might call here for nothing */
320 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
322 vector = irq_matrix_alloc_managed(vector_matrix, cpu);
323 trace_vector_alloc_managed(irqd->irq, vector, vector);
326 apic_update_vector(irqd, vector, cpu);
327 apic_update_irq_cfg(irqd, vector, cpu);
331 static void clear_irq_vector(struct irq_data *irqd)
333 struct apic_chip_data *apicd = apic_chip_data(irqd);
334 bool managed = irqd_affinity_is_managed(irqd);
335 unsigned int vector = apicd->vector;
337 lockdep_assert_held(&vector_lock);
342 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
345 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED;
346 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
349 /* Clean up move in progress */
350 vector = apicd->prev_vector;
354 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED;
355 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
356 apicd->prev_vector = 0;
357 apicd->move_in_progress = 0;
358 hlist_del_init(&apicd->clist);
361 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
363 struct apic_chip_data *apicd = apic_chip_data(irqd);
366 trace_vector_deactivate(irqd->irq, apicd->is_managed,
367 apicd->can_reserve, false);
369 /* Regular fixed assigned interrupt */
370 if (!apicd->is_managed && !apicd->can_reserve)
372 /* If the interrupt has a global reservation, nothing to do */
373 if (apicd->has_reserved)
376 raw_spin_lock_irqsave(&vector_lock, flags);
377 clear_irq_vector(irqd);
378 if (apicd->can_reserve)
379 reserve_irq_vector_locked(irqd);
381 vector_assign_managed_shutdown(irqd);
382 raw_spin_unlock_irqrestore(&vector_lock, flags);
385 static int activate_reserved(struct irq_data *irqd)
387 struct apic_chip_data *apicd = apic_chip_data(irqd);
390 ret = assign_irq_vector_any_locked(irqd);
392 apicd->has_reserved = false;
394 * Core might have disabled reservation mode after
395 * allocating the irq descriptor. Ideally this should
396 * happen before allocation time, but that would require
397 * completely convoluted ways of transporting that
400 if (!irqd_can_reserve(irqd))
401 apicd->can_reserve = false;
406 static int activate_managed(struct irq_data *irqd)
408 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
411 cpumask_and(vector_searchmask, dest, cpu_online_mask);
412 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
413 /* Something in the core code broke! Survive gracefully */
414 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
418 ret = assign_managed_vector(irqd, vector_searchmask);
420 * This should not happen. The vector reservation got buggered. Handle
423 if (WARN_ON_ONCE(ret < 0)) {
424 pr_err("Managed startup irq %u, no vector available\n",
430 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
433 struct apic_chip_data *apicd = apic_chip_data(irqd);
437 trace_vector_activate(irqd->irq, apicd->is_managed,
438 apicd->can_reserve, reserve);
440 /* Nothing to do for fixed assigned vectors */
441 if (!apicd->can_reserve && !apicd->is_managed)
444 raw_spin_lock_irqsave(&vector_lock, flags);
445 if (reserve || irqd_is_managed_and_shutdown(irqd))
446 vector_assign_managed_shutdown(irqd);
447 else if (apicd->is_managed)
448 ret = activate_managed(irqd);
449 else if (apicd->has_reserved)
450 ret = activate_reserved(irqd);
451 raw_spin_unlock_irqrestore(&vector_lock, flags);
455 static void vector_free_reserved_and_managed(struct irq_data *irqd)
457 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
458 struct apic_chip_data *apicd = apic_chip_data(irqd);
460 trace_vector_teardown(irqd->irq, apicd->is_managed,
461 apicd->has_reserved);
463 if (apicd->has_reserved)
464 irq_matrix_remove_reserved(vector_matrix);
465 if (apicd->is_managed)
466 irq_matrix_remove_managed(vector_matrix, dest);
469 static void x86_vector_free_irqs(struct irq_domain *domain,
470 unsigned int virq, unsigned int nr_irqs)
472 struct apic_chip_data *apicd;
473 struct irq_data *irqd;
477 for (i = 0; i < nr_irqs; i++) {
478 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
479 if (irqd && irqd->chip_data) {
480 raw_spin_lock_irqsave(&vector_lock, flags);
481 clear_irq_vector(irqd);
482 vector_free_reserved_and_managed(irqd);
483 apicd = irqd->chip_data;
484 irq_domain_reset_irq_data(irqd);
485 raw_spin_unlock_irqrestore(&vector_lock, flags);
486 free_apic_chip_data(apicd);
491 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
492 struct apic_chip_data *apicd)
495 bool realloc = false;
497 apicd->vector = ISA_IRQ_VECTOR(virq);
500 raw_spin_lock_irqsave(&vector_lock, flags);
502 * If the interrupt is activated, then it must stay at this vector
503 * position. That's usually the timer interrupt (0).
505 if (irqd_is_activated(irqd)) {
506 trace_vector_setup(virq, true, 0);
507 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
509 /* Release the vector */
510 apicd->can_reserve = true;
511 irqd_set_can_reserve(irqd);
512 clear_irq_vector(irqd);
515 raw_spin_unlock_irqrestore(&vector_lock, flags);
519 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
520 unsigned int nr_irqs, void *arg)
522 struct irq_alloc_info *info = arg;
523 struct apic_chip_data *apicd;
524 struct irq_data *irqd;
530 /* Currently vector allocator can't guarantee contiguous allocations */
531 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
534 for (i = 0; i < nr_irqs; i++) {
535 irqd = irq_domain_get_irq_data(domain, virq + i);
537 node = irq_data_get_node(irqd);
538 WARN_ON_ONCE(irqd->chip_data);
539 apicd = alloc_apic_chip_data(node);
545 apicd->irq = virq + i;
546 irqd->chip = &lapic_controller;
547 irqd->chip_data = apicd;
548 irqd->hwirq = virq + i;
549 irqd_set_single_target(irqd);
551 * Legacy vectors are already assigned when the IOAPIC
552 * takes them over. They stay on the same vector. This is
553 * required for check_timer() to work correctly as it might
554 * switch back to legacy mode. Only update the hardware
557 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
558 if (!vector_configure_legacy(virq + i, irqd, apicd))
562 err = assign_irq_vector_policy(irqd, info);
563 trace_vector_setup(virq + i, false, err);
565 irqd->chip_data = NULL;
566 free_apic_chip_data(apicd);
574 x86_vector_free_irqs(domain, virq, i);
578 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
579 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
580 struct irq_data *irqd, int ind)
582 struct apic_chip_data apicd;
587 irq_matrix_debug_show(m, vector_matrix, ind);
592 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
593 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
594 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
598 if (!irqd->chip_data) {
599 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
603 raw_spin_lock_irqsave(&vector_lock, flags);
604 memcpy(&apicd, irqd->chip_data, sizeof(apicd));
605 raw_spin_unlock_irqrestore(&vector_lock, flags);
607 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
608 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
609 if (apicd.prev_vector) {
610 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
611 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
613 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
614 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0);
615 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0);
616 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0);
617 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist));
621 static const struct irq_domain_ops x86_vector_domain_ops = {
622 .alloc = x86_vector_alloc_irqs,
623 .free = x86_vector_free_irqs,
624 .activate = x86_vector_activate,
625 .deactivate = x86_vector_deactivate,
626 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
627 .debug_show = x86_vector_debug_show,
631 int __init arch_probe_nr_irqs(void)
635 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
636 nr_irqs = NR_VECTORS * nr_cpu_ids;
638 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
639 #if defined(CONFIG_PCI_MSI)
641 * for MSI and HT dyn irq
643 if (gsi_top <= NR_IRQS_LEGACY)
644 nr += 8 * nr_cpu_ids;
652 * We don't know if PIC is present at this point so we need to do
653 * probe() to get the right number of legacy IRQs.
655 return legacy_pic->probe();
658 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
661 * Use assign system here so it wont get accounted as allocated
662 * and moveable in the cpu hotplug check and it prevents managed
663 * irq reservation from touching it.
665 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
668 void __init lapic_assign_system_vectors(void)
670 unsigned int i, vector = 0;
672 for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
673 irq_matrix_assign_system(vector_matrix, vector, false);
675 if (nr_legacy_irqs() > 1)
676 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
678 /* System vectors are reserved, online it */
679 irq_matrix_online(vector_matrix);
681 /* Mark the preallocated legacy interrupts */
682 for (i = 0; i < nr_legacy_irqs(); i++) {
683 if (i != PIC_CASCADE_IR)
684 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
688 int __init arch_early_irq_init(void)
690 struct fwnode_handle *fn;
692 fn = irq_domain_alloc_named_fwnode("VECTOR");
694 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
696 BUG_ON(x86_vector_domain == NULL);
697 irq_domain_free_fwnode(fn);
698 irq_set_default_host(x86_vector_domain);
700 arch_init_msi_domain(x86_vector_domain);
702 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
705 * Allocate the vector matrix allocator data structure and limit the
708 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
709 FIRST_SYSTEM_VECTOR);
710 BUG_ON(!vector_matrix);
712 return arch_early_ioapic_init();
717 static struct irq_desc *__setup_vector_irq(int vector)
719 int isairq = vector - ISA_IRQ_VECTOR(0);
721 /* Check whether the irq is in the legacy space */
722 if (isairq < 0 || isairq >= nr_legacy_irqs())
723 return VECTOR_UNUSED;
724 /* Check whether the irq is handled by the IOAPIC */
725 if (test_bit(isairq, &io_apic_irqs))
726 return VECTOR_UNUSED;
727 return irq_to_desc(isairq);
730 /* Online the local APIC infrastructure and initialize the vectors */
731 void lapic_online(void)
735 lockdep_assert_held(&vector_lock);
737 /* Online the vector matrix array for this CPU */
738 irq_matrix_online(vector_matrix);
741 * The interrupt affinity logic never targets interrupts to offline
742 * CPUs. The exception are the legacy PIC interrupts. In general
743 * they are only targeted to CPU0, but depending on the platform
744 * they can be distributed to any online CPU in hardware. The
745 * kernel has no influence on that. So all active legacy vectors
746 * must be installed on all CPUs. All non legacy interrupts can be
749 for (vector = 0; vector < NR_VECTORS; vector++)
750 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
753 void lapic_offline(void)
756 irq_matrix_offline(vector_matrix);
757 unlock_vector_lock();
760 static int apic_set_affinity(struct irq_data *irqd,
761 const struct cpumask *dest, bool force)
763 struct apic_chip_data *apicd = apic_chip_data(irqd);
767 * Core code can call here for inactive interrupts. For inactive
768 * interrupts which use managed or reservation mode there is no
769 * point in going through the vector assignment right now as the
770 * activation will assign a vector which fits the destination
771 * cpumask. Let the core code store the destination mask and be
774 if (!irqd_is_activated(irqd) &&
775 (apicd->is_managed || apicd->can_reserve))
776 return IRQ_SET_MASK_OK;
778 raw_spin_lock(&vector_lock);
779 cpumask_and(vector_searchmask, dest, cpu_online_mask);
780 if (irqd_affinity_is_managed(irqd))
781 err = assign_managed_vector(irqd, vector_searchmask);
783 err = assign_vector_locked(irqd, vector_searchmask);
784 raw_spin_unlock(&vector_lock);
785 return err ? err : IRQ_SET_MASK_OK;
789 # define apic_set_affinity NULL
792 static int apic_retrigger_irq(struct irq_data *irqd)
794 struct apic_chip_data *apicd = apic_chip_data(irqd);
797 raw_spin_lock_irqsave(&vector_lock, flags);
798 apic->send_IPI(apicd->cpu, apicd->vector);
799 raw_spin_unlock_irqrestore(&vector_lock, flags);
804 void apic_ack_irq(struct irq_data *irqd)
810 void apic_ack_edge(struct irq_data *irqd)
812 irq_complete_move(irqd_cfg(irqd));
816 static struct irq_chip lapic_controller = {
818 .irq_ack = apic_ack_edge,
819 .irq_set_affinity = apic_set_affinity,
820 .irq_retrigger = apic_retrigger_irq,
825 static void free_moved_vector(struct apic_chip_data *apicd)
827 unsigned int vector = apicd->prev_vector;
828 unsigned int cpu = apicd->prev_cpu;
829 bool managed = apicd->is_managed;
832 * This should never happen. Managed interrupts are not
833 * migrated except on CPU down, which does not involve the
834 * cleanup vector. But try to keep the accounting correct
837 WARN_ON_ONCE(managed);
839 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
840 irq_matrix_free(vector_matrix, cpu, vector, managed);
841 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
842 hlist_del_init(&apicd->clist);
843 apicd->prev_vector = 0;
844 apicd->move_in_progress = 0;
847 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
849 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
850 struct apic_chip_data *apicd;
851 struct hlist_node *tmp;
854 /* Prevent vectors vanishing under us */
855 raw_spin_lock(&vector_lock);
857 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
858 unsigned int irr, vector = apicd->prev_vector;
861 * Paranoia: Check if the vector that needs to be cleaned
862 * up is registered at the APICs IRR. If so, then this is
863 * not the best time to clean it up. Clean it up in the
864 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
865 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
866 * priority external vector, so on return from this
867 * interrupt the device interrupt will happen first.
869 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
870 if (irr & (1U << (vector % 32))) {
871 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
874 free_moved_vector(apicd);
877 raw_spin_unlock(&vector_lock);
881 static void __send_cleanup_vector(struct apic_chip_data *apicd)
885 raw_spin_lock(&vector_lock);
886 apicd->move_in_progress = 0;
887 cpu = apicd->prev_cpu;
888 if (cpu_online(cpu)) {
889 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
890 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
892 apicd->prev_vector = 0;
894 raw_spin_unlock(&vector_lock);
897 void send_cleanup_vector(struct irq_cfg *cfg)
899 struct apic_chip_data *apicd;
901 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
902 if (apicd->move_in_progress)
903 __send_cleanup_vector(apicd);
906 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
908 struct apic_chip_data *apicd;
910 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
911 if (likely(!apicd->move_in_progress))
914 if (vector == apicd->vector && apicd->cpu == smp_processor_id())
915 __send_cleanup_vector(apicd);
918 void irq_complete_move(struct irq_cfg *cfg)
920 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
924 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
926 void irq_force_complete_move(struct irq_desc *desc)
928 struct apic_chip_data *apicd;
929 struct irq_data *irqd;
933 * The function is called for all descriptors regardless of which
934 * irqdomain they belong to. For example if an IRQ is provided by
935 * an irq_chip as part of a GPIO driver, the chip data for that
936 * descriptor is specific to the irq_chip in question.
938 * Check first that the chip_data is what we expect
939 * (apic_chip_data) before touching it any further.
941 irqd = irq_domain_get_irq_data(x86_vector_domain,
942 irq_desc_get_irq(desc));
946 raw_spin_lock(&vector_lock);
947 apicd = apic_chip_data(irqd);
952 * If prev_vector is empty, no action required.
954 vector = apicd->prev_vector;
959 * This is tricky. If the cleanup of the old vector has not been
960 * done yet, then the following setaffinity call will fail with
961 * -EBUSY. This can leave the interrupt in a stale state.
963 * All CPUs are stuck in stop machine with interrupts disabled so
964 * calling __irq_complete_move() would be completely pointless.
966 * 1) The interrupt is in move_in_progress state. That means that we
967 * have not seen an interrupt since the io_apic was reprogrammed to
970 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
971 * have not been processed yet.
973 if (apicd->move_in_progress) {
975 * In theory there is a race:
977 * set_ioapic(new_vector) <-- Interrupt is raised before update
978 * is effective, i.e. it's raised on
981 * So if the target cpu cannot handle that interrupt before
982 * the old vector is cleaned up, we get a spurious interrupt
983 * and in the worst case the ioapic irq line becomes stale.
985 * But in case of cpu hotplug this should be a non issue
986 * because if the affinity update happens right before all
987 * cpus rendevouz in stop machine, there is no way that the
988 * interrupt can be blocked on the target cpu because all cpus
989 * loops first with interrupts enabled in stop machine, so the
990 * old vector is not yet cleaned up when the interrupt fires.
992 * So the only way to run into this issue is if the delivery
993 * of the interrupt on the apic/system bus would be delayed
994 * beyond the point where the target cpu disables interrupts
995 * in stop machine. I doubt that it can happen, but at least
996 * there is a theroretical chance. Virtualization might be
997 * able to expose this, but AFAICT the IOAPIC emulation is not
998 * as stupid as the real hardware.
1000 * Anyway, there is nothing we can do about that at this point
1001 * w/o refactoring the whole fixup_irq() business completely.
1002 * We print at least the irq number and the old vector number,
1003 * so we have the necessary information when a problem in that
1006 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1009 free_moved_vector(apicd);
1011 raw_spin_unlock(&vector_lock);
1014 #ifdef CONFIG_HOTPLUG_CPU
1016 * Note, this is not accurate accounting, but at least good enough to
1017 * prevent that the actual interrupt move will run out of vectors.
1019 int lapic_can_unplug_cpu(void)
1021 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1024 raw_spin_lock(&vector_lock);
1025 tomove = irq_matrix_allocated(vector_matrix);
1026 avl = irq_matrix_available(vector_matrix, true);
1028 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1033 rsvd = irq_matrix_reserved(vector_matrix);
1035 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1039 raw_spin_unlock(&vector_lock);
1042 #endif /* HOTPLUG_CPU */
1045 static void __init print_APIC_field(int base)
1051 for (i = 0; i < 8; i++)
1052 pr_cont("%08x", apic_read(base + i*0x10));
1057 static void __init print_local_APIC(void *dummy)
1059 unsigned int i, v, ver, maxlvt;
1062 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1063 smp_processor_id(), hard_smp_processor_id());
1064 v = apic_read(APIC_ID);
1065 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1066 v = apic_read(APIC_LVR);
1067 pr_info("... APIC VERSION: %08x\n", v);
1068 ver = GET_APIC_VERSION(v);
1069 maxlvt = lapic_get_maxlvt();
1071 v = apic_read(APIC_TASKPRI);
1072 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1075 if (APIC_INTEGRATED(ver)) {
1076 if (!APIC_XAPIC(ver)) {
1077 v = apic_read(APIC_ARBPRI);
1078 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1079 v, v & APIC_ARBPRI_MASK);
1081 v = apic_read(APIC_PROCPRI);
1082 pr_debug("... APIC PROCPRI: %08x\n", v);
1086 * Remote read supported only in the 82489DX and local APIC for
1087 * Pentium processors.
1089 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1090 v = apic_read(APIC_RRR);
1091 pr_debug("... APIC RRR: %08x\n", v);
1094 v = apic_read(APIC_LDR);
1095 pr_debug("... APIC LDR: %08x\n", v);
1096 if (!x2apic_enabled()) {
1097 v = apic_read(APIC_DFR);
1098 pr_debug("... APIC DFR: %08x\n", v);
1100 v = apic_read(APIC_SPIV);
1101 pr_debug("... APIC SPIV: %08x\n", v);
1103 pr_debug("... APIC ISR field:\n");
1104 print_APIC_field(APIC_ISR);
1105 pr_debug("... APIC TMR field:\n");
1106 print_APIC_field(APIC_TMR);
1107 pr_debug("... APIC IRR field:\n");
1108 print_APIC_field(APIC_IRR);
1111 if (APIC_INTEGRATED(ver)) {
1112 /* Due to the Pentium erratum 3AP. */
1114 apic_write(APIC_ESR, 0);
1116 v = apic_read(APIC_ESR);
1117 pr_debug("... APIC ESR: %08x\n", v);
1120 icr = apic_icr_read();
1121 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1122 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1124 v = apic_read(APIC_LVTT);
1125 pr_debug("... APIC LVTT: %08x\n", v);
1129 v = apic_read(APIC_LVTPC);
1130 pr_debug("... APIC LVTPC: %08x\n", v);
1132 v = apic_read(APIC_LVT0);
1133 pr_debug("... APIC LVT0: %08x\n", v);
1134 v = apic_read(APIC_LVT1);
1135 pr_debug("... APIC LVT1: %08x\n", v);
1139 v = apic_read(APIC_LVTERR);
1140 pr_debug("... APIC LVTERR: %08x\n", v);
1143 v = apic_read(APIC_TMICT);
1144 pr_debug("... APIC TMICT: %08x\n", v);
1145 v = apic_read(APIC_TMCCT);
1146 pr_debug("... APIC TMCCT: %08x\n", v);
1147 v = apic_read(APIC_TDCR);
1148 pr_debug("... APIC TDCR: %08x\n", v);
1150 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1151 v = apic_read(APIC_EFEAT);
1152 maxlvt = (v >> 16) & 0xff;
1153 pr_debug("... APIC EFEAT: %08x\n", v);
1154 v = apic_read(APIC_ECTRL);
1155 pr_debug("... APIC ECTRL: %08x\n", v);
1156 for (i = 0; i < maxlvt; i++) {
1157 v = apic_read(APIC_EILVTn(i));
1158 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1164 static void __init print_local_APICs(int maxcpu)
1172 for_each_online_cpu(cpu) {
1175 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1180 static void __init print_PIC(void)
1183 unsigned long flags;
1185 if (!nr_legacy_irqs())
1188 pr_debug("\nprinting PIC contents\n");
1190 raw_spin_lock_irqsave(&i8259A_lock, flags);
1192 v = inb(0xa1) << 8 | inb(0x21);
1193 pr_debug("... PIC IMR: %04x\n", v);
1195 v = inb(0xa0) << 8 | inb(0x20);
1196 pr_debug("... PIC IRR: %04x\n", v);
1200 v = inb(0xa0) << 8 | inb(0x20);
1204 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1206 pr_debug("... PIC ISR: %04x\n", v);
1208 v = inb(0x4d1) << 8 | inb(0x4d0);
1209 pr_debug("... PIC ELCR: %04x\n", v);
1212 static int show_lapic __initdata = 1;
1213 static __init int setup_show_lapic(char *arg)
1217 if (strcmp(arg, "all") == 0) {
1218 show_lapic = CONFIG_NR_CPUS;
1220 get_option(&arg, &num);
1227 __setup("show_lapic=", setup_show_lapic);
1229 static int __init print_ICs(void)
1231 if (apic_verbosity == APIC_QUIET)
1236 /* don't print out if apic is not there */
1237 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1240 print_local_APICs(show_lapic);
1246 late_initcall(print_ICs);