1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
23 * Historical information which is worth to be preserved:
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
35 #include <linux/interrupt.h>
36 #include <linux/init.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/pci.h>
40 #include <linux/mc146818rtc.h>
41 #include <linux/compiler.h>
42 #include <linux/acpi.h>
43 #include <linux/export.h>
44 #include <linux/syscore_ops.h>
45 #include <linux/freezer.h>
46 #include <linux/kthread.h>
47 #include <linux/jiffies.h> /* time_after() */
48 #include <linux/slab.h>
49 #include <linux/bootmem.h>
51 #include <asm/irqdomain.h>
56 #include <asm/proto.h>
59 #include <asm/timer.h>
60 #include <asm/i8259.h>
61 #include <asm/setup.h>
62 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
67 #define for_each_ioapic(idx) \
68 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
69 #define for_each_ioapic_reverse(idx) \
70 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
71 #define for_each_pin(idx, pin) \
72 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73 #define for_each_ioapic_pin(idx, pin) \
74 for_each_ioapic((idx)) \
75 for_each_pin((idx), (pin))
76 #define for_each_irq_pin(entry, head) \
77 list_for_each_entry(entry, &head, list)
79 static DEFINE_RAW_SPINLOCK(ioapic_lock);
80 static DEFINE_MUTEX(ioapic_mutex);
81 static unsigned int ioapic_dynirq_base;
82 static int ioapic_initialized;
85 struct list_head list;
90 struct list_head irq_2_pin;
91 struct IO_APIC_route_entry entry;
98 struct mp_ioapic_gsi {
103 static struct ioapic {
105 * # of IRQ routing registers
109 * Saved state during suspend/resume, or while enabling intr-remap.
111 struct IO_APIC_route_entry *saved_registers;
112 /* I/O APIC config */
113 struct mpc_ioapic mp_config;
114 /* IO APIC gsi routing info */
115 struct mp_ioapic_gsi gsi_config;
116 struct ioapic_domain_cfg irqdomain_cfg;
117 struct irq_domain *irqdomain;
118 struct resource *iomem_res;
119 } ioapics[MAX_IO_APICS];
121 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
123 int mpc_ioapic_id(int ioapic_idx)
125 return ioapics[ioapic_idx].mp_config.apicid;
128 unsigned int mpc_ioapic_addr(int ioapic_idx)
130 return ioapics[ioapic_idx].mp_config.apicaddr;
133 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
135 return &ioapics[ioapic_idx].gsi_config;
138 static inline int mp_ioapic_pin_count(int ioapic)
140 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
150 static inline bool mp_is_legacy_irq(int irq)
152 return irq >= 0 && irq < nr_legacy_irqs();
156 * Initialize all legacy IRQs and all pins on the first IOAPIC
157 * if we have legacy interrupt controller. Kernel boot option "pirq="
158 * may rely on non-legacy pins on the first IOAPIC.
160 static inline int mp_init_irq_at_boot(int ioapic, int irq)
162 if (!nr_legacy_irqs())
165 return ioapic == 0 || mp_is_legacy_irq(irq);
168 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
170 return ioapics[ioapic].irqdomain;
175 /* The one past the highest gsi number used */
178 /* MP IRQ source entries */
179 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
181 /* # of MP IRQ source entries */
185 int mp_bus_id_to_type[MAX_MP_BUSSES];
188 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
190 int skip_ioapic_setup;
193 * disable_ioapic_support() - disables ioapic support at runtime
195 void disable_ioapic_support(void)
199 noioapicreroute = -1;
201 skip_ioapic_setup = 1;
204 static int __init parse_noapic(char *str)
206 /* disable IO-APIC */
207 disable_ioapic_support();
210 early_param("noapic", parse_noapic);
212 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
213 void mp_save_irq(struct mpc_intsrc *m)
217 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
218 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
219 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
220 m->srcbusirq, m->dstapic, m->dstirq);
222 for (i = 0; i < mp_irq_entries; i++) {
223 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
227 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
228 if (++mp_irq_entries == MAX_IRQ_SOURCES)
229 panic("Max # of irq sources exceeded!!\n");
232 static void alloc_ioapic_saved_registers(int idx)
236 if (ioapics[idx].saved_registers)
239 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
240 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
241 if (!ioapics[idx].saved_registers)
242 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
245 static void free_ioapic_saved_registers(int idx)
247 kfree(ioapics[idx].saved_registers);
248 ioapics[idx].saved_registers = NULL;
251 int __init arch_early_ioapic_init(void)
255 if (!nr_legacy_irqs())
259 alloc_ioapic_saved_registers(i);
266 unsigned int unused[3];
268 unsigned int unused2[11];
272 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
274 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
275 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
278 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
280 struct io_apic __iomem *io_apic = io_apic_base(apic);
281 writel(vector, &io_apic->eoi);
284 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
286 struct io_apic __iomem *io_apic = io_apic_base(apic);
287 writel(reg, &io_apic->index);
288 return readl(&io_apic->data);
291 static void io_apic_write(unsigned int apic, unsigned int reg,
294 struct io_apic __iomem *io_apic = io_apic_base(apic);
296 writel(reg, &io_apic->index);
297 writel(value, &io_apic->data);
301 struct { u32 w1, w2; };
302 struct IO_APIC_route_entry entry;
305 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
307 union entry_union eu;
309 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
310 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
315 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
317 union entry_union eu;
320 raw_spin_lock_irqsave(&ioapic_lock, flags);
321 eu.entry = __ioapic_read_entry(apic, pin);
322 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
328 * When we write a new IO APIC routing entry, we need to write the high
329 * word first! If the mask bit in the low word is clear, we will enable
330 * the interrupt, and we need to make sure the entry is fully populated
331 * before that happens.
333 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
335 union entry_union eu = {{0, 0}};
338 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
339 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
342 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
346 raw_spin_lock_irqsave(&ioapic_lock, flags);
347 __ioapic_write_entry(apic, pin, e);
348 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
352 * When we mask an IO APIC routing entry, we need to write the low
353 * word first, in order to set the mask bit before we change the
356 static void ioapic_mask_entry(int apic, int pin)
359 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
361 raw_spin_lock_irqsave(&ioapic_lock, flags);
362 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
363 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
364 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
368 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
369 * shared ISA-space IRQs, so we have to support them. We are super
370 * fast in the common case, and fast for shared ISA-space IRQs.
372 static int __add_pin_to_irq_node(struct mp_chip_data *data,
373 int node, int apic, int pin)
375 struct irq_pin_list *entry;
377 /* don't allow duplicates */
378 for_each_irq_pin(entry, data->irq_2_pin)
379 if (entry->apic == apic && entry->pin == pin)
382 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
384 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
390 list_add_tail(&entry->list, &data->irq_2_pin);
395 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
397 struct irq_pin_list *tmp, *entry;
399 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
400 if (entry->apic == apic && entry->pin == pin) {
401 list_del(&entry->list);
407 static void add_pin_to_irq_node(struct mp_chip_data *data,
408 int node, int apic, int pin)
410 if (__add_pin_to_irq_node(data, node, apic, pin))
411 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
415 * Reroute an IRQ to a different pin.
417 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
418 int oldapic, int oldpin,
419 int newapic, int newpin)
421 struct irq_pin_list *entry;
423 for_each_irq_pin(entry, data->irq_2_pin) {
424 if (entry->apic == oldapic && entry->pin == oldpin) {
425 entry->apic = newapic;
427 /* every one is different, right? */
432 /* old apic/pin didn't exist, so just add new ones */
433 add_pin_to_irq_node(data, node, newapic, newpin);
436 static void io_apic_modify_irq(struct mp_chip_data *data,
437 int mask_and, int mask_or,
438 void (*final)(struct irq_pin_list *entry))
440 union entry_union eu;
441 struct irq_pin_list *entry;
443 eu.entry = data->entry;
446 data->entry = eu.entry;
448 for_each_irq_pin(entry, data->irq_2_pin) {
449 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
455 static void io_apic_sync(struct irq_pin_list *entry)
458 * Synchronize the IO-APIC and the CPU by doing
459 * a dummy read from the IO-APIC
461 struct io_apic __iomem *io_apic;
463 io_apic = io_apic_base(entry->apic);
464 readl(&io_apic->data);
467 static void mask_ioapic_irq(struct irq_data *irq_data)
469 struct mp_chip_data *data = irq_data->chip_data;
472 raw_spin_lock_irqsave(&ioapic_lock, flags);
473 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
474 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
477 static void __unmask_ioapic(struct mp_chip_data *data)
479 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
482 static void unmask_ioapic_irq(struct irq_data *irq_data)
484 struct mp_chip_data *data = irq_data->chip_data;
487 raw_spin_lock_irqsave(&ioapic_lock, flags);
488 __unmask_ioapic(data);
489 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
493 * IO-APIC versions below 0x20 don't support EOI register.
494 * For the record, here is the information about various versions:
496 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
497 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
500 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
501 * version as 0x2. This is an error with documentation and these ICH chips
502 * use io-apic's of version 0x20.
504 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
505 * Otherwise, we simulate the EOI message manually by changing the trigger
506 * mode to edge and then back to level, with RTE being masked during this.
508 static void __eoi_ioapic_pin(int apic, int pin, int vector)
510 if (mpc_ioapic_ver(apic) >= 0x20) {
511 io_apic_eoi(apic, vector);
513 struct IO_APIC_route_entry entry, entry1;
515 entry = entry1 = __ioapic_read_entry(apic, pin);
518 * Mask the entry and change the trigger mode to edge.
520 entry1.mask = IOAPIC_MASKED;
521 entry1.trigger = IOAPIC_EDGE;
523 __ioapic_write_entry(apic, pin, entry1);
526 * Restore the previous level triggered entry.
528 __ioapic_write_entry(apic, pin, entry);
532 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
535 struct irq_pin_list *entry;
537 raw_spin_lock_irqsave(&ioapic_lock, flags);
538 for_each_irq_pin(entry, data->irq_2_pin)
539 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
540 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
543 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
545 struct IO_APIC_route_entry entry;
547 /* Check delivery_mode to be sure we're not clearing an SMI pin */
548 entry = ioapic_read_entry(apic, pin);
549 if (entry.delivery_mode == dest_SMI)
553 * Make sure the entry is masked and re-read the contents to check
554 * if it is a level triggered pin and if the remote-IRR is set.
556 if (entry.mask == IOAPIC_UNMASKED) {
557 entry.mask = IOAPIC_MASKED;
558 ioapic_write_entry(apic, pin, entry);
559 entry = ioapic_read_entry(apic, pin);
566 * Make sure the trigger mode is set to level. Explicit EOI
567 * doesn't clear the remote-IRR if the trigger mode is not
570 if (entry.trigger == IOAPIC_EDGE) {
571 entry.trigger = IOAPIC_LEVEL;
572 ioapic_write_entry(apic, pin, entry);
574 raw_spin_lock_irqsave(&ioapic_lock, flags);
575 __eoi_ioapic_pin(apic, pin, entry.vector);
576 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
580 * Clear the rest of the bits in the IO-APIC RTE except for the mask
583 ioapic_mask_entry(apic, pin);
584 entry = ioapic_read_entry(apic, pin);
586 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
587 mpc_ioapic_id(apic), pin);
590 static void clear_IO_APIC (void)
594 for_each_ioapic_pin(apic, pin)
595 clear_IO_APIC_pin(apic, pin);
600 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
601 * specific CPU-side IRQs.
605 static int pirq_entries[MAX_PIRQS] = {
606 [0 ... MAX_PIRQS - 1] = -1
609 static int __init ioapic_pirq_setup(char *str)
612 int ints[MAX_PIRQS+1];
614 get_options(str, ARRAY_SIZE(ints), ints);
616 apic_printk(APIC_VERBOSE, KERN_INFO
617 "PIRQ redirection, working around broken MP-BIOS.\n");
619 if (ints[0] < MAX_PIRQS)
622 for (i = 0; i < max; i++) {
623 apic_printk(APIC_VERBOSE, KERN_DEBUG
624 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
626 * PIRQs are mapped upside down, usually.
628 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
633 __setup("pirq=", ioapic_pirq_setup);
634 #endif /* CONFIG_X86_32 */
637 * Saves all the IO-APIC RTE's
639 int save_ioapic_entries(void)
644 for_each_ioapic(apic) {
645 if (!ioapics[apic].saved_registers) {
650 for_each_pin(apic, pin)
651 ioapics[apic].saved_registers[pin] =
652 ioapic_read_entry(apic, pin);
659 * Mask all IO APIC entries.
661 void mask_ioapic_entries(void)
665 for_each_ioapic(apic) {
666 if (!ioapics[apic].saved_registers)
669 for_each_pin(apic, pin) {
670 struct IO_APIC_route_entry entry;
672 entry = ioapics[apic].saved_registers[pin];
673 if (entry.mask == IOAPIC_UNMASKED) {
674 entry.mask = IOAPIC_MASKED;
675 ioapic_write_entry(apic, pin, entry);
682 * Restore IO APIC entries which was saved in the ioapic structure.
684 int restore_ioapic_entries(void)
688 for_each_ioapic(apic) {
689 if (!ioapics[apic].saved_registers)
692 for_each_pin(apic, pin)
693 ioapic_write_entry(apic, pin,
694 ioapics[apic].saved_registers[pin]);
700 * Find the IRQ entry number of a certain pin.
702 static int find_irq_entry(int ioapic_idx, int pin, int type)
706 for (i = 0; i < mp_irq_entries; i++)
707 if (mp_irqs[i].irqtype == type &&
708 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
709 mp_irqs[i].dstapic == MP_APIC_ALL) &&
710 mp_irqs[i].dstirq == pin)
717 * Find the pin to which IRQ[irq] (ISA) is connected
719 static int __init find_isa_irq_pin(int irq, int type)
723 for (i = 0; i < mp_irq_entries; i++) {
724 int lbus = mp_irqs[i].srcbus;
726 if (test_bit(lbus, mp_bus_not_pci) &&
727 (mp_irqs[i].irqtype == type) &&
728 (mp_irqs[i].srcbusirq == irq))
730 return mp_irqs[i].dstirq;
735 static int __init find_isa_irq_apic(int irq, int type)
739 for (i = 0; i < mp_irq_entries; i++) {
740 int lbus = mp_irqs[i].srcbus;
742 if (test_bit(lbus, mp_bus_not_pci) &&
743 (mp_irqs[i].irqtype == type) &&
744 (mp_irqs[i].srcbusirq == irq))
748 if (i < mp_irq_entries) {
751 for_each_ioapic(ioapic_idx)
752 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
761 * EISA Edge/Level control register, ELCR
763 static int EISA_ELCR(unsigned int irq)
765 if (irq < nr_legacy_irqs()) {
766 unsigned int port = 0x4d0 + (irq >> 3);
767 return (inb(port) >> (irq & 7)) & 1;
769 apic_printk(APIC_VERBOSE, KERN_INFO
770 "Broken MPtable reports ISA irq %d\n", irq);
776 /* ISA interrupts are always active high edge triggered,
777 * when listed as conforming in the MP table. */
779 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
780 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
782 /* EISA interrupts are always polarity zero and can be edge or level
783 * trigger depending on the ELCR value. If an interrupt is listed as
784 * EISA conforming in the MP table, that means its trigger type must
785 * be read in from the ELCR */
787 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
788 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
790 /* PCI interrupts are always active low level triggered,
791 * when listed as conforming in the MP table. */
793 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
794 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
796 static int irq_polarity(int idx)
798 int bus = mp_irqs[idx].srcbus;
801 * Determine IRQ line polarity (high active or low active):
803 switch (mp_irqs[idx].irqflag & 0x03) {
805 /* conforms to spec, ie. bus-type dependent polarity */
806 if (test_bit(bus, mp_bus_not_pci))
807 return default_ISA_polarity(idx);
809 return default_PCI_polarity(idx);
811 return IOAPIC_POL_HIGH;
813 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
815 default: /* Pointless default required due to do gcc stupidity */
816 return IOAPIC_POL_LOW;
821 static int eisa_irq_trigger(int idx, int bus, int trigger)
823 switch (mp_bus_id_to_type[bus]) {
828 return default_EISA_trigger(idx);
830 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
834 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
840 static int irq_trigger(int idx)
842 int bus = mp_irqs[idx].srcbus;
846 * Determine IRQ trigger mode (edge or level sensitive):
848 switch ((mp_irqs[idx].irqflag >> 2) & 0x03) {
850 /* conforms to spec, ie. bus-type dependent trigger mode */
851 if (test_bit(bus, mp_bus_not_pci))
852 trigger = default_ISA_trigger(idx);
854 trigger = default_PCI_trigger(idx);
855 /* Take EISA into account */
856 return eisa_irq_trigger(idx, bus, trigger);
860 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
862 default: /* Pointless default required due to do gcc stupidity */
867 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
868 int trigger, int polarity)
870 init_irq_alloc_info(info, NULL);
871 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
872 info->ioapic_node = node;
873 info->ioapic_trigger = trigger;
874 info->ioapic_polarity = polarity;
875 info->ioapic_valid = 1;
879 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
882 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
883 struct irq_alloc_info *src,
884 u32 gsi, int ioapic_idx, int pin)
886 int trigger, polarity;
888 copy_irq_alloc_info(dst, src);
889 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
890 dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
891 dst->ioapic_pin = pin;
892 dst->ioapic_valid = 1;
893 if (src && src->ioapic_valid) {
894 dst->ioapic_node = src->ioapic_node;
895 dst->ioapic_trigger = src->ioapic_trigger;
896 dst->ioapic_polarity = src->ioapic_polarity;
898 dst->ioapic_node = NUMA_NO_NODE;
899 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
900 dst->ioapic_trigger = trigger;
901 dst->ioapic_polarity = polarity;
904 * PCI interrupts are always active low level
907 dst->ioapic_trigger = IOAPIC_LEVEL;
908 dst->ioapic_polarity = IOAPIC_POL_LOW;
913 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
915 return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
918 static void mp_register_handler(unsigned int irq, unsigned long trigger)
920 irq_flow_handler_t hdl;
924 irq_set_status_flags(irq, IRQ_LEVEL);
927 irq_clear_status_flags(irq, IRQ_LEVEL);
931 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
932 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
935 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
937 struct mp_chip_data *data = irq_get_chip_data(irq);
940 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
941 * and polarity attirbutes. So allow the first user to reprogram the
942 * pin with real trigger and polarity attributes.
944 if (irq < nr_legacy_irqs() && data->count == 1) {
945 if (info->ioapic_trigger != data->trigger)
946 mp_register_handler(irq, info->ioapic_trigger);
947 data->entry.trigger = data->trigger = info->ioapic_trigger;
948 data->entry.polarity = data->polarity = info->ioapic_polarity;
951 return data->trigger == info->ioapic_trigger &&
952 data->polarity == info->ioapic_polarity;
955 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
956 struct irq_alloc_info *info)
960 int type = ioapics[ioapic].irqdomain_cfg.type;
963 case IOAPIC_DOMAIN_LEGACY:
965 * Dynamically allocate IRQ number for non-ISA IRQs in the first
966 * 16 GSIs on some weird platforms.
968 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
970 legacy = mp_is_legacy_irq(irq);
972 case IOAPIC_DOMAIN_STRICT:
975 case IOAPIC_DOMAIN_DYNAMIC:
978 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
982 return __irq_domain_alloc_irqs(domain, irq, 1,
983 ioapic_alloc_attr_node(info),
988 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
989 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
990 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
991 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
992 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
993 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
994 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
995 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
997 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
998 int irq, int ioapic, int pin,
999 struct irq_alloc_info *info)
1001 struct mp_chip_data *data;
1002 struct irq_data *irq_data = irq_get_irq_data(irq);
1003 int node = ioapic_alloc_attr_node(info);
1006 * Legacy ISA IRQ has already been allocated, just add pin to
1007 * the pin list assoicated with this IRQ and program the IOAPIC
1008 * entry. The IOAPIC entry
1010 if (irq_data && irq_data->parent_data) {
1011 if (!mp_check_pin_attr(irq, info))
1013 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1017 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1020 irq_data = irq_domain_get_irq_data(domain, irq);
1021 data = irq_data->chip_data;
1022 data->isa_irq = true;
1029 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1030 unsigned int flags, struct irq_alloc_info *info)
1033 bool legacy = false;
1034 struct irq_alloc_info tmp;
1035 struct mp_chip_data *data;
1036 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1041 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1042 irq = mp_irqs[idx].srcbusirq;
1043 legacy = mp_is_legacy_irq(irq);
1046 mutex_lock(&ioapic_mutex);
1047 if (!(flags & IOAPIC_MAP_ALLOC)) {
1049 irq = irq_find_mapping(domain, pin);
1054 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1056 irq = alloc_isa_irq_from_domain(domain, irq,
1058 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1059 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1060 else if (!mp_check_pin_attr(irq, &tmp))
1063 data = irq_get_chip_data(irq);
1067 mutex_unlock(&ioapic_mutex);
1072 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1074 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1077 * Debugging check, we are in big trouble if this message pops up!
1079 if (mp_irqs[idx].dstirq != pin)
1080 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1082 #ifdef CONFIG_X86_32
1084 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1086 if ((pin >= 16) && (pin <= 23)) {
1087 if (pirq_entries[pin-16] != -1) {
1088 if (!pirq_entries[pin-16]) {
1089 apic_printk(APIC_VERBOSE, KERN_DEBUG
1090 "disabling PIRQ%d\n", pin-16);
1092 int irq = pirq_entries[pin-16];
1093 apic_printk(APIC_VERBOSE, KERN_DEBUG
1094 "using PIRQ%d -> IRQ %d\n",
1102 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1105 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1107 int ioapic, pin, idx;
1109 ioapic = mp_find_ioapic(gsi);
1113 pin = mp_find_ioapic_pin(ioapic, gsi);
1114 idx = find_irq_entry(ioapic, pin, mp_INT);
1115 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1118 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1121 void mp_unmap_irq(int irq)
1123 struct irq_data *irq_data = irq_get_irq_data(irq);
1124 struct mp_chip_data *data;
1126 if (!irq_data || !irq_data->domain)
1129 data = irq_data->chip_data;
1130 if (!data || data->isa_irq)
1133 mutex_lock(&ioapic_mutex);
1134 if (--data->count == 0)
1135 irq_domain_free_irqs(irq, 1);
1136 mutex_unlock(&ioapic_mutex);
1140 * Find a specific PCI IRQ entry.
1141 * Not an __init, possibly needed by modules
1143 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1145 int irq, i, best_ioapic = -1, best_idx = -1;
1147 apic_printk(APIC_DEBUG,
1148 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1150 if (test_bit(bus, mp_bus_not_pci)) {
1151 apic_printk(APIC_VERBOSE,
1152 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1156 for (i = 0; i < mp_irq_entries; i++) {
1157 int lbus = mp_irqs[i].srcbus;
1158 int ioapic_idx, found = 0;
1160 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1161 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1164 for_each_ioapic(ioapic_idx)
1165 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1166 mp_irqs[i].dstapic == MP_APIC_ALL) {
1174 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1175 if (irq > 0 && !IO_APIC_IRQ(irq))
1178 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1180 best_ioapic = ioapic_idx;
1185 * Use the first all-but-pin matching entry as a
1186 * best-guess fuzzy result for broken mptables.
1190 best_ioapic = ioapic_idx;
1197 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1200 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1202 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1204 static void __init setup_IO_APIC_irqs(void)
1206 unsigned int ioapic, pin;
1209 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1211 for_each_ioapic_pin(ioapic, pin) {
1212 idx = find_irq_entry(ioapic, pin, mp_INT);
1214 apic_printk(APIC_VERBOSE,
1215 KERN_DEBUG " apic %d pin %d not connected\n",
1216 mpc_ioapic_id(ioapic), pin);
1218 pin_2_irq(idx, ioapic, pin,
1219 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1223 void ioapic_zap_locks(void)
1225 raw_spin_lock_init(&ioapic_lock);
1228 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1232 struct IO_APIC_route_entry entry;
1233 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1235 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1236 for (i = 0; i <= nr_entries; i++) {
1237 entry = ioapic_read_entry(apic, i);
1238 snprintf(buf, sizeof(buf),
1239 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1241 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1242 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1243 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1244 entry.vector, entry.irr, entry.delivery_status);
1245 if (ir_entry->format)
1246 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1247 buf, (ir_entry->index2 << 15) | ir_entry->index,
1250 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1252 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1253 "logical " : "physical",
1254 entry.dest, entry.delivery_mode);
1258 static void __init print_IO_APIC(int ioapic_idx)
1260 union IO_APIC_reg_00 reg_00;
1261 union IO_APIC_reg_01 reg_01;
1262 union IO_APIC_reg_02 reg_02;
1263 union IO_APIC_reg_03 reg_03;
1264 unsigned long flags;
1266 raw_spin_lock_irqsave(&ioapic_lock, flags);
1267 reg_00.raw = io_apic_read(ioapic_idx, 0);
1268 reg_01.raw = io_apic_read(ioapic_idx, 1);
1269 if (reg_01.bits.version >= 0x10)
1270 reg_02.raw = io_apic_read(ioapic_idx, 2);
1271 if (reg_01.bits.version >= 0x20)
1272 reg_03.raw = io_apic_read(ioapic_idx, 3);
1273 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1275 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1276 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1277 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1278 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1279 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1281 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1282 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1283 reg_01.bits.entries);
1285 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1286 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1287 reg_01.bits.version);
1290 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1291 * but the value of reg_02 is read as the previous read register
1292 * value, so ignore it if reg_02 == reg_01.
1294 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1295 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1296 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1300 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1301 * or reg_03, but the value of reg_0[23] is read as the previous read
1302 * register value, so ignore it if reg_03 == reg_0[12].
1304 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1305 reg_03.raw != reg_01.raw) {
1306 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1307 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1310 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1311 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1314 void __init print_IO_APICs(void)
1319 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1320 for_each_ioapic(ioapic_idx)
1321 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1322 mpc_ioapic_id(ioapic_idx),
1323 ioapics[ioapic_idx].nr_registers);
1326 * We are a bit conservative about what we expect. We have to
1327 * know about every hardware change ASAP.
1329 printk(KERN_INFO "testing the IO APIC.......................\n");
1331 for_each_ioapic(ioapic_idx)
1332 print_IO_APIC(ioapic_idx);
1334 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1335 for_each_active_irq(irq) {
1336 struct irq_pin_list *entry;
1337 struct irq_chip *chip;
1338 struct mp_chip_data *data;
1340 chip = irq_get_chip(irq);
1341 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1343 data = irq_get_chip_data(irq);
1346 if (list_empty(&data->irq_2_pin))
1349 printk(KERN_DEBUG "IRQ%d ", irq);
1350 for_each_irq_pin(entry, data->irq_2_pin)
1351 pr_cont("-> %d:%d", entry->apic, entry->pin);
1355 printk(KERN_INFO ".................................... done.\n");
1358 /* Where if anywhere is the i8259 connect in external int mode */
1359 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1361 void __init enable_IO_APIC(void)
1363 int i8259_apic, i8259_pin;
1366 if (skip_ioapic_setup)
1369 if (!nr_legacy_irqs() || !nr_ioapics)
1372 for_each_ioapic_pin(apic, pin) {
1373 /* See if any of the pins is in ExtINT mode */
1374 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1376 /* If the interrupt line is enabled and in ExtInt mode
1377 * I have found the pin where the i8259 is connected.
1379 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1380 ioapic_i8259.apic = apic;
1381 ioapic_i8259.pin = pin;
1386 /* Look to see what if the MP table has reported the ExtINT */
1387 /* If we could not find the appropriate pin by looking at the ioapic
1388 * the i8259 probably is not connected the ioapic but give the
1389 * mptable a chance anyway.
1391 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1392 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1393 /* Trust the MP table if nothing is setup in the hardware */
1394 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1395 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1396 ioapic_i8259.pin = i8259_pin;
1397 ioapic_i8259.apic = i8259_apic;
1399 /* Complain if the MP table and the hardware disagree */
1400 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1401 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1403 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1407 * Do not trust the IO-APIC being empty at bootup
1412 void native_disable_io_apic(void)
1415 * If the i8259 is routed through an IOAPIC
1416 * Put that IOAPIC in virtual wire mode
1417 * so legacy interrupts can be delivered.
1419 if (ioapic_i8259.pin != -1) {
1420 struct IO_APIC_route_entry entry;
1422 memset(&entry, 0, sizeof(entry));
1423 entry.mask = IOAPIC_UNMASKED;
1424 entry.trigger = IOAPIC_EDGE;
1425 entry.polarity = IOAPIC_POL_HIGH;
1426 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1427 entry.delivery_mode = dest_ExtINT;
1428 entry.dest = read_apic_id();
1431 * Add it to the IO-APIC irq-routing table:
1433 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1436 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1437 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1441 * Not an __init, needed by the reboot code
1443 void disable_IO_APIC(void)
1446 * Clear the IO-APIC before rebooting:
1450 if (!nr_legacy_irqs())
1453 x86_io_apic_ops.disable();
1456 #ifdef CONFIG_X86_32
1458 * function to set the IO-APIC physical IDs based on the
1459 * values stored in the MPC table.
1461 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1463 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1465 union IO_APIC_reg_00 reg_00;
1466 physid_mask_t phys_id_present_map;
1469 unsigned char old_id;
1470 unsigned long flags;
1473 * This is broken; anything with a real cpu count has to
1474 * circumvent this idiocy regardless.
1476 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1479 * Set the IOAPIC ID to the value stored in the MPC table.
1481 for_each_ioapic(ioapic_idx) {
1482 /* Read the register 0 value */
1483 raw_spin_lock_irqsave(&ioapic_lock, flags);
1484 reg_00.raw = io_apic_read(ioapic_idx, 0);
1485 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1487 old_id = mpc_ioapic_id(ioapic_idx);
1489 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1490 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1491 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1492 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1494 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1498 * Sanity check, is the ID really free? Every APIC in a
1499 * system must have a unique ID or we get lots of nice
1500 * 'stuck on smp_invalidate_needed IPI wait' messages.
1502 if (apic->check_apicid_used(&phys_id_present_map,
1503 mpc_ioapic_id(ioapic_idx))) {
1504 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1505 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1506 for (i = 0; i < get_physical_broadcast(); i++)
1507 if (!physid_isset(i, phys_id_present_map))
1509 if (i >= get_physical_broadcast())
1510 panic("Max APIC ID exceeded!\n");
1511 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1513 physid_set(i, phys_id_present_map);
1514 ioapics[ioapic_idx].mp_config.apicid = i;
1517 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1519 apic_printk(APIC_VERBOSE, "Setting %d in the "
1520 "phys_id_present_map\n",
1521 mpc_ioapic_id(ioapic_idx));
1522 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1526 * We need to adjust the IRQ routing table
1527 * if the ID changed.
1529 if (old_id != mpc_ioapic_id(ioapic_idx))
1530 for (i = 0; i < mp_irq_entries; i++)
1531 if (mp_irqs[i].dstapic == old_id)
1533 = mpc_ioapic_id(ioapic_idx);
1536 * Update the ID register according to the right value
1537 * from the MPC table if they are different.
1539 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1542 apic_printk(APIC_VERBOSE, KERN_INFO
1543 "...changing IO-APIC physical APIC ID to %d ...",
1544 mpc_ioapic_id(ioapic_idx));
1546 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1547 raw_spin_lock_irqsave(&ioapic_lock, flags);
1548 io_apic_write(ioapic_idx, 0, reg_00.raw);
1549 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1554 raw_spin_lock_irqsave(&ioapic_lock, flags);
1555 reg_00.raw = io_apic_read(ioapic_idx, 0);
1556 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1557 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1558 pr_cont("could not set ID!\n");
1560 apic_printk(APIC_VERBOSE, " ok.\n");
1564 void __init setup_ioapic_ids_from_mpc(void)
1570 * Don't check I/O APIC IDs for xAPIC systems. They have
1571 * no meaning without the serial APIC bus.
1573 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1574 || APIC_XAPIC(boot_cpu_apic_version))
1576 setup_ioapic_ids_from_mpc_nocheck();
1580 int no_timer_check __initdata;
1582 static int __init notimercheck(char *s)
1587 __setup("no_timer_check", notimercheck);
1590 * There is a nasty bug in some older SMP boards, their mptable lies
1591 * about the timer IRQ. We do the following to work around the situation:
1593 * - timer IRQ defaults to IO-APIC IRQ
1594 * - if this function detects that timer IRQs are defunct, then we fall
1595 * back to ISA timer IRQs
1597 static int __init timer_irq_works(void)
1599 unsigned long t1 = jiffies;
1600 unsigned long flags;
1605 local_save_flags(flags);
1607 /* Let ten ticks pass... */
1608 mdelay((10 * 1000) / HZ);
1609 local_irq_restore(flags);
1612 * Expect a few ticks at least, to be sure some possible
1613 * glue logic does not lock up after one or two first
1614 * ticks in a non-ExtINT mode. Also the local APIC
1615 * might have cached one ExtINT interrupt. Finally, at
1616 * least one tick may be lost due to delays.
1620 if (time_after(jiffies, t1 + 4))
1626 * In the SMP+IOAPIC case it might happen that there are an unspecified
1627 * number of pending IRQ events unhandled. These cases are very rare,
1628 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1629 * better to do it this way as thus we do not have to be aware of
1630 * 'pending' interrupts in the IRQ path, except at this point.
1633 * Edge triggered needs to resend any interrupt
1634 * that was delayed but this is now handled in the device
1639 * Starting up a edge-triggered IO-APIC interrupt is
1640 * nasty - we need to make sure that we get the edge.
1641 * If it is already asserted for some reason, we need
1642 * return 1 to indicate that is was pending.
1644 * This is not complete - we should be able to fake
1645 * an edge even if it isn't on the 8259A...
1647 static unsigned int startup_ioapic_irq(struct irq_data *data)
1649 int was_pending = 0, irq = data->irq;
1650 unsigned long flags;
1652 raw_spin_lock_irqsave(&ioapic_lock, flags);
1653 if (irq < nr_legacy_irqs()) {
1654 legacy_pic->mask(irq);
1655 if (legacy_pic->irq_pending(irq))
1658 __unmask_ioapic(data->chip_data);
1659 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1664 atomic_t irq_mis_count;
1666 #ifdef CONFIG_GENERIC_PENDING_IRQ
1667 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1669 struct irq_pin_list *entry;
1670 unsigned long flags;
1672 raw_spin_lock_irqsave(&ioapic_lock, flags);
1673 for_each_irq_pin(entry, data->irq_2_pin) {
1678 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1679 /* Is the remote IRR bit set? */
1680 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1681 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1685 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1690 static inline bool ioapic_irqd_mask(struct irq_data *data)
1692 /* If we are moving the irq we need to mask it */
1693 if (unlikely(irqd_is_setaffinity_pending(data))) {
1694 mask_ioapic_irq(data);
1700 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1702 if (unlikely(masked)) {
1703 /* Only migrate the irq if the ack has been received.
1705 * On rare occasions the broadcast level triggered ack gets
1706 * delayed going to ioapics, and if we reprogram the
1707 * vector while Remote IRR is still set the irq will never
1710 * To prevent this scenario we read the Remote IRR bit
1711 * of the ioapic. This has two effects.
1712 * - On any sane system the read of the ioapic will
1713 * flush writes (and acks) going to the ioapic from
1715 * - We get to see if the ACK has actually been delivered.
1717 * Based on failed experiments of reprogramming the
1718 * ioapic entry from outside of irq context starting
1719 * with masking the ioapic entry and then polling until
1720 * Remote IRR was clear before reprogramming the
1721 * ioapic I don't trust the Remote IRR bit to be
1722 * completey accurate.
1724 * However there appears to be no other way to plug
1725 * this race, so if the Remote IRR bit is not
1726 * accurate and is causing problems then it is a hardware bug
1727 * and you can go talk to the chipset vendor about it.
1729 if (!io_apic_level_ack_pending(data->chip_data))
1730 irq_move_masked_irq(data);
1731 unmask_ioapic_irq(data);
1735 static inline bool ioapic_irqd_mask(struct irq_data *data)
1739 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1744 static void ioapic_ack_level(struct irq_data *irq_data)
1746 struct irq_cfg *cfg = irqd_cfg(irq_data);
1751 irq_complete_move(cfg);
1752 masked = ioapic_irqd_mask(irq_data);
1755 * It appears there is an erratum which affects at least version 0x11
1756 * of I/O APIC (that's the 82093AA and cores integrated into various
1757 * chipsets). Under certain conditions a level-triggered interrupt is
1758 * erroneously delivered as edge-triggered one but the respective IRR
1759 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1760 * message but it will never arrive and further interrupts are blocked
1761 * from the source. The exact reason is so far unknown, but the
1762 * phenomenon was observed when two consecutive interrupt requests
1763 * from a given source get delivered to the same CPU and the source is
1764 * temporarily disabled in between.
1766 * A workaround is to simulate an EOI message manually. We achieve it
1767 * by setting the trigger mode to edge and then to level when the edge
1768 * trigger mode gets detected in the TMR of a local APIC for a
1769 * level-triggered interrupt. We mask the source for the time of the
1770 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1771 * The idea is from Manfred Spraul. --macro
1773 * Also in the case when cpu goes offline, fixup_irqs() will forward
1774 * any unhandled interrupt on the offlined cpu to the new cpu
1775 * destination that is handling the corresponding interrupt. This
1776 * interrupt forwarding is done via IPI's. Hence, in this case also
1777 * level-triggered io-apic interrupt will be seen as an edge
1778 * interrupt in the IRR. And we can't rely on the cpu's EOI
1779 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1780 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1781 * supporting EOI register, we do an explicit EOI to clear the
1782 * remote IRR and on IO-APIC's which don't have an EOI register,
1783 * we use the above logic (mask+edge followed by unmask+level) from
1784 * Manfred Spraul to clear the remote IRR.
1787 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1790 * We must acknowledge the irq before we move it or the acknowledge will
1791 * not propagate properly.
1796 * Tail end of clearing remote IRR bit (either by delivering the EOI
1797 * message via io-apic EOI register write or simulating it using
1798 * mask+edge followed by unnask+level logic) manually when the
1799 * level triggered interrupt is seen as the edge triggered interrupt
1802 if (!(v & (1 << (i & 0x1f)))) {
1803 atomic_inc(&irq_mis_count);
1804 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1807 ioapic_irqd_unmask(irq_data, masked);
1810 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1812 struct mp_chip_data *data = irq_data->chip_data;
1815 * Intr-remapping uses pin number as the virtual vector
1816 * in the RTE. Actual vector is programmed in
1817 * intr-remapping table entry. Hence for the io-apic
1818 * EOI we use the pin number.
1821 eoi_ioapic_pin(data->entry.vector, data);
1824 static int ioapic_set_affinity(struct irq_data *irq_data,
1825 const struct cpumask *mask, bool force)
1827 struct irq_data *parent = irq_data->parent_data;
1828 struct mp_chip_data *data = irq_data->chip_data;
1829 struct irq_pin_list *entry;
1830 struct irq_cfg *cfg;
1831 unsigned long flags;
1834 ret = parent->chip->irq_set_affinity(parent, mask, force);
1835 raw_spin_lock_irqsave(&ioapic_lock, flags);
1836 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
1837 cfg = irqd_cfg(irq_data);
1838 data->entry.dest = cfg->dest_apicid;
1839 data->entry.vector = cfg->vector;
1840 for_each_irq_pin(entry, data->irq_2_pin)
1841 __ioapic_write_entry(entry->apic, entry->pin,
1844 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1849 static struct irq_chip ioapic_chip __read_mostly = {
1851 .irq_startup = startup_ioapic_irq,
1852 .irq_mask = mask_ioapic_irq,
1853 .irq_unmask = unmask_ioapic_irq,
1854 .irq_ack = irq_chip_ack_parent,
1855 .irq_eoi = ioapic_ack_level,
1856 .irq_set_affinity = ioapic_set_affinity,
1857 .irq_retrigger = irq_chip_retrigger_hierarchy,
1858 .flags = IRQCHIP_SKIP_SET_WAKE,
1861 static struct irq_chip ioapic_ir_chip __read_mostly = {
1862 .name = "IR-IO-APIC",
1863 .irq_startup = startup_ioapic_irq,
1864 .irq_mask = mask_ioapic_irq,
1865 .irq_unmask = unmask_ioapic_irq,
1866 .irq_ack = irq_chip_ack_parent,
1867 .irq_eoi = ioapic_ir_ack_level,
1868 .irq_set_affinity = ioapic_set_affinity,
1869 .irq_retrigger = irq_chip_retrigger_hierarchy,
1870 .flags = IRQCHIP_SKIP_SET_WAKE,
1873 static inline void init_IO_APIC_traps(void)
1875 struct irq_cfg *cfg;
1878 for_each_active_irq(irq) {
1880 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1882 * Hmm.. We don't have an entry for this,
1883 * so default to an old-fashioned 8259
1884 * interrupt if we can..
1886 if (irq < nr_legacy_irqs())
1887 legacy_pic->make_irq(irq);
1889 /* Strange. Oh, well.. */
1890 irq_set_chip(irq, &no_irq_chip);
1896 * The local APIC irq-chip implementation:
1899 static void mask_lapic_irq(struct irq_data *data)
1903 v = apic_read(APIC_LVT0);
1904 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1907 static void unmask_lapic_irq(struct irq_data *data)
1911 v = apic_read(APIC_LVT0);
1912 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1915 static void ack_lapic_irq(struct irq_data *data)
1920 static struct irq_chip lapic_chip __read_mostly = {
1921 .name = "local-APIC",
1922 .irq_mask = mask_lapic_irq,
1923 .irq_unmask = unmask_lapic_irq,
1924 .irq_ack = ack_lapic_irq,
1927 static void lapic_register_intr(int irq)
1929 irq_clear_status_flags(irq, IRQ_LEVEL);
1930 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1935 * This looks a bit hackish but it's about the only one way of sending
1936 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1937 * not support the ExtINT mode, unfortunately. We need to send these
1938 * cycles as some i82489DX-based boards have glue logic that keeps the
1939 * 8259A interrupt line asserted until INTA. --macro
1941 static inline void __init unlock_ExtINT_logic(void)
1944 struct IO_APIC_route_entry entry0, entry1;
1945 unsigned char save_control, save_freq_select;
1947 pin = find_isa_irq_pin(8, mp_INT);
1952 apic = find_isa_irq_apic(8, mp_INT);
1958 entry0 = ioapic_read_entry(apic, pin);
1959 clear_IO_APIC_pin(apic, pin);
1961 memset(&entry1, 0, sizeof(entry1));
1963 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1964 entry1.mask = IOAPIC_UNMASKED;
1965 entry1.dest = hard_smp_processor_id();
1966 entry1.delivery_mode = dest_ExtINT;
1967 entry1.polarity = entry0.polarity;
1968 entry1.trigger = IOAPIC_EDGE;
1971 ioapic_write_entry(apic, pin, entry1);
1973 save_control = CMOS_READ(RTC_CONTROL);
1974 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1975 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1977 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1982 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1986 CMOS_WRITE(save_control, RTC_CONTROL);
1987 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1988 clear_IO_APIC_pin(apic, pin);
1990 ioapic_write_entry(apic, pin, entry0);
1993 static int disable_timer_pin_1 __initdata;
1994 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
1995 static int __init disable_timer_pin_setup(char *arg)
1997 disable_timer_pin_1 = 1;
2000 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2002 static int mp_alloc_timer_irq(int ioapic, int pin)
2005 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2008 struct irq_alloc_info info;
2010 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2011 info.ioapic_id = mpc_ioapic_id(ioapic);
2012 info.ioapic_pin = pin;
2013 mutex_lock(&ioapic_mutex);
2014 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2015 mutex_unlock(&ioapic_mutex);
2022 * This code may look a bit paranoid, but it's supposed to cooperate with
2023 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2024 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2025 * fanatically on his truly buggy board.
2027 * FIXME: really need to revamp this for all platforms.
2029 static inline void __init check_timer(void)
2031 struct irq_data *irq_data = irq_get_irq_data(0);
2032 struct mp_chip_data *data = irq_data->chip_data;
2033 struct irq_cfg *cfg = irqd_cfg(irq_data);
2034 int node = cpu_to_node(0);
2035 int apic1, pin1, apic2, pin2;
2036 unsigned long flags;
2039 local_irq_save(flags);
2042 * get/set the timer IRQ vector:
2044 legacy_pic->mask(0);
2047 * As IRQ0 is to be enabled in the 8259A, the virtual
2048 * wire has to be disabled in the local APIC. Also
2049 * timer interrupts need to be acknowledged manually in
2050 * the 8259A for the i82489DX when using the NMI
2051 * watchdog as that APIC treats NMIs as level-triggered.
2052 * The AEOI mode will finish them in the 8259A
2055 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2056 legacy_pic->init(1);
2058 pin1 = find_isa_irq_pin(0, mp_INT);
2059 apic1 = find_isa_irq_apic(0, mp_INT);
2060 pin2 = ioapic_i8259.pin;
2061 apic2 = ioapic_i8259.apic;
2063 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2064 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2065 cfg->vector, apic1, pin1, apic2, pin2);
2068 * Some BIOS writers are clueless and report the ExtINTA
2069 * I/O APIC input from the cascaded 8259A as the timer
2070 * interrupt input. So just in case, if only one pin
2071 * was found above, try it both directly and through the
2075 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2079 } else if (pin2 == -1) {
2085 /* Ok, does IRQ0 through the IOAPIC work? */
2087 mp_alloc_timer_irq(apic1, pin1);
2090 * for edge trigger, it's already unmasked,
2091 * so only need to unmask if it is level-trigger
2092 * do we really have level trigger timer?
2095 idx = find_irq_entry(apic1, pin1, mp_INT);
2096 if (idx != -1 && irq_trigger(idx))
2097 unmask_ioapic_irq(irq_get_irq_data(0));
2099 irq_domain_deactivate_irq(irq_data);
2100 irq_domain_activate_irq(irq_data, false);
2101 if (timer_irq_works()) {
2102 if (disable_timer_pin_1 > 0)
2103 clear_IO_APIC_pin(0, pin1);
2106 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2107 local_irq_disable();
2108 clear_IO_APIC_pin(apic1, pin1);
2110 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2111 "8254 timer not connected to IO-APIC\n");
2113 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2114 "(IRQ0) through the 8259A ...\n");
2115 apic_printk(APIC_QUIET, KERN_INFO
2116 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2118 * legacy devices should be connected to IO APIC #0
2120 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2121 irq_domain_deactivate_irq(irq_data);
2122 irq_domain_activate_irq(irq_data, false);
2123 legacy_pic->unmask(0);
2124 if (timer_irq_works()) {
2125 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2129 * Cleanup, just in case ...
2131 local_irq_disable();
2132 legacy_pic->mask(0);
2133 clear_IO_APIC_pin(apic2, pin2);
2134 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2137 apic_printk(APIC_QUIET, KERN_INFO
2138 "...trying to set up timer as Virtual Wire IRQ...\n");
2140 lapic_register_intr(0);
2141 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2142 legacy_pic->unmask(0);
2144 if (timer_irq_works()) {
2145 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2148 local_irq_disable();
2149 legacy_pic->mask(0);
2150 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2151 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2153 apic_printk(APIC_QUIET, KERN_INFO
2154 "...trying to set up timer as ExtINT IRQ...\n");
2156 legacy_pic->init(0);
2157 legacy_pic->make_irq(0);
2158 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2160 unlock_ExtINT_logic();
2162 if (timer_irq_works()) {
2163 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2166 local_irq_disable();
2167 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2168 if (apic_is_x2apic_enabled())
2169 apic_printk(APIC_QUIET, KERN_INFO
2170 "Perhaps problem with the pre-enabled x2apic mode\n"
2171 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2172 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2173 "report. Then try booting with the 'noapic' option.\n");
2175 local_irq_restore(flags);
2179 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2180 * to devices. However there may be an I/O APIC pin available for
2181 * this interrupt regardless. The pin may be left unconnected, but
2182 * typically it will be reused as an ExtINT cascade interrupt for
2183 * the master 8259A. In the MPS case such a pin will normally be
2184 * reported as an ExtINT interrupt in the MP table. With ACPI
2185 * there is no provision for ExtINT interrupts, and in the absence
2186 * of an override it would be treated as an ordinary ISA I/O APIC
2187 * interrupt, that is edge-triggered and unmasked by default. We
2188 * used to do this, but it caused problems on some systems because
2189 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2190 * the same ExtINT cascade interrupt to drive the local APIC of the
2191 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2192 * the I/O APIC in all cases now. No actual device should request
2193 * it anyway. --macro
2195 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2197 static int mp_irqdomain_create(int ioapic)
2199 struct irq_alloc_info info;
2200 struct irq_domain *parent;
2201 int hwirqs = mp_ioapic_pin_count(ioapic);
2202 struct ioapic *ip = &ioapics[ioapic];
2203 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2204 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2205 struct fwnode_handle *fn;
2206 char *name = "IO-APIC";
2208 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2211 init_irq_alloc_info(&info, NULL);
2212 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2213 info.ioapic_id = mpc_ioapic_id(ioapic);
2214 parent = irq_remapping_get_ir_irq_domain(&info);
2216 parent = x86_vector_domain;
2218 name = "IO-APIC-IR";
2220 /* Handle device tree enumerated APICs proper */
2222 fn = of_node_to_fwnode(cfg->dev);
2224 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2229 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2230 (void *)(long)ioapic);
2232 /* Release fw handle if it was allocated above */
2234 irq_domain_free_fwnode(fn);
2239 ip->irqdomain->parent = parent;
2241 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2242 cfg->type == IOAPIC_DOMAIN_STRICT)
2243 ioapic_dynirq_base = max(ioapic_dynirq_base,
2244 gsi_cfg->gsi_end + 1);
2249 static void ioapic_destroy_irqdomain(int idx)
2251 if (ioapics[idx].irqdomain) {
2252 irq_domain_remove(ioapics[idx].irqdomain);
2253 ioapics[idx].irqdomain = NULL;
2257 void __init setup_IO_APIC(void)
2261 if (skip_ioapic_setup || !nr_ioapics)
2264 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2266 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2267 for_each_ioapic(ioapic)
2268 BUG_ON(mp_irqdomain_create(ioapic));
2271 * Set up IO-APIC IRQ routing.
2273 x86_init.mpparse.setup_ioapic_ids();
2276 setup_IO_APIC_irqs();
2277 init_IO_APIC_traps();
2278 if (nr_legacy_irqs())
2281 ioapic_initialized = 1;
2284 static void resume_ioapic_id(int ioapic_idx)
2286 unsigned long flags;
2287 union IO_APIC_reg_00 reg_00;
2289 raw_spin_lock_irqsave(&ioapic_lock, flags);
2290 reg_00.raw = io_apic_read(ioapic_idx, 0);
2291 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2292 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2293 io_apic_write(ioapic_idx, 0, reg_00.raw);
2295 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2298 static void ioapic_resume(void)
2302 for_each_ioapic_reverse(ioapic_idx)
2303 resume_ioapic_id(ioapic_idx);
2305 restore_ioapic_entries();
2308 static struct syscore_ops ioapic_syscore_ops = {
2309 .suspend = save_ioapic_entries,
2310 .resume = ioapic_resume,
2313 static int __init ioapic_init_ops(void)
2315 register_syscore_ops(&ioapic_syscore_ops);
2320 device_initcall(ioapic_init_ops);
2322 static int io_apic_get_redir_entries(int ioapic)
2324 union IO_APIC_reg_01 reg_01;
2325 unsigned long flags;
2327 raw_spin_lock_irqsave(&ioapic_lock, flags);
2328 reg_01.raw = io_apic_read(ioapic, 1);
2329 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2331 /* The register returns the maximum index redir index
2332 * supported, which is one less than the total number of redir
2335 return reg_01.bits.entries + 1;
2338 unsigned int arch_dynirq_lower_bound(unsigned int from)
2341 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2342 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2344 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2347 #ifdef CONFIG_X86_32
2348 static int io_apic_get_unique_id(int ioapic, int apic_id)
2350 union IO_APIC_reg_00 reg_00;
2351 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2353 unsigned long flags;
2357 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2358 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2359 * supports up to 16 on one shared APIC bus.
2361 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2362 * advantage of new APIC bus architecture.
2365 if (physids_empty(apic_id_map))
2366 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2368 raw_spin_lock_irqsave(&ioapic_lock, flags);
2369 reg_00.raw = io_apic_read(ioapic, 0);
2370 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2372 if (apic_id >= get_physical_broadcast()) {
2373 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2374 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2375 apic_id = reg_00.bits.ID;
2379 * Every APIC in a system must have a unique ID or we get lots of nice
2380 * 'stuck on smp_invalidate_needed IPI wait' messages.
2382 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2384 for (i = 0; i < get_physical_broadcast(); i++) {
2385 if (!apic->check_apicid_used(&apic_id_map, i))
2389 if (i == get_physical_broadcast())
2390 panic("Max apic_id exceeded!\n");
2392 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2393 "trying %d\n", ioapic, apic_id, i);
2398 apic->apicid_to_cpu_present(apic_id, &tmp);
2399 physids_or(apic_id_map, apic_id_map, tmp);
2401 if (reg_00.bits.ID != apic_id) {
2402 reg_00.bits.ID = apic_id;
2404 raw_spin_lock_irqsave(&ioapic_lock, flags);
2405 io_apic_write(ioapic, 0, reg_00.raw);
2406 reg_00.raw = io_apic_read(ioapic, 0);
2407 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2410 if (reg_00.bits.ID != apic_id) {
2411 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2417 apic_printk(APIC_VERBOSE, KERN_INFO
2418 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2423 static u8 io_apic_unique_id(int idx, u8 id)
2425 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2426 !APIC_XAPIC(boot_cpu_apic_version))
2427 return io_apic_get_unique_id(idx, id);
2432 static u8 io_apic_unique_id(int idx, u8 id)
2434 union IO_APIC_reg_00 reg_00;
2435 DECLARE_BITMAP(used, 256);
2436 unsigned long flags;
2440 bitmap_zero(used, 256);
2442 __set_bit(mpc_ioapic_id(i), used);
2444 /* Hand out the requested id if available */
2445 if (!test_bit(id, used))
2449 * Read the current id from the ioapic and keep it if
2452 raw_spin_lock_irqsave(&ioapic_lock, flags);
2453 reg_00.raw = io_apic_read(idx, 0);
2454 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2455 new_id = reg_00.bits.ID;
2456 if (!test_bit(new_id, used)) {
2457 apic_printk(APIC_VERBOSE, KERN_INFO
2458 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2464 * Get the next free id and write it to the ioapic.
2466 new_id = find_first_zero_bit(used, 256);
2467 reg_00.bits.ID = new_id;
2468 raw_spin_lock_irqsave(&ioapic_lock, flags);
2469 io_apic_write(idx, 0, reg_00.raw);
2470 reg_00.raw = io_apic_read(idx, 0);
2471 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2473 BUG_ON(reg_00.bits.ID != new_id);
2479 static int io_apic_get_version(int ioapic)
2481 union IO_APIC_reg_01 reg_01;
2482 unsigned long flags;
2484 raw_spin_lock_irqsave(&ioapic_lock, flags);
2485 reg_01.raw = io_apic_read(ioapic, 1);
2486 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2488 return reg_01.bits.version;
2491 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2493 int ioapic, pin, idx;
2495 if (skip_ioapic_setup)
2498 ioapic = mp_find_ioapic(gsi);
2502 pin = mp_find_ioapic_pin(ioapic, gsi);
2506 idx = find_irq_entry(ioapic, pin, mp_INT);
2510 *trigger = irq_trigger(idx);
2511 *polarity = irq_polarity(idx);
2516 * This function currently is only a helper for the i386 smp boot process where
2517 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2518 * so mask in all cases should simply be apic->target_cpus()
2521 void __init setup_ioapic_dest(void)
2523 int pin, ioapic, irq, irq_entry;
2524 const struct cpumask *mask;
2525 struct irq_desc *desc;
2526 struct irq_data *idata;
2527 struct irq_chip *chip;
2529 if (skip_ioapic_setup == 1)
2532 for_each_ioapic_pin(ioapic, pin) {
2533 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2534 if (irq_entry == -1)
2537 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2538 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2541 desc = irq_to_desc(irq);
2542 raw_spin_lock_irq(&desc->lock);
2543 idata = irq_desc_get_irq_data(desc);
2546 * Honour affinities which have been set in early boot
2548 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2549 mask = irq_data_get_affinity_mask(idata);
2551 mask = apic->target_cpus();
2553 chip = irq_data_get_irq_chip(idata);
2554 /* Might be lapic_chip for irq 0 */
2555 if (chip->irq_set_affinity)
2556 chip->irq_set_affinity(idata, mask, false);
2557 raw_spin_unlock_irq(&desc->lock);
2562 #define IOAPIC_RESOURCE_NAME_SIZE 11
2564 static struct resource *ioapic_resources;
2566 static struct resource * __init ioapic_setup_resources(void)
2569 struct resource *res;
2573 if (nr_ioapics == 0)
2576 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2579 mem = alloc_bootmem(n);
2582 mem += sizeof(struct resource) * nr_ioapics;
2584 for_each_ioapic(i) {
2586 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2587 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2588 mem += IOAPIC_RESOURCE_NAME_SIZE;
2589 ioapics[i].iomem_res = &res[i];
2592 ioapic_resources = res;
2597 void __init io_apic_init_mappings(void)
2599 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2600 struct resource *ioapic_res;
2603 ioapic_res = ioapic_setup_resources();
2604 for_each_ioapic(i) {
2605 if (smp_found_config) {
2606 ioapic_phys = mpc_ioapic_addr(i);
2607 #ifdef CONFIG_X86_32
2610 "WARNING: bogus zero IO-APIC "
2611 "address found in MPTABLE, "
2612 "disabling IO/APIC support!\n");
2613 smp_found_config = 0;
2614 skip_ioapic_setup = 1;
2615 goto fake_ioapic_page;
2619 #ifdef CONFIG_X86_32
2622 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2623 ioapic_phys = __pa(ioapic_phys);
2625 set_fixmap_nocache(idx, ioapic_phys);
2626 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2627 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2631 ioapic_res->start = ioapic_phys;
2632 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2637 void __init ioapic_insert_resources(void)
2640 struct resource *r = ioapic_resources;
2645 "IO APIC resources couldn't be allocated.\n");
2649 for_each_ioapic(i) {
2650 insert_resource(&iomem_resource, r);
2655 int mp_find_ioapic(u32 gsi)
2659 if (nr_ioapics == 0)
2662 /* Find the IOAPIC that manages this GSI. */
2663 for_each_ioapic(i) {
2664 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2665 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2669 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2673 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2675 struct mp_ioapic_gsi *gsi_cfg;
2677 if (WARN_ON(ioapic < 0))
2680 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2681 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2684 return gsi - gsi_cfg->gsi_base;
2687 static int bad_ioapic_register(int idx)
2689 union IO_APIC_reg_00 reg_00;
2690 union IO_APIC_reg_01 reg_01;
2691 union IO_APIC_reg_02 reg_02;
2693 reg_00.raw = io_apic_read(idx, 0);
2694 reg_01.raw = io_apic_read(idx, 1);
2695 reg_02.raw = io_apic_read(idx, 2);
2697 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2698 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2699 mpc_ioapic_addr(idx));
2706 static int find_free_ioapic_entry(void)
2710 for (idx = 0; idx < MAX_IO_APICS; idx++)
2711 if (ioapics[idx].nr_registers == 0)
2714 return MAX_IO_APICS;
2718 * mp_register_ioapic - Register an IOAPIC device
2719 * @id: hardware IOAPIC ID
2720 * @address: physical address of IOAPIC register area
2721 * @gsi_base: base of GSI associated with the IOAPIC
2722 * @cfg: configuration information for the IOAPIC
2724 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2725 struct ioapic_domain_cfg *cfg)
2727 bool hotplug = !!ioapic_initialized;
2728 struct mp_ioapic_gsi *gsi_cfg;
2729 int idx, ioapic, entries;
2733 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2736 for_each_ioapic(ioapic)
2737 if (ioapics[ioapic].mp_config.apicaddr == address) {
2738 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2743 idx = find_free_ioapic_entry();
2744 if (idx >= MAX_IO_APICS) {
2745 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2750 ioapics[idx].mp_config.type = MP_IOAPIC;
2751 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2752 ioapics[idx].mp_config.apicaddr = address;
2754 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2755 if (bad_ioapic_register(idx)) {
2756 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2760 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2761 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2764 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2765 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2767 entries = io_apic_get_redir_entries(idx);
2768 gsi_end = gsi_base + entries - 1;
2769 for_each_ioapic(ioapic) {
2770 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2771 if ((gsi_base >= gsi_cfg->gsi_base &&
2772 gsi_base <= gsi_cfg->gsi_end) ||
2773 (gsi_end >= gsi_cfg->gsi_base &&
2774 gsi_end <= gsi_cfg->gsi_end)) {
2775 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2777 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2778 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2782 gsi_cfg = mp_ioapic_gsi_routing(idx);
2783 gsi_cfg->gsi_base = gsi_base;
2784 gsi_cfg->gsi_end = gsi_end;
2786 ioapics[idx].irqdomain = NULL;
2787 ioapics[idx].irqdomain_cfg = *cfg;
2790 * If mp_register_ioapic() is called during early boot stage when
2791 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2792 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2795 if (mp_irqdomain_create(idx)) {
2796 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2799 alloc_ioapic_saved_registers(idx);
2802 if (gsi_cfg->gsi_end >= gsi_top)
2803 gsi_top = gsi_cfg->gsi_end + 1;
2804 if (nr_ioapics <= idx)
2805 nr_ioapics = idx + 1;
2807 /* Set nr_registers to mark entry present */
2808 ioapics[idx].nr_registers = entries;
2810 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2811 idx, mpc_ioapic_id(idx),
2812 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2813 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2818 int mp_unregister_ioapic(u32 gsi_base)
2823 for_each_ioapic(ioapic)
2824 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2829 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2833 for_each_pin(ioapic, pin) {
2834 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2835 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2836 struct mp_chip_data *data;
2839 data = irq_get_chip_data(irq);
2840 if (data && data->count) {
2841 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2848 /* Mark entry not present */
2849 ioapics[ioapic].nr_registers = 0;
2850 ioapic_destroy_irqdomain(ioapic);
2851 free_ioapic_saved_registers(ioapic);
2852 if (ioapics[ioapic].iomem_res)
2853 release_resource(ioapics[ioapic].iomem_res);
2854 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2855 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2860 int mp_ioapic_registered(u32 gsi_base)
2864 for_each_ioapic(ioapic)
2865 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2871 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2872 struct irq_alloc_info *info)
2874 if (info && info->ioapic_valid) {
2875 data->trigger = info->ioapic_trigger;
2876 data->polarity = info->ioapic_polarity;
2877 } else if (acpi_get_override_irq(gsi, &data->trigger,
2878 &data->polarity) < 0) {
2879 /* PCI interrupts are always active low level triggered. */
2880 data->trigger = IOAPIC_LEVEL;
2881 data->polarity = IOAPIC_POL_LOW;
2885 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2886 struct IO_APIC_route_entry *entry)
2888 memset(entry, 0, sizeof(*entry));
2889 entry->delivery_mode = apic->irq_delivery_mode;
2890 entry->dest_mode = apic->irq_dest_mode;
2891 entry->dest = cfg->dest_apicid;
2892 entry->vector = cfg->vector;
2893 entry->trigger = data->trigger;
2894 entry->polarity = data->polarity;
2896 * Mask level triggered irqs. Edge triggered irqs are masked
2897 * by the irq core code in case they fire.
2899 if (data->trigger == IOAPIC_LEVEL)
2900 entry->mask = IOAPIC_MASKED;
2902 entry->mask = IOAPIC_UNMASKED;
2905 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2906 unsigned int nr_irqs, void *arg)
2908 int ret, ioapic, pin;
2909 struct irq_cfg *cfg;
2910 struct irq_data *irq_data;
2911 struct mp_chip_data *data;
2912 struct irq_alloc_info *info = arg;
2913 unsigned long flags;
2915 if (!info || nr_irqs > 1)
2917 irq_data = irq_domain_get_irq_data(domain, virq);
2921 ioapic = mp_irqdomain_ioapic_idx(domain);
2922 pin = info->ioapic_pin;
2923 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2926 data = kzalloc(sizeof(*data), GFP_KERNEL);
2930 info->ioapic_entry = &data->entry;
2931 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2937 INIT_LIST_HEAD(&data->irq_2_pin);
2938 irq_data->hwirq = info->ioapic_pin;
2939 irq_data->chip = (domain->parent == x86_vector_domain) ?
2940 &ioapic_chip : &ioapic_ir_chip;
2941 irq_data->chip_data = data;
2942 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2944 cfg = irqd_cfg(irq_data);
2945 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2947 local_irq_save(flags);
2948 if (info->ioapic_entry)
2949 mp_setup_entry(cfg, data, info->ioapic_entry);
2950 mp_register_handler(virq, data->trigger);
2951 if (virq < nr_legacy_irqs())
2952 legacy_pic->mask(virq);
2953 local_irq_restore(flags);
2955 apic_printk(APIC_VERBOSE, KERN_DEBUG
2956 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2957 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2958 virq, data->trigger, data->polarity, cfg->dest_apicid);
2963 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2964 unsigned int nr_irqs)
2966 struct irq_data *irq_data;
2967 struct mp_chip_data *data;
2969 BUG_ON(nr_irqs != 1);
2970 irq_data = irq_domain_get_irq_data(domain, virq);
2971 if (irq_data && irq_data->chip_data) {
2972 data = irq_data->chip_data;
2973 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
2974 (int)irq_data->hwirq);
2975 WARN_ON(!list_empty(&data->irq_2_pin));
2976 kfree(irq_data->chip_data);
2978 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2981 int mp_irqdomain_activate(struct irq_domain *domain,
2982 struct irq_data *irq_data, bool early)
2984 unsigned long flags;
2985 struct irq_pin_list *entry;
2986 struct mp_chip_data *data = irq_data->chip_data;
2988 raw_spin_lock_irqsave(&ioapic_lock, flags);
2989 for_each_irq_pin(entry, data->irq_2_pin)
2990 __ioapic_write_entry(entry->apic, entry->pin, data->entry);
2991 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2995 void mp_irqdomain_deactivate(struct irq_domain *domain,
2996 struct irq_data *irq_data)
2998 /* It won't be called for IRQ with multiple IOAPIC pins associated */
2999 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3000 (int)irq_data->hwirq);
3003 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3005 return (int)(long)domain->host_data;
3008 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3009 .alloc = mp_irqdomain_alloc,
3010 .free = mp_irqdomain_free,
3011 .activate = mp_irqdomain_activate,
3012 .deactivate = mp_irqdomain_deactivate,