1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC handling, local APIC timers
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
15 * Mikael Pettersson : PM converted to driver model.
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/memblock.h>
25 #include <linux/ftrace.h>
26 #include <linux/ioport.h>
27 #include <linux/export.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/delay.h>
30 #include <linux/timex.h>
31 #include <linux/i8253.h>
32 #include <linux/dmar.h>
33 #include <linux/init.h>
34 #include <linux/cpu.h>
35 #include <linux/dmi.h>
36 #include <linux/smp.h>
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <asm/pgalloc.h>
44 #include <linux/atomic.h>
45 #include <asm/mpspec.h>
46 #include <asm/i8259.h>
47 #include <asm/proto.h>
48 #include <asm/traps.h>
50 #include <asm/io_apic.h>
58 #include <asm/hypervisor.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/intel-family.h>
61 #include <asm/irq_regs.h>
63 unsigned int num_processors;
65 unsigned disabled_cpus;
67 /* Processor that is doing the boot up */
68 unsigned int boot_cpu_physical_apicid = -1U;
69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
71 u8 boot_cpu_apic_version;
74 * The highest APIC ID seen during enumeration.
76 static unsigned int max_physical_apicid;
79 * Bitmask of physically existing CPUs:
81 physid_mask_t phys_cpu_present_map;
84 * Processor to be disabled specified by kernel parameter
85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
86 * avoid undefined behaviour caused by sending INIT from AP to BSP.
88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
91 * This variable controls which CPUs receive external NMIs. By default,
92 * external NMIs are delivered only to the BSP.
94 static int apic_extnmi = APIC_EXTNMI_BSP;
97 * Map cpu index to physical APIC ID
99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
109 * On x86_32, the mapping between cpu and logical apicid may vary
110 * depending on apic in use. The following early percpu variable is
111 * used for the mapping. This is where the behaviors of x86_64 and 32
112 * actually diverge. Let's keep it ugly for now.
114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
116 /* Local APIC was disabled by the BIOS and enabled by the kernel */
117 static int enabled_via_apicbase;
120 * Handle interrupt mode configuration register (IMCR).
121 * This register controls whether the interrupt signals
122 * that reach the BSP come from the master PIC or from the
123 * local APIC. Before entering Symmetric I/O Mode, either
124 * the BIOS or the operating system must switch out of
125 * PIC Mode by changing the IMCR.
127 static inline void imcr_pic_to_apic(void)
129 /* select IMCR register */
131 /* NMI and 8259 INTR go through APIC */
135 static inline void imcr_apic_to_pic(void)
137 /* select IMCR register */
139 /* NMI and 8259 INTR go directly to BSP */
145 * Knob to control our willingness to enable the local APIC.
149 static int force_enable_local_apic __initdata;
152 * APIC command line parameters
154 static int __init parse_lapic(char *arg)
156 if (IS_ENABLED(CONFIG_X86_32) && !arg)
157 force_enable_local_apic = 1;
158 else if (arg && !strncmp(arg, "notscdeadline", 13))
159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
162 early_param("lapic", parse_lapic);
165 static int apic_calibrate_pmtmr __initdata;
166 static __init int setup_apicpmtimer(char *s)
168 apic_calibrate_pmtmr = 1;
172 __setup("apicpmtimer", setup_apicpmtimer);
175 unsigned long mp_lapic_addr;
177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
178 static int disable_apic_timer __initdata;
179 /* Local APIC timer works in C2 */
180 int local_apic_timer_c2_ok;
181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
184 * Debug level, exported for io_apic.c
190 /* Have we found an MP table */
191 int smp_found_config;
193 static struct resource lapic_resource = {
194 .name = "Local APIC",
195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
198 unsigned int lapic_timer_period = 0;
200 static void apic_pm_activate(void);
202 static unsigned long apic_phys;
205 * Get the LAPIC version
207 static inline int lapic_get_version(void)
209 return GET_APIC_VERSION(apic_read(APIC_LVR));
213 * Check, if the APIC is integrated or a separate chip
215 static inline int lapic_is_integrated(void)
217 return APIC_INTEGRATED(lapic_get_version());
221 * Check, whether this is a modern or a first generation APIC
223 static int modern_apic(void)
225 /* AMD systems use old APIC versions, so check the CPU */
226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
227 boot_cpu_data.x86 >= 0xf)
230 /* Hygon systems use modern APIC */
231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 static void __init apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
253 u32 native_safe_apic_wait_icr_idle(void)
260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
263 inc_irq_stat(icr_read_retry_count);
265 } while (timeout++ < 1000);
270 void native_apic_icr_write(u32 low, u32 id)
274 local_irq_save(flags);
275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
276 apic_write(APIC_ICR, low);
277 local_irq_restore(flags);
280 u64 native_apic_icr_read(void)
284 icr2 = apic_read(APIC_ICR2);
285 icr1 = apic_read(APIC_ICR);
287 return icr1 | ((u64)icr2 << 32);
292 * get_physical_broadcast - Get number of physical broadcast IDs
294 int get_physical_broadcast(void)
296 return modern_apic() ? 0xff : 0xf;
301 * lapic_get_maxlvt - get the maximum number of local vector table entries
303 int lapic_get_maxlvt(void)
306 * - we always have APIC integrated on 64bit mode
307 * - 82489DXs do not report # of LVT entries
309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
317 #define APIC_DIVISOR 16
318 #define TSC_DIVISOR 8
321 * This function sets up the local APIC timer, with a timeout of
322 * 'clocks' APIC bus clock. During calibration we actually call
323 * this function twice on the boot CPU, once with a bogus timeout
324 * value, second time for real. The other (noncalibrating) CPUs
325 * call this function only once, with the real, calibrated value.
327 * We do reads before writes even if unnecessary, to get around the
328 * P5 APIC double write bug.
330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
332 unsigned int lvtt_value, tmp_value;
334 lvtt_value = LOCAL_TIMER_VECTOR;
336 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
340 if (!lapic_is_integrated())
341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
344 lvtt_value |= APIC_LVT_MASKED;
346 apic_write(APIC_LVTT, lvtt_value);
348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
352 * According to Intel, MFENCE can do the serialization here.
354 asm volatile("mfence" : : : "memory");
356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
363 tmp_value = apic_read(APIC_TDCR);
364 apic_write(APIC_TDCR,
365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
373 * Setup extended LVT, AMD specific
375 * Software should use the LVT offsets the BIOS provides. The offsets
376 * are determined by the subsystems using it like those for MCE
377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
378 * are supported. Beginning with family 10h at least 4 offsets are
381 * Since the offsets must be consistent for all cores, we keep track
382 * of the LVT offsets in software and reserve the offset for the same
383 * vector also to be used on other cores. An offset is freed by
384 * setting the entry to APIC_EILVT_MASKED.
386 * If the BIOS is right, there should be no conflicts. Otherwise a
387 * "[Firmware Bug]: ..." error message is generated. However, if
388 * software does not properly determines the offsets, it is not
389 * necessarily a BIOS bug.
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 return (old & APIC_EILVT_MASKED)
397 || (new == APIC_EILVT_MASKED)
398 || ((new & ~APIC_EILVT_MASKED) == old);
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 unsigned int rsvd, vector;
405 if (offset >= APIC_EILVT_NR_MAX)
408 rsvd = atomic_read(&eilvt_offsets[offset]);
410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
411 if (vector && !eilvt_entry_is_changeable(vector, new))
412 /* may not change if vectors are different */
414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 } while (rsvd != new);
417 rsvd &= ~APIC_EILVT_MASKED;
418 if (rsvd && rsvd != vector)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
433 unsigned long reg = APIC_EILVTn(offset);
434 unsigned int new, old, reserved;
436 new = (mask << 16) | (msg_type << 8) | vector;
437 old = apic_read(reg);
438 reserved = reserve_eilvt_offset(offset, new);
440 if (reserved != new) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg, offset, new, reserved);
448 if (!eilvt_entry_is_changeable(old, new)) {
449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg, offset, new, old);
456 apic_write(reg, new);
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
463 * Program the next event, relative to now
465 static int lapic_next_event(unsigned long delta,
466 struct clock_event_device *evt)
468 apic_write(APIC_TMICT, delta);
472 static int lapic_next_deadline(unsigned long delta,
473 struct clock_event_device *evt)
478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
482 static int lapic_timer_shutdown(struct clock_event_device *evt)
486 /* Lapic used as dummy for broadcast ? */
487 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
490 v = apic_read(APIC_LVTT);
491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
492 apic_write(APIC_LVTT, v);
493 apic_write(APIC_TMICT, 0);
498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
500 /* Lapic used as dummy for broadcast ? */
501 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
508 static int lapic_timer_set_periodic(struct clock_event_device *evt)
510 return lapic_timer_set_periodic_oneshot(evt, false);
513 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
515 return lapic_timer_set_periodic_oneshot(evt, true);
519 * Local APIC timer broadcast function
521 static void lapic_timer_broadcast(const struct cpumask *mask)
524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
530 * The local apic timer can be used for any function which is CPU local.
532 static struct clock_event_device lapic_clockevent = {
534 .features = CLOCK_EVT_FEAT_PERIODIC |
535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
536 | CLOCK_EVT_FEAT_DUMMY,
538 .set_state_shutdown = lapic_timer_shutdown,
539 .set_state_periodic = lapic_timer_set_periodic,
540 .set_state_oneshot = lapic_timer_set_oneshot,
541 .set_state_oneshot_stopped = lapic_timer_shutdown,
542 .set_next_event = lapic_next_event,
543 .broadcast = lapic_timer_broadcast,
547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
555 static u32 hsx_deadline_rev(void)
557 switch (boot_cpu_data.x86_stepping) {
558 case 0x02: return 0x3a; /* EP */
559 case 0x04: return 0x0f; /* EX */
565 static u32 bdx_deadline_rev(void)
567 switch (boot_cpu_data.x86_stepping) {
568 case 0x02: return 0x00000011;
569 case 0x03: return 0x0700000e;
570 case 0x04: return 0x0f00000c;
571 case 0x05: return 0x0e000003;
577 static u32 skx_deadline_rev(void)
579 switch (boot_cpu_data.x86_stepping) {
580 case 0x03: return 0x01000136;
581 case 0x04: return 0x02000014;
584 if (boot_cpu_data.x86_stepping > 4)
590 static const struct x86_cpu_id deadline_match[] = {
591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
612 static void apic_check_deadline_errata(void)
614 const struct x86_cpu_id *m;
617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
618 boot_cpu_has(X86_FEATURE_HYPERVISOR))
621 m = x86_match_cpu(deadline_match);
626 * Function pointers will have the MSB set due to address layout,
627 * immediate revisions will not.
629 if ((long)m->driver_data < 0)
630 rev = ((u32 (*)(void))(m->driver_data))();
632 rev = (u32)m->driver_data;
634 if (boot_cpu_data.microcode >= rev)
637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
639 "please update microcode to version: 0x%x (or later)\n", rev);
643 * Setup the local APIC timer for this CPU. Copy the initialized values
644 * of the boot CPU and register the clock event in the framework.
646 static void setup_APIC_timer(void)
648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
650 if (this_cpu_has(X86_FEATURE_ARAT)) {
651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
652 /* Make LAPIC timer preferrable over percpu HPET */
653 lapic_clockevent.rating = 150;
656 memcpy(levt, &lapic_clockevent, sizeof(*levt));
657 levt->cpumask = cpumask_of(smp_processor_id());
659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
660 levt->name = "lapic-deadline";
661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
662 CLOCK_EVT_FEAT_DUMMY);
663 levt->set_next_event = lapic_next_deadline;
664 clockevents_config_and_register(levt,
665 tsc_khz * (1000 / TSC_DIVISOR),
668 clockevents_register_device(levt);
672 * Install the updated TSC frequency from recalibration at the TSC
673 * deadline clockevent devices.
675 static void __lapic_update_tsc_freq(void *info)
677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
685 void lapic_update_tsc_freq(void)
688 * The clockevent device's ->mult and ->shift can both be
689 * changed. In order to avoid races, schedule the frequency
690 * update code on each CPU.
692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
696 * In this functions we calibrate APIC bus clocks to the external timer.
698 * We want to do the calibration only once since we want to have local timer
699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
702 * This was previously done by reading the PIT/HPET and waiting for a wrap
703 * around to find out, that a tick has elapsed. I have a box, where the PIT
704 * readout is broken, so it never gets out of the wait loop again. This was
705 * also reported by others.
707 * Monitoring the jiffies value is inaccurate and the clockevents
708 * infrastructure allows us to do a simple substitution of the interrupt
711 * The calibration routine also uses the pm_timer when possible, as the PIT
712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
713 * back to normal later in the boot process).
716 #define LAPIC_CAL_LOOPS (HZ/10)
718 static __initdata int lapic_cal_loops = -1;
719 static __initdata long lapic_cal_t1, lapic_cal_t2;
720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
725 * Temporary interrupt handler.
727 static void __init lapic_cal_handler(struct clock_event_device *dev)
729 unsigned long long tsc = 0;
730 long tapic = apic_read(APIC_TMCCT);
731 unsigned long pm = acpi_pm_read_early();
733 if (boot_cpu_has(X86_FEATURE_TSC))
736 switch (lapic_cal_loops++) {
738 lapic_cal_t1 = tapic;
739 lapic_cal_tsc1 = tsc;
741 lapic_cal_j1 = jiffies;
744 case LAPIC_CAL_LOOPS:
745 lapic_cal_t2 = tapic;
746 lapic_cal_tsc2 = tsc;
747 if (pm < lapic_cal_pm1)
748 pm += ACPI_PM_OVRRUN;
750 lapic_cal_j2 = jiffies;
756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
759 const long pm_thresh = pm_100ms / 100;
763 #ifndef CONFIG_X86_PM_TIMER
767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
769 /* Check, if the PM timer is available */
773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
775 if (deltapm > (pm_100ms - pm_thresh) &&
776 deltapm < (pm_100ms + pm_thresh)) {
777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
781 res = (((u64)deltapm) * mult) >> 22;
782 do_div(res, 1000000);
783 pr_warning("APIC calibration not consistent "
784 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
786 /* Correct the lapic counter value */
787 res = (((u64)(*delta)) * pm_100ms);
788 do_div(res, deltapm);
789 pr_info("APIC delta adjusted to PM-Timer: "
790 "%lu (%ld)\n", (unsigned long)res, *delta);
793 /* Correct the tsc counter value */
794 if (boot_cpu_has(X86_FEATURE_TSC)) {
795 res = (((u64)(*deltatsc)) * pm_100ms);
796 do_div(res, deltapm);
797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
798 "PM-Timer: %lu (%ld)\n",
799 (unsigned long)res, *deltatsc);
800 *deltatsc = (long)res;
806 static int __init lapic_init_clockevent(void)
808 if (!lapic_timer_period)
811 /* Calculate the scaled math multiplication factor */
812 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
813 TICK_NSEC, lapic_clockevent.shift);
814 lapic_clockevent.max_delta_ns =
815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
817 lapic_clockevent.min_delta_ns =
818 clockevent_delta2ns(0xF, &lapic_clockevent);
819 lapic_clockevent.min_delta_ticks = 0xF;
824 bool __init apic_needs_pit(void)
827 * If the frequencies are not known, PIT is required for both TSC
828 * and apic timer calibration.
830 if (!tsc_khz || !cpu_khz)
833 /* Is there an APIC at all? */
834 if (!boot_cpu_has(X86_FEATURE_APIC))
837 /* Deadline timer is based on TSC so no further PIT action required */
838 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
841 /* APIC timer disabled? */
842 if (disable_apic_timer)
845 * The APIC timer frequency is known already, no PIT calibration
846 * required. If unknown, let the PIT be initialized.
848 return lapic_timer_period == 0;
851 static int __init calibrate_APIC_clock(void)
853 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
854 void (*real_handler)(struct clock_event_device *dev);
855 unsigned long deltaj;
856 long delta, deltatsc;
857 int pm_referenced = 0;
859 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
863 * Check if lapic timer has already been calibrated by platform
864 * specific routine, such as tsc calibration code. If so just fill
865 * in the clockevent structure and return.
867 if (!lapic_init_clockevent()) {
868 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
871 * Direct calibration methods must have an always running
872 * local APIC timer, no need for broadcast timer.
874 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
878 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
879 "calibrating APIC timer ...\n");
883 /* Replace the global interrupt handler */
884 real_handler = global_clock_event->event_handler;
885 global_clock_event->event_handler = lapic_cal_handler;
888 * Setup the APIC counter to maximum. There is no way the lapic
889 * can underflow in the 100ms detection time frame
891 __setup_APIC_LVTT(0xffffffff, 0, 0);
893 /* Let the interrupts run */
896 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
901 /* Restore the real event handler */
902 global_clock_event->event_handler = real_handler;
904 /* Build delta t1-t2 as apic timer counts down */
905 delta = lapic_cal_t1 - lapic_cal_t2;
906 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
908 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
910 /* we trust the PM based calibration if possible */
911 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
914 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
915 lapic_init_clockevent();
917 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
918 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
919 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
922 if (boot_cpu_has(X86_FEATURE_TSC)) {
923 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
925 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
926 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
929 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
931 lapic_timer_period / (1000000 / HZ),
932 lapic_timer_period % (1000000 / HZ));
935 * Do a sanity check on the APIC calibration result
937 if (lapic_timer_period < (1000000 / HZ)) {
939 pr_warning("APIC frequency too slow, disabling apic timer\n");
943 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
946 * PM timer calibration failed or not turned on
947 * so lets try APIC timer based calibration
949 if (!pm_referenced) {
950 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
953 * Setup the apic timer manually
955 levt->event_handler = lapic_cal_handler;
956 lapic_timer_set_periodic(levt);
957 lapic_cal_loops = -1;
959 /* Let the interrupts run */
962 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
965 /* Stop the lapic timer */
967 lapic_timer_shutdown(levt);
970 deltaj = lapic_cal_j2 - lapic_cal_j1;
971 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
973 /* Check, if the jiffies result is consistent */
974 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
975 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
977 levt->features |= CLOCK_EVT_FEAT_DUMMY;
981 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
982 pr_warning("APIC timer disabled due to verification failure\n");
990 * Setup the boot APIC
992 * Calibrate and verify the result.
994 void __init setup_boot_APIC_clock(void)
997 * The local apic timer can be disabled via the kernel
998 * commandline or from the CPU detection code. Register the lapic
999 * timer as a dummy clock event source on SMP systems, so the
1000 * broadcast mechanism is used. On UP systems simply ignore it.
1002 if (disable_apic_timer) {
1003 pr_info("Disabling APIC timer\n");
1004 /* No broadcast on UP ! */
1005 if (num_possible_cpus() > 1) {
1006 lapic_clockevent.mult = 1;
1012 if (calibrate_APIC_clock()) {
1013 /* No broadcast on UP ! */
1014 if (num_possible_cpus() > 1)
1020 * If nmi_watchdog is set to IO_APIC, we need the
1021 * PIT/HPET going. Otherwise register lapic as a dummy
1024 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1026 /* Setup the lapic or request the broadcast */
1028 amd_e400_c1e_apic_setup();
1031 void setup_secondary_APIC_clock(void)
1034 amd_e400_c1e_apic_setup();
1038 * The guts of the apic timer interrupt
1040 static void local_apic_timer_interrupt(void)
1042 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1045 * Normally we should not be here till LAPIC has been initialized but
1046 * in some cases like kdump, its possible that there is a pending LAPIC
1047 * timer interrupt from previous kernel's context and is delivered in
1048 * new kernel the moment interrupts are enabled.
1050 * Interrupts are enabled early and LAPIC is setup much later, hence
1051 * its possible that when we get here evt->event_handler is NULL.
1052 * Check for event_handler being NULL and discard the interrupt as
1055 if (!evt->event_handler) {
1056 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1057 smp_processor_id());
1059 lapic_timer_shutdown(evt);
1064 * the NMI deadlock-detector uses this.
1066 inc_irq_stat(apic_timer_irqs);
1068 evt->event_handler(evt);
1072 * Local APIC timer interrupt. This is the most natural way for doing
1073 * local interrupts, but local timer interrupts can be emulated by
1074 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1076 * [ if a single-CPU system runs an SMP kernel then we call the local
1077 * interrupt as well. Thus we cannot inline the local irq ... ]
1079 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1081 struct pt_regs *old_regs = set_irq_regs(regs);
1084 * NOTE! We'd better ACK the irq immediately,
1085 * because timer handling can be slow.
1087 * update_process_times() expects us to have done irq_enter().
1088 * Besides, if we don't timer interrupts ignore the global
1089 * interrupt lock, which is the WrongThing (tm) to do.
1092 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1093 local_apic_timer_interrupt();
1094 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1097 set_irq_regs(old_regs);
1100 int setup_profiling_timer(unsigned int multiplier)
1106 * Local APIC start and shutdown
1110 * clear_local_APIC - shutdown the local APIC
1112 * This is called, when a CPU is disabled and before rebooting, so the state of
1113 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1114 * leftovers during boot.
1116 void clear_local_APIC(void)
1121 /* APIC hasn't been mapped yet */
1122 if (!x2apic_mode && !apic_phys)
1125 maxlvt = lapic_get_maxlvt();
1127 * Masking an LVT entry can trigger a local APIC error
1128 * if the vector is zero. Mask LVTERR first to prevent this.
1131 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1132 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1135 * Careful: we have to set masks only first to deassert
1136 * any level-triggered sources.
1138 v = apic_read(APIC_LVTT);
1139 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1140 v = apic_read(APIC_LVT0);
1141 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1142 v = apic_read(APIC_LVT1);
1143 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1145 v = apic_read(APIC_LVTPC);
1146 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1149 /* lets not touch this if we didn't frob it */
1150 #ifdef CONFIG_X86_THERMAL_VECTOR
1152 v = apic_read(APIC_LVTTHMR);
1153 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1156 #ifdef CONFIG_X86_MCE_INTEL
1158 v = apic_read(APIC_LVTCMCI);
1159 if (!(v & APIC_LVT_MASKED))
1160 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1165 * Clean APIC state for other OSs:
1167 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1168 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1169 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1171 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1173 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1175 /* Integrated APIC (!82489DX) ? */
1176 if (lapic_is_integrated()) {
1178 /* Clear ESR due to Pentium errata 3AP and 11AP */
1179 apic_write(APIC_ESR, 0);
1180 apic_read(APIC_ESR);
1185 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1187 * Contrary to disable_local_APIC() this does not touch the enable bit in
1188 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1189 * bus would require a hardware reset as the APIC would lose track of bus
1190 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1191 * but it has to be guaranteed that no interrupt is sent to the APIC while
1192 * in that state and it's not clear from the SDM whether it still responds
1193 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1195 void apic_soft_disable(void)
1201 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1202 value = apic_read(APIC_SPIV);
1203 value &= ~APIC_SPIV_APIC_ENABLED;
1204 apic_write(APIC_SPIV, value);
1208 * disable_local_APIC - clear and disable the local APIC
1210 void disable_local_APIC(void)
1212 /* APIC hasn't been mapped yet */
1213 if (!x2apic_mode && !apic_phys)
1216 apic_soft_disable();
1218 #ifdef CONFIG_X86_32
1220 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1221 * restore the disabled state.
1223 if (enabled_via_apicbase) {
1226 rdmsr(MSR_IA32_APICBASE, l, h);
1227 l &= ~MSR_IA32_APICBASE_ENABLE;
1228 wrmsr(MSR_IA32_APICBASE, l, h);
1234 * If Linux enabled the LAPIC against the BIOS default disable it down before
1235 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1236 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1237 * for the case where Linux didn't enable the LAPIC.
1239 void lapic_shutdown(void)
1241 unsigned long flags;
1243 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1246 local_irq_save(flags);
1248 #ifdef CONFIG_X86_32
1249 if (!enabled_via_apicbase)
1253 disable_local_APIC();
1256 local_irq_restore(flags);
1260 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1262 void __init sync_Arb_IDs(void)
1265 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1268 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1274 apic_wait_icr_idle();
1276 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1277 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1278 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1281 enum apic_intr_mode_id apic_intr_mode;
1283 static int __init apic_intr_mode_select(void)
1285 /* Check kernel option */
1287 pr_info("APIC disabled via kernel command line\n");
1292 #ifdef CONFIG_X86_64
1293 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1294 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1296 pr_info("APIC disabled by BIOS\n");
1300 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1302 /* Neither 82489DX nor integrated APIC ? */
1303 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1308 /* If the BIOS pretends there is an integrated APIC ? */
1309 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1310 APIC_INTEGRATED(boot_cpu_apic_version)) {
1312 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1313 boot_cpu_physical_apicid);
1318 /* Check MP table or ACPI MADT configuration */
1319 if (!smp_found_config) {
1320 disable_ioapic_support();
1322 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1323 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1325 return APIC_VIRTUAL_WIRE;
1329 /* If SMP should be disabled, then really disable it! */
1330 if (!setup_max_cpus) {
1331 pr_info("APIC: SMP mode deactivated\n");
1332 return APIC_SYMMETRIC_IO_NO_ROUTING;
1335 if (read_apic_id() != boot_cpu_physical_apicid) {
1336 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1337 read_apic_id(), boot_cpu_physical_apicid);
1338 /* Or can we switch back to PIC here? */
1342 return APIC_SYMMETRIC_IO;
1346 * An initial setup of the virtual wire mode.
1348 void __init init_bsp_APIC(void)
1353 * Don't do the setup now if we have a SMP BIOS as the
1354 * through-I/O-APIC virtual wire mode might be active.
1356 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1360 * Do not trust the local APIC being empty at bootup.
1367 value = apic_read(APIC_SPIV);
1368 value &= ~APIC_VECTOR_MASK;
1369 value |= APIC_SPIV_APIC_ENABLED;
1371 #ifdef CONFIG_X86_32
1372 /* This bit is reserved on P4/Xeon and should be cleared */
1373 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1374 (boot_cpu_data.x86 == 15))
1375 value &= ~APIC_SPIV_FOCUS_DISABLED;
1378 value |= APIC_SPIV_FOCUS_DISABLED;
1379 value |= SPURIOUS_APIC_VECTOR;
1380 apic_write(APIC_SPIV, value);
1383 * Set up the virtual wire mode.
1385 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1386 value = APIC_DM_NMI;
1387 if (!lapic_is_integrated()) /* 82489DX */
1388 value |= APIC_LVT_LEVEL_TRIGGER;
1389 if (apic_extnmi == APIC_EXTNMI_NONE)
1390 value |= APIC_LVT_MASKED;
1391 apic_write(APIC_LVT1, value);
1394 static void __init apic_bsp_setup(bool upmode);
1396 /* Init the interrupt delivery mode for the BSP */
1397 void __init apic_intr_mode_init(void)
1399 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1401 apic_intr_mode = apic_intr_mode_select();
1403 switch (apic_intr_mode) {
1405 pr_info("APIC: Keep in PIC mode(8259)\n");
1407 case APIC_VIRTUAL_WIRE:
1408 pr_info("APIC: Switch to virtual wire mode setup\n");
1409 default_setup_apic_routing();
1411 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1412 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1414 default_setup_apic_routing();
1416 case APIC_SYMMETRIC_IO:
1417 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1418 default_setup_apic_routing();
1420 case APIC_SYMMETRIC_IO_NO_ROUTING:
1421 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1425 apic_bsp_setup(upmode);
1428 static void lapic_setup_esr(void)
1430 unsigned int oldvalue, value, maxlvt;
1432 if (!lapic_is_integrated()) {
1433 pr_info("No ESR for 82489DX.\n");
1437 if (apic->disable_esr) {
1439 * Something untraceable is creating bad interrupts on
1440 * secondary quads ... for the moment, just leave the
1441 * ESR disabled - we can't do anything useful with the
1442 * errors anyway - mbligh
1444 pr_info("Leaving ESR disabled.\n");
1448 maxlvt = lapic_get_maxlvt();
1449 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1450 apic_write(APIC_ESR, 0);
1451 oldvalue = apic_read(APIC_ESR);
1453 /* enables sending errors */
1454 value = ERROR_APIC_VECTOR;
1455 apic_write(APIC_LVTERR, value);
1458 * spec says clear errors after enabling vector.
1461 apic_write(APIC_ESR, 0);
1462 value = apic_read(APIC_ESR);
1463 if (value != oldvalue)
1464 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1465 "vector: 0x%08x after: 0x%08x\n",
1469 #define APIC_IR_REGS APIC_ISR_NR
1470 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1471 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1474 unsigned long map[APIC_IR_MAPSIZE];
1475 u32 regs[APIC_IR_REGS];
1478 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1483 for (i = 0; i < APIC_IR_REGS; i++)
1484 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1487 for (i = 0; i < APIC_IR_REGS; i++)
1488 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1491 * If the ISR map is not empty. ACK the APIC and run another round
1492 * to verify whether a pending IRR has been unblocked and turned
1495 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1497 * There can be multiple ISR bits set when a high priority
1498 * interrupt preempted a lower priority one. Issue an ACK
1501 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1506 return !bitmap_empty(irr->map, APIC_IR_BITS);
1510 * After a crash, we no longer service the interrupts and a pending
1511 * interrupt from previous kernel might still have ISR bit set.
1513 * Most probably by now the CPU has serviced that pending interrupt and it
1514 * might not have done the ack_APIC_irq() because it thought, interrupt
1515 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1516 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1517 * a vector might get locked. It was noticed for timer irq (vector
1518 * 0x31). Issue an extra EOI to clear ISR.
1520 * If there are pending IRR bits they turn into ISR bits after a higher
1521 * priority ISR bit has been acked.
1523 static void apic_pending_intr_clear(void)
1525 union apic_ir irr, isr;
1528 /* 512 loops are way oversized and give the APIC a chance to obey. */
1529 for (i = 0; i < 512; i++) {
1530 if (!apic_check_and_ack(&irr, &isr))
1533 /* Dump the IRR/ISR content if that failed */
1534 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1538 * setup_local_APIC - setup the local APIC
1540 * Used to setup local APIC while initializing BSP or bringing up APs.
1541 * Always called with preemption disabled.
1543 static void setup_local_APIC(void)
1545 int cpu = smp_processor_id();
1547 #ifdef CONFIG_X86_32
1548 int logical_apicid, ldr_apicid;
1552 disable_ioapic_support();
1557 * If this comes from kexec/kcrash the APIC might be enabled in
1558 * SPIV. Soft disable it before doing further initialization.
1560 value = apic_read(APIC_SPIV);
1561 value &= ~APIC_SPIV_APIC_ENABLED;
1562 apic_write(APIC_SPIV, value);
1564 #ifdef CONFIG_X86_32
1565 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1566 if (lapic_is_integrated() && apic->disable_esr) {
1567 apic_write(APIC_ESR, 0);
1568 apic_write(APIC_ESR, 0);
1569 apic_write(APIC_ESR, 0);
1570 apic_write(APIC_ESR, 0);
1574 * Double-check whether this APIC is really registered.
1575 * This is meaningless in clustered apic mode, so we skip it.
1577 BUG_ON(!apic->apic_id_registered());
1580 * Intel recommends to set DFR, LDR and TPR before enabling
1581 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1582 * document number 292116). So here it goes...
1584 apic->init_apic_ldr();
1586 #ifdef CONFIG_X86_32
1588 * APIC LDR is initialized. If logical_apicid mapping was
1589 * initialized during get_smp_config(), make sure it matches the
1592 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1593 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1594 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
1595 /* always use the value from LDR */
1596 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1600 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1601 * vector in the 16-31 range could be delivered if TPR == 0, but we
1602 * would think it's an exception and terrible things will happen. We
1603 * never change this later on.
1605 value = apic_read(APIC_TASKPRI);
1606 value &= ~APIC_TPRI_MASK;
1608 apic_write(APIC_TASKPRI, value);
1610 /* Clear eventually stale ISR/IRR bits */
1611 apic_pending_intr_clear();
1614 * Now that we are all set up, enable the APIC
1616 value = apic_read(APIC_SPIV);
1617 value &= ~APIC_VECTOR_MASK;
1621 value |= APIC_SPIV_APIC_ENABLED;
1623 #ifdef CONFIG_X86_32
1625 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1626 * certain networking cards. If high frequency interrupts are
1627 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1628 * entry is masked/unmasked at a high rate as well then sooner or
1629 * later IOAPIC line gets 'stuck', no more interrupts are received
1630 * from the device. If focus CPU is disabled then the hang goes
1633 * [ This bug can be reproduced easily with a level-triggered
1634 * PCI Ne2000 networking cards and PII/PIII processors, dual
1638 * Actually disabling the focus CPU check just makes the hang less
1639 * frequent as it makes the interrupt distributon model be more
1640 * like LRU than MRU (the short-term load is more even across CPUs).
1644 * - enable focus processor (bit==0)
1645 * - 64bit mode always use processor focus
1646 * so no need to set it
1648 value &= ~APIC_SPIV_FOCUS_DISABLED;
1652 * Set spurious IRQ vector
1654 value |= SPURIOUS_APIC_VECTOR;
1655 apic_write(APIC_SPIV, value);
1657 perf_events_lapic_init();
1660 * Set up LVT0, LVT1:
1662 * set up through-local-APIC on the boot CPU's LINT0. This is not
1663 * strictly necessary in pure symmetric-IO mode, but sometimes
1664 * we delegate interrupts to the 8259A.
1667 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1669 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1670 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1671 value = APIC_DM_EXTINT;
1672 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1674 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1675 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1677 apic_write(APIC_LVT0, value);
1680 * Only the BSP sees the LINT1 NMI signal by default. This can be
1681 * modified by apic_extnmi= boot option.
1683 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1684 apic_extnmi == APIC_EXTNMI_ALL)
1685 value = APIC_DM_NMI;
1687 value = APIC_DM_NMI | APIC_LVT_MASKED;
1690 if (!lapic_is_integrated())
1691 value |= APIC_LVT_LEVEL_TRIGGER;
1692 apic_write(APIC_LVT1, value);
1694 #ifdef CONFIG_X86_MCE_INTEL
1695 /* Recheck CMCI information after local APIC is up on CPU #0 */
1701 static void end_local_APIC_setup(void)
1705 #ifdef CONFIG_X86_32
1708 /* Disable the local apic timer */
1709 value = apic_read(APIC_LVTT);
1710 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1711 apic_write(APIC_LVTT, value);
1719 * APIC setup function for application processors. Called from smpboot.c
1721 void apic_ap_setup(void)
1724 end_local_APIC_setup();
1727 #ifdef CONFIG_X86_X2APIC
1735 static int x2apic_state;
1737 static void __x2apic_disable(void)
1741 if (!boot_cpu_has(X86_FEATURE_APIC))
1744 rdmsrl(MSR_IA32_APICBASE, msr);
1745 if (!(msr & X2APIC_ENABLE))
1747 /* Disable xapic and x2apic first and then reenable xapic mode */
1748 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1749 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1750 printk_once(KERN_INFO "x2apic disabled\n");
1753 static void __x2apic_enable(void)
1757 rdmsrl(MSR_IA32_APICBASE, msr);
1758 if (msr & X2APIC_ENABLE)
1760 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1761 printk_once(KERN_INFO "x2apic enabled\n");
1764 static int __init setup_nox2apic(char *str)
1766 if (x2apic_enabled()) {
1767 int apicid = native_apic_msr_read(APIC_ID);
1769 if (apicid >= 255) {
1770 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1774 pr_warning("x2apic already enabled.\n");
1777 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1778 x2apic_state = X2APIC_DISABLED;
1782 early_param("nox2apic", setup_nox2apic);
1784 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1785 void x2apic_setup(void)
1788 * If x2apic is not in ON state, disable it if already enabled
1791 if (x2apic_state != X2APIC_ON) {
1798 static __init void x2apic_disable(void)
1800 u32 x2apic_id, state = x2apic_state;
1803 x2apic_state = X2APIC_DISABLED;
1805 if (state != X2APIC_ON)
1808 x2apic_id = read_apic_id();
1809 if (x2apic_id >= 255)
1810 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1813 register_lapic_address(mp_lapic_addr);
1816 static __init void x2apic_enable(void)
1818 if (x2apic_state != X2APIC_OFF)
1822 x2apic_state = X2APIC_ON;
1826 static __init void try_to_enable_x2apic(int remap_mode)
1828 if (x2apic_state == X2APIC_DISABLED)
1831 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1832 /* IR is required if there is APIC ID > 255 even when running
1835 if (max_physical_apicid > 255 ||
1836 !x86_init.hyper.x2apic_available()) {
1837 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1843 * without IR all CPUs can be addressed by IOAPIC/MSI
1844 * only in physical mode
1851 void __init check_x2apic(void)
1853 if (x2apic_enabled()) {
1854 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1856 x2apic_state = X2APIC_ON;
1857 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1858 x2apic_state = X2APIC_DISABLED;
1861 #else /* CONFIG_X86_X2APIC */
1862 static int __init validate_x2apic(void)
1864 if (!apic_is_x2apic_enabled())
1867 * Checkme: Can we simply turn off x2apic here instead of panic?
1869 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1871 early_initcall(validate_x2apic);
1873 static inline void try_to_enable_x2apic(int remap_mode) { }
1874 static inline void __x2apic_enable(void) { }
1875 #endif /* !CONFIG_X86_X2APIC */
1877 void __init enable_IR_x2apic(void)
1879 unsigned long flags;
1882 if (skip_ioapic_setup) {
1883 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1887 ir_stat = irq_remapping_prepare();
1888 if (ir_stat < 0 && !x2apic_supported())
1891 ret = save_ioapic_entries();
1893 pr_info("Saving IO-APIC state failed: %d\n", ret);
1897 local_irq_save(flags);
1898 legacy_pic->mask_all();
1899 mask_ioapic_entries();
1901 /* If irq_remapping_prepare() succeeded, try to enable it */
1903 ir_stat = irq_remapping_enable();
1904 /* ir_stat contains the remap mode or an error code */
1905 try_to_enable_x2apic(ir_stat);
1908 restore_ioapic_entries();
1909 legacy_pic->restore_mask();
1910 local_irq_restore(flags);
1913 #ifdef CONFIG_X86_64
1915 * Detect and enable local APICs on non-SMP boards.
1916 * Original code written by Keir Fraser.
1917 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1918 * not correctly set up (usually the APIC timer won't work etc.)
1920 static int __init detect_init_APIC(void)
1922 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1923 pr_info("No local APIC present\n");
1927 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1932 static int __init apic_verify(void)
1937 * The APIC feature bit should now be enabled
1940 features = cpuid_edx(1);
1941 if (!(features & (1 << X86_FEATURE_APIC))) {
1942 pr_warning("Could not enable APIC!\n");
1945 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1946 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1948 /* The BIOS may have set up the APIC at some other address */
1949 if (boot_cpu_data.x86 >= 6) {
1950 rdmsr(MSR_IA32_APICBASE, l, h);
1951 if (l & MSR_IA32_APICBASE_ENABLE)
1952 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1955 pr_info("Found and enabled local APIC!\n");
1959 int __init apic_force_enable(unsigned long addr)
1967 * Some BIOSes disable the local APIC in the APIC_BASE
1968 * MSR. This can only be done in software for Intel P6 or later
1969 * and AMD K7 (Model > 1) or later.
1971 if (boot_cpu_data.x86 >= 6) {
1972 rdmsr(MSR_IA32_APICBASE, l, h);
1973 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1974 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1975 l &= ~MSR_IA32_APICBASE_BASE;
1976 l |= MSR_IA32_APICBASE_ENABLE | addr;
1977 wrmsr(MSR_IA32_APICBASE, l, h);
1978 enabled_via_apicbase = 1;
1981 return apic_verify();
1985 * Detect and initialize APIC
1987 static int __init detect_init_APIC(void)
1989 /* Disabled by kernel option? */
1993 switch (boot_cpu_data.x86_vendor) {
1994 case X86_VENDOR_AMD:
1995 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1996 (boot_cpu_data.x86 >= 15))
1999 case X86_VENDOR_HYGON:
2001 case X86_VENDOR_INTEL:
2002 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2003 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2010 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2012 * Over-ride BIOS and try to enable the local APIC only if
2013 * "lapic" specified.
2015 if (!force_enable_local_apic) {
2016 pr_info("Local APIC disabled by BIOS -- "
2017 "you can enable it with \"lapic\"\n");
2020 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2032 pr_info("No local APIC present or hardware disabled\n");
2038 * init_apic_mappings - initialize APIC mappings
2040 void __init init_apic_mappings(void)
2042 unsigned int new_apicid;
2044 apic_check_deadline_errata();
2047 boot_cpu_physical_apicid = read_apic_id();
2051 /* If no local APIC can be found return early */
2052 if (!smp_found_config && detect_init_APIC()) {
2053 /* lets NOP'ify apic operations */
2054 pr_info("APIC: disable apic facility\n");
2057 apic_phys = mp_lapic_addr;
2060 * If the system has ACPI MADT tables or MP info, the LAPIC
2061 * address is already registered.
2063 if (!acpi_lapic && !smp_found_config)
2064 register_lapic_address(apic_phys);
2068 * Fetch the APIC ID of the BSP in case we have a
2069 * default configuration (or the MP table is broken).
2071 new_apicid = read_apic_id();
2072 if (boot_cpu_physical_apicid != new_apicid) {
2073 boot_cpu_physical_apicid = new_apicid;
2075 * yeah -- we lie about apic_version
2076 * in case if apic was disabled via boot option
2077 * but it's not a problem for SMP compiled kernel
2078 * since apic_intr_mode_select is prepared for such
2079 * a case and disable smp mode
2081 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2085 void __init register_lapic_address(unsigned long address)
2087 mp_lapic_addr = address;
2090 set_fixmap_nocache(FIX_APIC_BASE, address);
2091 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2092 APIC_BASE, address);
2094 if (boot_cpu_physical_apicid == -1U) {
2095 boot_cpu_physical_apicid = read_apic_id();
2096 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2101 * Local APIC interrupts
2105 * This interrupt should _never_ happen with our APIC/SMP architecture
2107 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2109 u8 vector = ~regs->orig_ax;
2113 trace_spurious_apic_entry(vector);
2115 inc_irq_stat(irq_spurious_count);
2118 * If this is a spurious interrupt then do not acknowledge
2120 if (vector == SPURIOUS_APIC_VECTOR) {
2122 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2123 smp_processor_id());
2128 * If it is a vectored one, verify it's set in the ISR. If set,
2131 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2132 if (v & (1 << (vector & 0x1f))) {
2133 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2134 vector, smp_processor_id());
2137 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2138 vector, smp_processor_id());
2141 trace_spurious_apic_exit(vector);
2146 * This interrupt should never happen with our APIC/SMP architecture
2148 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2150 static const char * const error_interrupt_reason[] = {
2151 "Send CS error", /* APIC Error Bit 0 */
2152 "Receive CS error", /* APIC Error Bit 1 */
2153 "Send accept error", /* APIC Error Bit 2 */
2154 "Receive accept error", /* APIC Error Bit 3 */
2155 "Redirectable IPI", /* APIC Error Bit 4 */
2156 "Send illegal vector", /* APIC Error Bit 5 */
2157 "Received illegal vector", /* APIC Error Bit 6 */
2158 "Illegal register address", /* APIC Error Bit 7 */
2163 trace_error_apic_entry(ERROR_APIC_VECTOR);
2165 /* First tickle the hardware, only then report what went on. -- REW */
2166 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2167 apic_write(APIC_ESR, 0);
2168 v = apic_read(APIC_ESR);
2170 atomic_inc(&irq_err_count);
2172 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2173 smp_processor_id(), v);
2178 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2183 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2185 trace_error_apic_exit(ERROR_APIC_VECTOR);
2190 * connect_bsp_APIC - attach the APIC to the interrupt system
2192 static void __init connect_bsp_APIC(void)
2194 #ifdef CONFIG_X86_32
2197 * Do not trust the local APIC being empty at bootup.
2201 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2202 * local APIC to INT and NMI lines.
2204 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2205 "enabling APIC mode.\n");
2212 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2213 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2215 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2218 void disconnect_bsp_APIC(int virt_wire_setup)
2222 #ifdef CONFIG_X86_32
2225 * Put the board back into PIC mode (has an effect only on
2226 * certain older boards). Note that APIC interrupts, including
2227 * IPIs, won't work beyond this point! The only exception are
2230 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2231 "entering PIC mode.\n");
2237 /* Go back to Virtual Wire compatibility mode */
2239 /* For the spurious interrupt use vector F, and enable it */
2240 value = apic_read(APIC_SPIV);
2241 value &= ~APIC_VECTOR_MASK;
2242 value |= APIC_SPIV_APIC_ENABLED;
2244 apic_write(APIC_SPIV, value);
2246 if (!virt_wire_setup) {
2248 * For LVT0 make it edge triggered, active high,
2249 * external and enabled
2251 value = apic_read(APIC_LVT0);
2252 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2253 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2254 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2255 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2256 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2257 apic_write(APIC_LVT0, value);
2260 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2264 * For LVT1 make it edge triggered, active high,
2267 value = apic_read(APIC_LVT1);
2268 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2269 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2270 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2271 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2272 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2273 apic_write(APIC_LVT1, value);
2277 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2278 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2279 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2280 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2282 * NOTE: Reserve 0 for BSP.
2284 static int nr_logical_cpuids = 1;
2287 * Used to store mapping between logical CPU IDs and APIC IDs.
2289 static int cpuid_to_apicid[] = {
2290 [0 ... NR_CPUS - 1] = -1,
2295 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2296 * @id: APIC ID to check
2298 bool apic_id_is_primary_thread(unsigned int apicid)
2302 if (smp_num_siblings == 1)
2304 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2305 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2306 return !(apicid & mask);
2311 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2312 * and cpuid_to_apicid[] synchronized.
2314 static int allocate_logical_cpuid(int apicid)
2319 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2320 * check if the kernel has allocated a cpuid for it.
2322 for (i = 0; i < nr_logical_cpuids; i++) {
2323 if (cpuid_to_apicid[i] == apicid)
2327 /* Allocate a new cpuid. */
2328 if (nr_logical_cpuids >= nr_cpu_ids) {
2329 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2330 "Processor %d/0x%x and the rest are ignored.\n",
2331 nr_cpu_ids, nr_logical_cpuids, apicid);
2335 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2336 return nr_logical_cpuids++;
2339 int generic_processor_info(int apicid, int version)
2341 int cpu, max = nr_cpu_ids;
2342 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2343 phys_cpu_present_map);
2346 * boot_cpu_physical_apicid is designed to have the apicid
2347 * returned by read_apic_id(), i.e, the apicid of the
2348 * currently booting-up processor. However, on some platforms,
2349 * it is temporarily modified by the apicid reported as BSP
2350 * through MP table. Concretely:
2352 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2353 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2355 * This function is executed with the modified
2356 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2357 * parameter doesn't work to disable APs on kdump 2nd kernel.
2359 * Since fixing handling of boot_cpu_physical_apicid requires
2360 * another discussion and tests on each platform, we leave it
2361 * for now and here we use read_apic_id() directly in this
2362 * function, generic_processor_info().
2364 if (disabled_cpu_apicid != BAD_APICID &&
2365 disabled_cpu_apicid != read_apic_id() &&
2366 disabled_cpu_apicid == apicid) {
2367 int thiscpu = num_processors + disabled_cpus;
2369 pr_warning("APIC: Disabling requested cpu."
2370 " Processor %d/0x%x ignored.\n",
2378 * If boot cpu has not been detected yet, then only allow upto
2379 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2381 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2382 apicid != boot_cpu_physical_apicid) {
2383 int thiscpu = max + disabled_cpus - 1;
2386 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2387 " reached. Keeping one slot for boot cpu."
2388 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2394 if (num_processors >= nr_cpu_ids) {
2395 int thiscpu = max + disabled_cpus;
2397 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2398 "reached. Processor %d/0x%x ignored.\n",
2399 max, thiscpu, apicid);
2405 if (apicid == boot_cpu_physical_apicid) {
2407 * x86_bios_cpu_apicid is required to have processors listed
2408 * in same order as logical cpu numbers. Hence the first
2409 * entry is BSP, and so on.
2410 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2415 /* Logical cpuid 0 is reserved for BSP. */
2416 cpuid_to_apicid[0] = apicid;
2418 cpu = allocate_logical_cpuid(apicid);
2428 if (version == 0x0) {
2429 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2434 if (version != boot_cpu_apic_version) {
2435 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2436 boot_cpu_apic_version, cpu, version);
2439 if (apicid > max_physical_apicid)
2440 max_physical_apicid = apicid;
2442 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2443 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2444 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2446 #ifdef CONFIG_X86_32
2447 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2448 apic->x86_32_early_logical_apicid(cpu);
2450 set_cpu_possible(cpu, true);
2451 physid_set(apicid, phys_cpu_present_map);
2452 set_cpu_present(cpu, true);
2458 int hard_smp_processor_id(void)
2460 return read_apic_id();
2464 * Override the generic EOI implementation with an optimized version.
2465 * Only called during early boot when only one CPU is active and with
2466 * interrupts disabled, so we know this does not race with actual APIC driver
2469 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2473 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2474 /* Should happen once for each apic */
2475 WARN_ON((*drv)->eoi_write == eoi_write);
2476 (*drv)->native_eoi_write = (*drv)->eoi_write;
2477 (*drv)->eoi_write = eoi_write;
2481 static void __init apic_bsp_up_setup(void)
2483 #ifdef CONFIG_X86_64
2484 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2487 * Hack: In case of kdump, after a crash, kernel might be booting
2488 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2489 * might be zero if read from MP tables. Get it from LAPIC.
2491 # ifdef CONFIG_CRASH_DUMP
2492 boot_cpu_physical_apicid = read_apic_id();
2495 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2499 * apic_bsp_setup - Setup function for local apic and io-apic
2500 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2502 static void __init apic_bsp_setup(bool upmode)
2506 apic_bsp_up_setup();
2510 end_local_APIC_setup();
2511 irq_remap_enable_fault_handling();
2515 #ifdef CONFIG_UP_LATE_INIT
2516 void __init up_late_init(void)
2518 if (apic_intr_mode == APIC_PIC)
2521 /* Setup local timer */
2522 x86_init.timers.setup_percpu_clockev();
2533 * 'active' is true if the local APIC was enabled by us and
2534 * not the BIOS; this signifies that we are also responsible
2535 * for disabling it before entering apm/acpi suspend
2538 /* r/w apic fields */
2539 unsigned int apic_id;
2540 unsigned int apic_taskpri;
2541 unsigned int apic_ldr;
2542 unsigned int apic_dfr;
2543 unsigned int apic_spiv;
2544 unsigned int apic_lvtt;
2545 unsigned int apic_lvtpc;
2546 unsigned int apic_lvt0;
2547 unsigned int apic_lvt1;
2548 unsigned int apic_lvterr;
2549 unsigned int apic_tmict;
2550 unsigned int apic_tdcr;
2551 unsigned int apic_thmr;
2552 unsigned int apic_cmci;
2555 static int lapic_suspend(void)
2557 unsigned long flags;
2560 if (!apic_pm_state.active)
2563 maxlvt = lapic_get_maxlvt();
2565 apic_pm_state.apic_id = apic_read(APIC_ID);
2566 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2567 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2568 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2569 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2570 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2572 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2573 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2574 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2575 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2576 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2577 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2578 #ifdef CONFIG_X86_THERMAL_VECTOR
2580 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2582 #ifdef CONFIG_X86_MCE_INTEL
2584 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2587 local_irq_save(flags);
2588 disable_local_APIC();
2590 irq_remapping_disable();
2592 local_irq_restore(flags);
2596 static void lapic_resume(void)
2599 unsigned long flags;
2602 if (!apic_pm_state.active)
2605 local_irq_save(flags);
2608 * IO-APIC and PIC have their own resume routines.
2609 * We just mask them here to make sure the interrupt
2610 * subsystem is completely quiet while we enable x2apic
2611 * and interrupt-remapping.
2613 mask_ioapic_entries();
2614 legacy_pic->mask_all();
2620 * Make sure the APICBASE points to the right address
2622 * FIXME! This will be wrong if we ever support suspend on
2623 * SMP! We'll need to do this as part of the CPU restore!
2625 if (boot_cpu_data.x86 >= 6) {
2626 rdmsr(MSR_IA32_APICBASE, l, h);
2627 l &= ~MSR_IA32_APICBASE_BASE;
2628 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2629 wrmsr(MSR_IA32_APICBASE, l, h);
2633 maxlvt = lapic_get_maxlvt();
2634 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2635 apic_write(APIC_ID, apic_pm_state.apic_id);
2636 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2637 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2638 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2639 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2640 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2641 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2642 #ifdef CONFIG_X86_THERMAL_VECTOR
2644 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2646 #ifdef CONFIG_X86_MCE_INTEL
2648 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2651 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2652 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2653 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2654 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2655 apic_write(APIC_ESR, 0);
2656 apic_read(APIC_ESR);
2657 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2658 apic_write(APIC_ESR, 0);
2659 apic_read(APIC_ESR);
2661 irq_remapping_reenable(x2apic_mode);
2663 local_irq_restore(flags);
2667 * This device has no shutdown method - fully functioning local APICs
2668 * are needed on every CPU up until machine_halt/restart/poweroff.
2671 static struct syscore_ops lapic_syscore_ops = {
2672 .resume = lapic_resume,
2673 .suspend = lapic_suspend,
2676 static void apic_pm_activate(void)
2678 apic_pm_state.active = 1;
2681 static int __init init_lapic_sysfs(void)
2683 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2684 if (boot_cpu_has(X86_FEATURE_APIC))
2685 register_syscore_ops(&lapic_syscore_ops);
2690 /* local apic needs to resume before other devices access its registers. */
2691 core_initcall(init_lapic_sysfs);
2693 #else /* CONFIG_PM */
2695 static void apic_pm_activate(void) { }
2697 #endif /* CONFIG_PM */
2699 #ifdef CONFIG_X86_64
2701 static int multi_checked;
2704 static int set_multi(const struct dmi_system_id *d)
2708 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2713 static const struct dmi_system_id multi_dmi_table[] = {
2715 .callback = set_multi,
2716 .ident = "IBM System Summit2",
2718 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2719 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2725 static void dmi_check_multi(void)
2730 dmi_check_system(multi_dmi_table);
2735 * apic_is_clustered_box() -- Check if we can expect good TSC
2737 * Thus far, the major user of this is IBM's Summit2 series:
2738 * Clustered boxes may have unsynced TSC problems if they are
2740 * Use DMI to check them
2742 int apic_is_clustered_box(void)
2750 * APIC command line parameters
2752 static int __init setup_disableapic(char *arg)
2755 setup_clear_cpu_cap(X86_FEATURE_APIC);
2758 early_param("disableapic", setup_disableapic);
2760 /* same as disableapic, for compatibility */
2761 static int __init setup_nolapic(char *arg)
2763 return setup_disableapic(arg);
2765 early_param("nolapic", setup_nolapic);
2767 static int __init parse_lapic_timer_c2_ok(char *arg)
2769 local_apic_timer_c2_ok = 1;
2772 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2774 static int __init parse_disable_apic_timer(char *arg)
2776 disable_apic_timer = 1;
2779 early_param("noapictimer", parse_disable_apic_timer);
2781 static int __init parse_nolapic_timer(char *arg)
2783 disable_apic_timer = 1;
2786 early_param("nolapic_timer", parse_nolapic_timer);
2788 static int __init apic_set_verbosity(char *arg)
2791 #ifdef CONFIG_X86_64
2792 skip_ioapic_setup = 0;
2798 if (strcmp("debug", arg) == 0)
2799 apic_verbosity = APIC_DEBUG;
2800 else if (strcmp("verbose", arg) == 0)
2801 apic_verbosity = APIC_VERBOSE;
2802 #ifdef CONFIG_X86_64
2804 pr_warning("APIC Verbosity level %s not recognised"
2805 " use apic=verbose or apic=debug\n", arg);
2812 early_param("apic", apic_set_verbosity);
2814 static int __init lapic_insert_resource(void)
2819 /* Put local APIC into the resource map. */
2820 lapic_resource.start = apic_phys;
2821 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2822 insert_resource(&iomem_resource, &lapic_resource);
2828 * need call insert after e820__reserve_resources()
2829 * that is using request_resource
2831 late_initcall(lapic_insert_resource);
2833 static int __init apic_set_disabled_cpu_apicid(char *arg)
2835 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2840 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2842 static int __init apic_set_extnmi(char *arg)
2847 if (!strncmp("all", arg, 3))
2848 apic_extnmi = APIC_EXTNMI_ALL;
2849 else if (!strncmp("none", arg, 4))
2850 apic_extnmi = APIC_EXTNMI_NONE;
2851 else if (!strncmp("bsp", arg, 3))
2852 apic_extnmi = APIC_EXTNMI_BSP;
2854 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2860 early_param("apic_extnmi", apic_set_extnmi);