2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
48 #include <asm/io_apic.h>
56 #include <asm/hypervisor.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
60 unsigned int num_processors;
62 unsigned disabled_cpus;
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_physical_apicid = -1U;
66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
68 u8 boot_cpu_apic_version;
71 * The highest APIC ID seen during enumeration.
73 static unsigned int max_physical_apicid;
76 * Bitmask of physically existing CPUs:
78 physid_mask_t phys_cpu_present_map;
81 * Processor to be disabled specified by kernel parameter
82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
83 * avoid undefined behaviour caused by sending INIT from AP to BSP.
85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
88 * This variable controls which CPUs receive external NMIs. By default,
89 * external NMIs are delivered only to the BSP.
91 static int apic_extnmi = APIC_EXTNMI_BSP;
94 * Map cpu index to physical APIC ID
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
106 * On x86_32, the mapping between cpu and logical apicid may vary
107 * depending on apic in use. The following early percpu variable is
108 * used for the mapping. This is where the behaviors of x86_64 and 32
109 * actually diverge. Let's keep it ugly for now.
111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase;
117 * Handle interrupt mode configuration register (IMCR).
118 * This register controls whether the interrupt signals
119 * that reach the BSP come from the master PIC or from the
120 * local APIC. Before entering Symmetric I/O Mode, either
121 * the BIOS or the operating system must switch out of
122 * PIC Mode by changing the IMCR.
124 static inline void imcr_pic_to_apic(void)
126 /* select IMCR register */
128 /* NMI and 8259 INTR go through APIC */
132 static inline void imcr_apic_to_pic(void)
134 /* select IMCR register */
136 /* NMI and 8259 INTR go directly to BSP */
142 * Knob to control our willingness to enable the local APIC.
146 static int force_enable_local_apic __initdata;
149 * APIC command line parameters
151 static int __init parse_lapic(char *arg)
153 if (IS_ENABLED(CONFIG_X86_32) && !arg)
154 force_enable_local_apic = 1;
155 else if (arg && !strncmp(arg, "notscdeadline", 13))
156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
159 early_param("lapic", parse_lapic);
162 static int apic_calibrate_pmtmr __initdata;
163 static __init int setup_apicpmtimer(char *s)
165 apic_calibrate_pmtmr = 1;
169 __setup("apicpmtimer", setup_apicpmtimer);
172 unsigned long mp_lapic_addr;
174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
175 static int disable_apic_timer __initdata;
176 /* Local APIC timer works in C2 */
177 int local_apic_timer_c2_ok;
178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
181 * Debug level, exported for io_apic.c
183 unsigned int apic_verbosity;
187 /* Have we found an MP table */
188 int smp_found_config;
190 static struct resource lapic_resource = {
191 .name = "Local APIC",
192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
195 unsigned int lapic_timer_frequency = 0;
197 static void apic_pm_activate(void);
199 static unsigned long apic_phys;
202 * Get the LAPIC version
204 static inline int lapic_get_version(void)
206 return GET_APIC_VERSION(apic_read(APIC_LVR));
210 * Check, if the APIC is integrated or a separate chip
212 static inline int lapic_is_integrated(void)
214 return APIC_INTEGRATED(lapic_get_version());
218 * Check, whether this is a modern or a first generation APIC
220 static int modern_apic(void)
222 /* AMD systems use old APIC versions, so check the CPU */
223 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
224 boot_cpu_data.x86 >= 0xf)
226 return lapic_get_version() >= 0x14;
230 * right after this call apic become NOOP driven
231 * so apic->write/read doesn't do anything
233 static void __init apic_disable(void)
235 pr_info("APIC: switched to apic NOOP\n");
239 void native_apic_wait_icr_idle(void)
241 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
245 u32 native_safe_apic_wait_icr_idle(void)
252 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
255 inc_irq_stat(icr_read_retry_count);
257 } while (timeout++ < 1000);
262 void native_apic_icr_write(u32 low, u32 id)
266 local_irq_save(flags);
267 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
268 apic_write(APIC_ICR, low);
269 local_irq_restore(flags);
272 u64 native_apic_icr_read(void)
276 icr2 = apic_read(APIC_ICR2);
277 icr1 = apic_read(APIC_ICR);
279 return icr1 | ((u64)icr2 << 32);
284 * get_physical_broadcast - Get number of physical broadcast IDs
286 int get_physical_broadcast(void)
288 return modern_apic() ? 0xff : 0xf;
293 * lapic_get_maxlvt - get the maximum number of local vector table entries
295 int lapic_get_maxlvt(void)
298 * - we always have APIC integrated on 64bit mode
299 * - 82489DXs do not report # of LVT entries
301 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
309 #define APIC_DIVISOR 16
310 #define TSC_DIVISOR 8
313 * This function sets up the local APIC timer, with a timeout of
314 * 'clocks' APIC bus clock. During calibration we actually call
315 * this function twice on the boot CPU, once with a bogus timeout
316 * value, second time for real. The other (noncalibrating) CPUs
317 * call this function only once, with the real, calibrated value.
319 * We do reads before writes even if unnecessary, to get around the
320 * P5 APIC double write bug.
322 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
324 unsigned int lvtt_value, tmp_value;
326 lvtt_value = LOCAL_TIMER_VECTOR;
328 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
329 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
330 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
332 if (!lapic_is_integrated())
333 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
336 lvtt_value |= APIC_LVT_MASKED;
338 apic_write(APIC_LVTT, lvtt_value);
340 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
342 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
343 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
344 * According to Intel, MFENCE can do the serialization here.
346 asm volatile("mfence" : : : "memory");
348 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
355 tmp_value = apic_read(APIC_TDCR);
356 apic_write(APIC_TDCR,
357 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
361 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
365 * Setup extended LVT, AMD specific
367 * Software should use the LVT offsets the BIOS provides. The offsets
368 * are determined by the subsystems using it like those for MCE
369 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
370 * are supported. Beginning with family 10h at least 4 offsets are
373 * Since the offsets must be consistent for all cores, we keep track
374 * of the LVT offsets in software and reserve the offset for the same
375 * vector also to be used on other cores. An offset is freed by
376 * setting the entry to APIC_EILVT_MASKED.
378 * If the BIOS is right, there should be no conflicts. Otherwise a
379 * "[Firmware Bug]: ..." error message is generated. However, if
380 * software does not properly determines the offsets, it is not
381 * necessarily a BIOS bug.
384 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
386 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
388 return (old & APIC_EILVT_MASKED)
389 || (new == APIC_EILVT_MASKED)
390 || ((new & ~APIC_EILVT_MASKED) == old);
393 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
395 unsigned int rsvd, vector;
397 if (offset >= APIC_EILVT_NR_MAX)
400 rsvd = atomic_read(&eilvt_offsets[offset]);
402 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
403 if (vector && !eilvt_entry_is_changeable(vector, new))
404 /* may not change if vectors are different */
406 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
407 } while (rsvd != new);
409 rsvd &= ~APIC_EILVT_MASKED;
410 if (rsvd && rsvd != vector)
411 pr_info("LVT offset %d assigned for vector 0x%02x\n",
418 * If mask=1, the LVT entry does not generate interrupts while mask=0
419 * enables the vector. See also the BKDGs. Must be called with
420 * preemption disabled.
423 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
425 unsigned long reg = APIC_EILVTn(offset);
426 unsigned int new, old, reserved;
428 new = (mask << 16) | (msg_type << 8) | vector;
429 old = apic_read(reg);
430 reserved = reserve_eilvt_offset(offset, new);
432 if (reserved != new) {
433 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
434 "vector 0x%x, but the register is already in use for "
435 "vector 0x%x on another cpu\n",
436 smp_processor_id(), reg, offset, new, reserved);
440 if (!eilvt_entry_is_changeable(old, new)) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on this cpu\n",
444 smp_processor_id(), reg, offset, new, old);
448 apic_write(reg, new);
452 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
455 * Program the next event, relative to now
457 static int lapic_next_event(unsigned long delta,
458 struct clock_event_device *evt)
460 apic_write(APIC_TMICT, delta);
464 static int lapic_next_deadline(unsigned long delta,
465 struct clock_event_device *evt)
470 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
474 static int lapic_timer_shutdown(struct clock_event_device *evt)
478 /* Lapic used as dummy for broadcast ? */
479 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
482 v = apic_read(APIC_LVTT);
483 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
484 apic_write(APIC_LVTT, v);
485 apic_write(APIC_TMICT, 0);
490 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
492 /* Lapic used as dummy for broadcast ? */
493 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
496 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
500 static int lapic_timer_set_periodic(struct clock_event_device *evt)
502 return lapic_timer_set_periodic_oneshot(evt, false);
505 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
507 return lapic_timer_set_periodic_oneshot(evt, true);
511 * Local APIC timer broadcast function
513 static void lapic_timer_broadcast(const struct cpumask *mask)
516 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
522 * The local apic timer can be used for any function which is CPU local.
524 static struct clock_event_device lapic_clockevent = {
526 .features = CLOCK_EVT_FEAT_PERIODIC |
527 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
528 | CLOCK_EVT_FEAT_DUMMY,
530 .set_state_shutdown = lapic_timer_shutdown,
531 .set_state_periodic = lapic_timer_set_periodic,
532 .set_state_oneshot = lapic_timer_set_oneshot,
533 .set_state_oneshot_stopped = lapic_timer_shutdown,
534 .set_next_event = lapic_next_event,
535 .broadcast = lapic_timer_broadcast,
539 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
541 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
542 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
544 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
545 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
547 static u32 hsx_deadline_rev(void)
549 switch (boot_cpu_data.x86_stepping) {
550 case 0x02: return 0x3a; /* EP */
551 case 0x04: return 0x0f; /* EX */
557 static u32 bdx_deadline_rev(void)
559 switch (boot_cpu_data.x86_stepping) {
560 case 0x02: return 0x00000011;
561 case 0x03: return 0x0700000e;
562 case 0x04: return 0x0f00000c;
563 case 0x05: return 0x0e000003;
569 static u32 skx_deadline_rev(void)
571 switch (boot_cpu_data.x86_stepping) {
572 case 0x03: return 0x01000136;
573 case 0x04: return 0x02000014;
579 static const struct x86_cpu_id deadline_match[] = {
580 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
581 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
582 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
583 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev),
585 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
587 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
601 static void apic_check_deadline_errata(void)
603 const struct x86_cpu_id *m;
606 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
607 boot_cpu_has(X86_FEATURE_HYPERVISOR))
610 m = x86_match_cpu(deadline_match);
615 * Function pointers will have the MSB set due to address layout,
616 * immediate revisions will not.
618 if ((long)m->driver_data < 0)
619 rev = ((u32 (*)(void))(m->driver_data))();
621 rev = (u32)m->driver_data;
623 if (boot_cpu_data.microcode >= rev)
626 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
627 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
628 "please update microcode to version: 0x%x (or later)\n", rev);
632 * Setup the local APIC timer for this CPU. Copy the initialized values
633 * of the boot CPU and register the clock event in the framework.
635 static void setup_APIC_timer(void)
637 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
639 if (this_cpu_has(X86_FEATURE_ARAT)) {
640 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
641 /* Make LAPIC timer preferrable over percpu HPET */
642 lapic_clockevent.rating = 150;
645 memcpy(levt, &lapic_clockevent, sizeof(*levt));
646 levt->cpumask = cpumask_of(smp_processor_id());
648 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
649 levt->name = "lapic-deadline";
650 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
651 CLOCK_EVT_FEAT_DUMMY);
652 levt->set_next_event = lapic_next_deadline;
653 clockevents_config_and_register(levt,
654 tsc_khz * (1000 / TSC_DIVISOR),
657 clockevents_register_device(levt);
661 * Install the updated TSC frequency from recalibration at the TSC
662 * deadline clockevent devices.
664 static void __lapic_update_tsc_freq(void *info)
666 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
668 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
671 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
674 void lapic_update_tsc_freq(void)
677 * The clockevent device's ->mult and ->shift can both be
678 * changed. In order to avoid races, schedule the frequency
679 * update code on each CPU.
681 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
685 * In this functions we calibrate APIC bus clocks to the external timer.
687 * We want to do the calibration only once since we want to have local timer
688 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
691 * This was previously done by reading the PIT/HPET and waiting for a wrap
692 * around to find out, that a tick has elapsed. I have a box, where the PIT
693 * readout is broken, so it never gets out of the wait loop again. This was
694 * also reported by others.
696 * Monitoring the jiffies value is inaccurate and the clockevents
697 * infrastructure allows us to do a simple substitution of the interrupt
700 * The calibration routine also uses the pm_timer when possible, as the PIT
701 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
702 * back to normal later in the boot process).
705 #define LAPIC_CAL_LOOPS (HZ/10)
707 static __initdata int lapic_cal_loops = -1;
708 static __initdata long lapic_cal_t1, lapic_cal_t2;
709 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
710 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
711 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
714 * Temporary interrupt handler.
716 static void __init lapic_cal_handler(struct clock_event_device *dev)
718 unsigned long long tsc = 0;
719 long tapic = apic_read(APIC_TMCCT);
720 unsigned long pm = acpi_pm_read_early();
722 if (boot_cpu_has(X86_FEATURE_TSC))
725 switch (lapic_cal_loops++) {
727 lapic_cal_t1 = tapic;
728 lapic_cal_tsc1 = tsc;
730 lapic_cal_j1 = jiffies;
733 case LAPIC_CAL_LOOPS:
734 lapic_cal_t2 = tapic;
735 lapic_cal_tsc2 = tsc;
736 if (pm < lapic_cal_pm1)
737 pm += ACPI_PM_OVRRUN;
739 lapic_cal_j2 = jiffies;
745 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
747 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
748 const long pm_thresh = pm_100ms / 100;
752 #ifndef CONFIG_X86_PM_TIMER
756 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
758 /* Check, if the PM timer is available */
762 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
764 if (deltapm > (pm_100ms - pm_thresh) &&
765 deltapm < (pm_100ms + pm_thresh)) {
766 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
770 res = (((u64)deltapm) * mult) >> 22;
771 do_div(res, 1000000);
772 pr_warning("APIC calibration not consistent "
773 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
775 /* Correct the lapic counter value */
776 res = (((u64)(*delta)) * pm_100ms);
777 do_div(res, deltapm);
778 pr_info("APIC delta adjusted to PM-Timer: "
779 "%lu (%ld)\n", (unsigned long)res, *delta);
782 /* Correct the tsc counter value */
783 if (boot_cpu_has(X86_FEATURE_TSC)) {
784 res = (((u64)(*deltatsc)) * pm_100ms);
785 do_div(res, deltapm);
786 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
787 "PM-Timer: %lu (%ld)\n",
788 (unsigned long)res, *deltatsc);
789 *deltatsc = (long)res;
795 static int __init calibrate_APIC_clock(void)
797 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
798 void (*real_handler)(struct clock_event_device *dev);
799 unsigned long deltaj;
800 long delta, deltatsc;
801 int pm_referenced = 0;
804 * check if lapic timer has already been calibrated by platform
805 * specific routine, such as tsc calibration code. if so, we just fill
806 * in the clockevent structure and return.
809 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
811 } else if (lapic_timer_frequency) {
812 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
813 lapic_timer_frequency);
814 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
815 TICK_NSEC, lapic_clockevent.shift);
816 lapic_clockevent.max_delta_ns =
817 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
818 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
819 lapic_clockevent.min_delta_ns =
820 clockevent_delta2ns(0xF, &lapic_clockevent);
821 lapic_clockevent.min_delta_ticks = 0xF;
822 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
826 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
827 "calibrating APIC timer ...\n");
831 /* Replace the global interrupt handler */
832 real_handler = global_clock_event->event_handler;
833 global_clock_event->event_handler = lapic_cal_handler;
836 * Setup the APIC counter to maximum. There is no way the lapic
837 * can underflow in the 100ms detection time frame
839 __setup_APIC_LVTT(0xffffffff, 0, 0);
841 /* Let the interrupts run */
844 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
849 /* Restore the real event handler */
850 global_clock_event->event_handler = real_handler;
852 /* Build delta t1-t2 as apic timer counts down */
853 delta = lapic_cal_t1 - lapic_cal_t2;
854 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
856 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
858 /* we trust the PM based calibration if possible */
859 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
862 /* Calculate the scaled math multiplication factor */
863 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
864 lapic_clockevent.shift);
865 lapic_clockevent.max_delta_ns =
866 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
867 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
868 lapic_clockevent.min_delta_ns =
869 clockevent_delta2ns(0xF, &lapic_clockevent);
870 lapic_clockevent.min_delta_ticks = 0xF;
872 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
874 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
875 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
876 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
877 lapic_timer_frequency);
879 if (boot_cpu_has(X86_FEATURE_TSC)) {
880 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
882 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
883 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
886 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
888 lapic_timer_frequency / (1000000 / HZ),
889 lapic_timer_frequency % (1000000 / HZ));
892 * Do a sanity check on the APIC calibration result
894 if (lapic_timer_frequency < (1000000 / HZ)) {
896 pr_warning("APIC frequency too slow, disabling apic timer\n");
900 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
903 * PM timer calibration failed or not turned on
904 * so lets try APIC timer based calibration
906 if (!pm_referenced) {
907 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
910 * Setup the apic timer manually
912 levt->event_handler = lapic_cal_handler;
913 lapic_timer_set_periodic(levt);
914 lapic_cal_loops = -1;
916 /* Let the interrupts run */
919 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
922 /* Stop the lapic timer */
924 lapic_timer_shutdown(levt);
927 deltaj = lapic_cal_j2 - lapic_cal_j1;
928 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
930 /* Check, if the jiffies result is consistent */
931 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
932 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
934 levt->features |= CLOCK_EVT_FEAT_DUMMY;
938 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
939 pr_warning("APIC timer disabled due to verification failure\n");
947 * Setup the boot APIC
949 * Calibrate and verify the result.
951 void __init setup_boot_APIC_clock(void)
954 * The local apic timer can be disabled via the kernel
955 * commandline or from the CPU detection code. Register the lapic
956 * timer as a dummy clock event source on SMP systems, so the
957 * broadcast mechanism is used. On UP systems simply ignore it.
959 if (disable_apic_timer) {
960 pr_info("Disabling APIC timer\n");
961 /* No broadcast on UP ! */
962 if (num_possible_cpus() > 1) {
963 lapic_clockevent.mult = 1;
969 if (calibrate_APIC_clock()) {
970 /* No broadcast on UP ! */
971 if (num_possible_cpus() > 1)
977 * If nmi_watchdog is set to IO_APIC, we need the
978 * PIT/HPET going. Otherwise register lapic as a dummy
981 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
983 /* Setup the lapic or request the broadcast */
985 amd_e400_c1e_apic_setup();
988 void setup_secondary_APIC_clock(void)
991 amd_e400_c1e_apic_setup();
995 * The guts of the apic timer interrupt
997 static void local_apic_timer_interrupt(void)
999 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1002 * Normally we should not be here till LAPIC has been initialized but
1003 * in some cases like kdump, its possible that there is a pending LAPIC
1004 * timer interrupt from previous kernel's context and is delivered in
1005 * new kernel the moment interrupts are enabled.
1007 * Interrupts are enabled early and LAPIC is setup much later, hence
1008 * its possible that when we get here evt->event_handler is NULL.
1009 * Check for event_handler being NULL and discard the interrupt as
1012 if (!evt->event_handler) {
1013 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1014 smp_processor_id());
1016 lapic_timer_shutdown(evt);
1021 * the NMI deadlock-detector uses this.
1023 inc_irq_stat(apic_timer_irqs);
1025 evt->event_handler(evt);
1029 * Local APIC timer interrupt. This is the most natural way for doing
1030 * local interrupts, but local timer interrupts can be emulated by
1031 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1033 * [ if a single-CPU system runs an SMP kernel then we call the local
1034 * interrupt as well. Thus we cannot inline the local irq ... ]
1036 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1038 struct pt_regs *old_regs = set_irq_regs(regs);
1041 * NOTE! We'd better ACK the irq immediately,
1042 * because timer handling can be slow.
1044 * update_process_times() expects us to have done irq_enter().
1045 * Besides, if we don't timer interrupts ignore the global
1046 * interrupt lock, which is the WrongThing (tm) to do.
1049 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1050 local_apic_timer_interrupt();
1051 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1054 set_irq_regs(old_regs);
1057 int setup_profiling_timer(unsigned int multiplier)
1063 * Local APIC start and shutdown
1067 * clear_local_APIC - shutdown the local APIC
1069 * This is called, when a CPU is disabled and before rebooting, so the state of
1070 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1071 * leftovers during boot.
1073 void clear_local_APIC(void)
1078 /* APIC hasn't been mapped yet */
1079 if (!x2apic_mode && !apic_phys)
1082 maxlvt = lapic_get_maxlvt();
1084 * Masking an LVT entry can trigger a local APIC error
1085 * if the vector is zero. Mask LVTERR first to prevent this.
1088 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1089 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1092 * Careful: we have to set masks only first to deassert
1093 * any level-triggered sources.
1095 v = apic_read(APIC_LVTT);
1096 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1097 v = apic_read(APIC_LVT0);
1098 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1099 v = apic_read(APIC_LVT1);
1100 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1102 v = apic_read(APIC_LVTPC);
1103 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1106 /* lets not touch this if we didn't frob it */
1107 #ifdef CONFIG_X86_THERMAL_VECTOR
1109 v = apic_read(APIC_LVTTHMR);
1110 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1113 #ifdef CONFIG_X86_MCE_INTEL
1115 v = apic_read(APIC_LVTCMCI);
1116 if (!(v & APIC_LVT_MASKED))
1117 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1122 * Clean APIC state for other OSs:
1124 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1125 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1126 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1128 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1130 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1132 /* Integrated APIC (!82489DX) ? */
1133 if (lapic_is_integrated()) {
1135 /* Clear ESR due to Pentium errata 3AP and 11AP */
1136 apic_write(APIC_ESR, 0);
1137 apic_read(APIC_ESR);
1142 * disable_local_APIC - clear and disable the local APIC
1144 void disable_local_APIC(void)
1148 /* APIC hasn't been mapped yet */
1149 if (!x2apic_mode && !apic_phys)
1155 * Disable APIC (implies clearing of registers
1158 value = apic_read(APIC_SPIV);
1159 value &= ~APIC_SPIV_APIC_ENABLED;
1160 apic_write(APIC_SPIV, value);
1162 #ifdef CONFIG_X86_32
1164 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1165 * restore the disabled state.
1167 if (enabled_via_apicbase) {
1170 rdmsr(MSR_IA32_APICBASE, l, h);
1171 l &= ~MSR_IA32_APICBASE_ENABLE;
1172 wrmsr(MSR_IA32_APICBASE, l, h);
1178 * If Linux enabled the LAPIC against the BIOS default disable it down before
1179 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1180 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1181 * for the case where Linux didn't enable the LAPIC.
1183 void lapic_shutdown(void)
1185 unsigned long flags;
1187 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1190 local_irq_save(flags);
1192 #ifdef CONFIG_X86_32
1193 if (!enabled_via_apicbase)
1197 disable_local_APIC();
1200 local_irq_restore(flags);
1204 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1206 void __init sync_Arb_IDs(void)
1209 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1212 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1218 apic_wait_icr_idle();
1220 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1221 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1222 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1225 enum apic_intr_mode_id apic_intr_mode;
1227 static int __init apic_intr_mode_select(void)
1229 /* Check kernel option */
1231 pr_info("APIC disabled via kernel command line\n");
1236 #ifdef CONFIG_X86_64
1237 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1238 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1240 pr_info("APIC disabled by BIOS\n");
1244 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1246 /* Neither 82489DX nor integrated APIC ? */
1247 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1252 /* If the BIOS pretends there is an integrated APIC ? */
1253 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1254 APIC_INTEGRATED(boot_cpu_apic_version)) {
1256 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1257 boot_cpu_physical_apicid);
1262 /* Check MP table or ACPI MADT configuration */
1263 if (!smp_found_config) {
1264 disable_ioapic_support();
1266 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1267 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1269 return APIC_VIRTUAL_WIRE;
1273 /* If SMP should be disabled, then really disable it! */
1274 if (!setup_max_cpus) {
1275 pr_info("APIC: SMP mode deactivated\n");
1276 return APIC_SYMMETRIC_IO_NO_ROUTING;
1279 if (read_apic_id() != boot_cpu_physical_apicid) {
1280 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1281 read_apic_id(), boot_cpu_physical_apicid);
1282 /* Or can we switch back to PIC here? */
1286 return APIC_SYMMETRIC_IO;
1290 * An initial setup of the virtual wire mode.
1292 void __init init_bsp_APIC(void)
1297 * Don't do the setup now if we have a SMP BIOS as the
1298 * through-I/O-APIC virtual wire mode might be active.
1300 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1304 * Do not trust the local APIC being empty at bootup.
1311 value = apic_read(APIC_SPIV);
1312 value &= ~APIC_VECTOR_MASK;
1313 value |= APIC_SPIV_APIC_ENABLED;
1315 #ifdef CONFIG_X86_32
1316 /* This bit is reserved on P4/Xeon and should be cleared */
1317 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1318 (boot_cpu_data.x86 == 15))
1319 value &= ~APIC_SPIV_FOCUS_DISABLED;
1322 value |= APIC_SPIV_FOCUS_DISABLED;
1323 value |= SPURIOUS_APIC_VECTOR;
1324 apic_write(APIC_SPIV, value);
1327 * Set up the virtual wire mode.
1329 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1330 value = APIC_DM_NMI;
1331 if (!lapic_is_integrated()) /* 82489DX */
1332 value |= APIC_LVT_LEVEL_TRIGGER;
1333 if (apic_extnmi == APIC_EXTNMI_NONE)
1334 value |= APIC_LVT_MASKED;
1335 apic_write(APIC_LVT1, value);
1338 /* Init the interrupt delivery mode for the BSP */
1339 void __init apic_intr_mode_init(void)
1341 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1343 apic_intr_mode = apic_intr_mode_select();
1345 switch (apic_intr_mode) {
1347 pr_info("APIC: Keep in PIC mode(8259)\n");
1349 case APIC_VIRTUAL_WIRE:
1350 pr_info("APIC: Switch to virtual wire mode setup\n");
1351 default_setup_apic_routing();
1353 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1354 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1356 default_setup_apic_routing();
1358 case APIC_SYMMETRIC_IO:
1359 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1360 default_setup_apic_routing();
1362 case APIC_SYMMETRIC_IO_NO_ROUTING:
1363 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1367 apic_bsp_setup(upmode);
1370 static void lapic_setup_esr(void)
1372 unsigned int oldvalue, value, maxlvt;
1374 if (!lapic_is_integrated()) {
1375 pr_info("No ESR for 82489DX.\n");
1379 if (apic->disable_esr) {
1381 * Something untraceable is creating bad interrupts on
1382 * secondary quads ... for the moment, just leave the
1383 * ESR disabled - we can't do anything useful with the
1384 * errors anyway - mbligh
1386 pr_info("Leaving ESR disabled.\n");
1390 maxlvt = lapic_get_maxlvt();
1391 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1392 apic_write(APIC_ESR, 0);
1393 oldvalue = apic_read(APIC_ESR);
1395 /* enables sending errors */
1396 value = ERROR_APIC_VECTOR;
1397 apic_write(APIC_LVTERR, value);
1400 * spec says clear errors after enabling vector.
1403 apic_write(APIC_ESR, 0);
1404 value = apic_read(APIC_ESR);
1405 if (value != oldvalue)
1406 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1407 "vector: 0x%08x after: 0x%08x\n",
1411 static void apic_pending_intr_clear(void)
1413 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1414 unsigned long long tsc = 0, ntsc;
1415 unsigned int queued;
1416 unsigned long value;
1417 int i, j, acked = 0;
1419 if (boot_cpu_has(X86_FEATURE_TSC))
1422 * After a crash, we no longer service the interrupts and a pending
1423 * interrupt from previous kernel might still have ISR bit set.
1425 * Most probably by now CPU has serviced that pending interrupt and
1426 * it might not have done the ack_APIC_irq() because it thought,
1427 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1428 * does not clear the ISR bit and cpu thinks it has already serivced
1429 * the interrupt. Hence a vector might get locked. It was noticed
1430 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1434 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1435 queued |= apic_read(APIC_IRR + i*0x10);
1437 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1438 value = apic_read(APIC_ISR + i*0x10);
1439 for_each_set_bit(j, &value, 32) {
1445 pr_err("LAPIC pending interrupts after %d EOI\n", acked);
1449 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1451 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1456 } while (queued && max_loops > 0);
1457 WARN_ON(max_loops <= 0);
1461 * setup_local_APIC - setup the local APIC
1463 * Used to setup local APIC while initializing BSP or bringing up APs.
1464 * Always called with preemption disabled.
1466 static void setup_local_APIC(void)
1468 int cpu = smp_processor_id();
1470 #ifdef CONFIG_X86_32
1471 int logical_apicid, ldr_apicid;
1476 disable_ioapic_support();
1480 #ifdef CONFIG_X86_32
1481 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1482 if (lapic_is_integrated() && apic->disable_esr) {
1483 apic_write(APIC_ESR, 0);
1484 apic_write(APIC_ESR, 0);
1485 apic_write(APIC_ESR, 0);
1486 apic_write(APIC_ESR, 0);
1489 perf_events_lapic_init();
1492 * Double-check whether this APIC is really registered.
1493 * This is meaningless in clustered apic mode, so we skip it.
1495 BUG_ON(!apic->apic_id_registered());
1498 * Intel recommends to set DFR, LDR and TPR before enabling
1499 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1500 * document number 292116). So here it goes...
1502 apic->init_apic_ldr();
1504 #ifdef CONFIG_X86_32
1506 * APIC LDR is initialized. If logical_apicid mapping was
1507 * initialized during get_smp_config(), make sure it matches the
1510 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1511 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1512 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
1513 /* always use the value from LDR */
1514 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1518 * Set Task Priority to 'accept all'. We never change this
1521 value = apic_read(APIC_TASKPRI);
1522 value &= ~APIC_TPRI_MASK;
1523 apic_write(APIC_TASKPRI, value);
1525 apic_pending_intr_clear();
1528 * Now that we are all set up, enable the APIC
1530 value = apic_read(APIC_SPIV);
1531 value &= ~APIC_VECTOR_MASK;
1535 value |= APIC_SPIV_APIC_ENABLED;
1537 #ifdef CONFIG_X86_32
1539 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1540 * certain networking cards. If high frequency interrupts are
1541 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1542 * entry is masked/unmasked at a high rate as well then sooner or
1543 * later IOAPIC line gets 'stuck', no more interrupts are received
1544 * from the device. If focus CPU is disabled then the hang goes
1547 * [ This bug can be reproduced easily with a level-triggered
1548 * PCI Ne2000 networking cards and PII/PIII processors, dual
1552 * Actually disabling the focus CPU check just makes the hang less
1553 * frequent as it makes the interrupt distributon model be more
1554 * like LRU than MRU (the short-term load is more even across CPUs).
1558 * - enable focus processor (bit==0)
1559 * - 64bit mode always use processor focus
1560 * so no need to set it
1562 value &= ~APIC_SPIV_FOCUS_DISABLED;
1566 * Set spurious IRQ vector
1568 value |= SPURIOUS_APIC_VECTOR;
1569 apic_write(APIC_SPIV, value);
1572 * Set up LVT0, LVT1:
1574 * set up through-local-APIC on the boot CPU's LINT0. This is not
1575 * strictly necessary in pure symmetric-IO mode, but sometimes
1576 * we delegate interrupts to the 8259A.
1579 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1581 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1582 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1583 value = APIC_DM_EXTINT;
1584 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1586 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1587 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1589 apic_write(APIC_LVT0, value);
1592 * Only the BSP sees the LINT1 NMI signal by default. This can be
1593 * modified by apic_extnmi= boot option.
1595 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1596 apic_extnmi == APIC_EXTNMI_ALL)
1597 value = APIC_DM_NMI;
1599 value = APIC_DM_NMI | APIC_LVT_MASKED;
1602 if (!lapic_is_integrated())
1603 value |= APIC_LVT_LEVEL_TRIGGER;
1604 apic_write(APIC_LVT1, value);
1606 #ifdef CONFIG_X86_MCE_INTEL
1607 /* Recheck CMCI information after local APIC is up on CPU #0 */
1613 static void end_local_APIC_setup(void)
1617 #ifdef CONFIG_X86_32
1620 /* Disable the local apic timer */
1621 value = apic_read(APIC_LVTT);
1622 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1623 apic_write(APIC_LVTT, value);
1631 * APIC setup function for application processors. Called from smpboot.c
1633 void apic_ap_setup(void)
1636 end_local_APIC_setup();
1639 #ifdef CONFIG_X86_X2APIC
1647 static int x2apic_state;
1649 static void __x2apic_disable(void)
1653 if (!boot_cpu_has(X86_FEATURE_APIC))
1656 rdmsrl(MSR_IA32_APICBASE, msr);
1657 if (!(msr & X2APIC_ENABLE))
1659 /* Disable xapic and x2apic first and then reenable xapic mode */
1660 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1661 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1662 printk_once(KERN_INFO "x2apic disabled\n");
1665 static void __x2apic_enable(void)
1669 rdmsrl(MSR_IA32_APICBASE, msr);
1670 if (msr & X2APIC_ENABLE)
1672 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1673 printk_once(KERN_INFO "x2apic enabled\n");
1676 static int __init setup_nox2apic(char *str)
1678 if (x2apic_enabled()) {
1679 int apicid = native_apic_msr_read(APIC_ID);
1681 if (apicid >= 255) {
1682 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1686 pr_warning("x2apic already enabled.\n");
1689 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1690 x2apic_state = X2APIC_DISABLED;
1694 early_param("nox2apic", setup_nox2apic);
1696 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1697 void x2apic_setup(void)
1700 * If x2apic is not in ON state, disable it if already enabled
1703 if (x2apic_state != X2APIC_ON) {
1710 static __init void x2apic_disable(void)
1712 u32 x2apic_id, state = x2apic_state;
1715 x2apic_state = X2APIC_DISABLED;
1717 if (state != X2APIC_ON)
1720 x2apic_id = read_apic_id();
1721 if (x2apic_id >= 255)
1722 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1725 register_lapic_address(mp_lapic_addr);
1728 static __init void x2apic_enable(void)
1730 if (x2apic_state != X2APIC_OFF)
1734 x2apic_state = X2APIC_ON;
1738 static __init void try_to_enable_x2apic(int remap_mode)
1740 if (x2apic_state == X2APIC_DISABLED)
1743 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1744 /* IR is required if there is APIC ID > 255 even when running
1747 if (max_physical_apicid > 255 ||
1748 !x86_init.hyper.x2apic_available()) {
1749 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1755 * without IR all CPUs can be addressed by IOAPIC/MSI
1756 * only in physical mode
1763 void __init check_x2apic(void)
1765 if (x2apic_enabled()) {
1766 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1768 x2apic_state = X2APIC_ON;
1769 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1770 x2apic_state = X2APIC_DISABLED;
1773 #else /* CONFIG_X86_X2APIC */
1774 static int __init validate_x2apic(void)
1776 if (!apic_is_x2apic_enabled())
1779 * Checkme: Can we simply turn off x2apic here instead of panic?
1781 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1783 early_initcall(validate_x2apic);
1785 static inline void try_to_enable_x2apic(int remap_mode) { }
1786 static inline void __x2apic_enable(void) { }
1787 #endif /* !CONFIG_X86_X2APIC */
1789 void __init enable_IR_x2apic(void)
1791 unsigned long flags;
1794 if (skip_ioapic_setup) {
1795 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1799 ir_stat = irq_remapping_prepare();
1800 if (ir_stat < 0 && !x2apic_supported())
1803 ret = save_ioapic_entries();
1805 pr_info("Saving IO-APIC state failed: %d\n", ret);
1809 local_irq_save(flags);
1810 legacy_pic->mask_all();
1811 mask_ioapic_entries();
1813 /* If irq_remapping_prepare() succeeded, try to enable it */
1815 ir_stat = irq_remapping_enable();
1816 /* ir_stat contains the remap mode or an error code */
1817 try_to_enable_x2apic(ir_stat);
1820 restore_ioapic_entries();
1821 legacy_pic->restore_mask();
1822 local_irq_restore(flags);
1825 #ifdef CONFIG_X86_64
1827 * Detect and enable local APICs on non-SMP boards.
1828 * Original code written by Keir Fraser.
1829 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1830 * not correctly set up (usually the APIC timer won't work etc.)
1832 static int __init detect_init_APIC(void)
1834 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1835 pr_info("No local APIC present\n");
1839 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1844 static int __init apic_verify(void)
1849 * The APIC feature bit should now be enabled
1852 features = cpuid_edx(1);
1853 if (!(features & (1 << X86_FEATURE_APIC))) {
1854 pr_warning("Could not enable APIC!\n");
1857 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1858 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1860 /* The BIOS may have set up the APIC at some other address */
1861 if (boot_cpu_data.x86 >= 6) {
1862 rdmsr(MSR_IA32_APICBASE, l, h);
1863 if (l & MSR_IA32_APICBASE_ENABLE)
1864 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1867 pr_info("Found and enabled local APIC!\n");
1871 int __init apic_force_enable(unsigned long addr)
1879 * Some BIOSes disable the local APIC in the APIC_BASE
1880 * MSR. This can only be done in software for Intel P6 or later
1881 * and AMD K7 (Model > 1) or later.
1883 if (boot_cpu_data.x86 >= 6) {
1884 rdmsr(MSR_IA32_APICBASE, l, h);
1885 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1886 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1887 l &= ~MSR_IA32_APICBASE_BASE;
1888 l |= MSR_IA32_APICBASE_ENABLE | addr;
1889 wrmsr(MSR_IA32_APICBASE, l, h);
1890 enabled_via_apicbase = 1;
1893 return apic_verify();
1897 * Detect and initialize APIC
1899 static int __init detect_init_APIC(void)
1901 /* Disabled by kernel option? */
1905 switch (boot_cpu_data.x86_vendor) {
1906 case X86_VENDOR_AMD:
1907 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1908 (boot_cpu_data.x86 >= 15))
1911 case X86_VENDOR_INTEL:
1912 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1913 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1920 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1922 * Over-ride BIOS and try to enable the local APIC only if
1923 * "lapic" specified.
1925 if (!force_enable_local_apic) {
1926 pr_info("Local APIC disabled by BIOS -- "
1927 "you can enable it with \"lapic\"\n");
1930 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1942 pr_info("No local APIC present or hardware disabled\n");
1948 * init_apic_mappings - initialize APIC mappings
1950 void __init init_apic_mappings(void)
1952 unsigned int new_apicid;
1954 apic_check_deadline_errata();
1957 boot_cpu_physical_apicid = read_apic_id();
1961 /* If no local APIC can be found return early */
1962 if (!smp_found_config && detect_init_APIC()) {
1963 /* lets NOP'ify apic operations */
1964 pr_info("APIC: disable apic facility\n");
1967 apic_phys = mp_lapic_addr;
1970 * If the system has ACPI MADT tables or MP info, the LAPIC
1971 * address is already registered.
1973 if (!acpi_lapic && !smp_found_config)
1974 register_lapic_address(apic_phys);
1978 * Fetch the APIC ID of the BSP in case we have a
1979 * default configuration (or the MP table is broken).
1981 new_apicid = read_apic_id();
1982 if (boot_cpu_physical_apicid != new_apicid) {
1983 boot_cpu_physical_apicid = new_apicid;
1985 * yeah -- we lie about apic_version
1986 * in case if apic was disabled via boot option
1987 * but it's not a problem for SMP compiled kernel
1988 * since apic_intr_mode_select is prepared for such
1989 * a case and disable smp mode
1991 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1995 void __init register_lapic_address(unsigned long address)
1997 mp_lapic_addr = address;
2000 set_fixmap_nocache(FIX_APIC_BASE, address);
2001 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2002 APIC_BASE, address);
2004 if (boot_cpu_physical_apicid == -1U) {
2005 boot_cpu_physical_apicid = read_apic_id();
2006 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2011 * Local APIC interrupts
2015 * This interrupt should _never_ happen with our APIC/SMP architecture
2017 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2019 u8 vector = ~regs->orig_ax;
2023 trace_spurious_apic_entry(vector);
2026 * Check if this really is a spurious interrupt and ACK it
2027 * if it is a vectored one. Just in case...
2028 * Spurious interrupts should not be ACKed.
2030 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2031 if (v & (1 << (vector & 0x1f)))
2034 inc_irq_stat(irq_spurious_count);
2036 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
2037 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
2038 "should never happen.\n", vector, smp_processor_id());
2040 trace_spurious_apic_exit(vector);
2045 * This interrupt should never happen with our APIC/SMP architecture
2047 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2049 static const char * const error_interrupt_reason[] = {
2050 "Send CS error", /* APIC Error Bit 0 */
2051 "Receive CS error", /* APIC Error Bit 1 */
2052 "Send accept error", /* APIC Error Bit 2 */
2053 "Receive accept error", /* APIC Error Bit 3 */
2054 "Redirectable IPI", /* APIC Error Bit 4 */
2055 "Send illegal vector", /* APIC Error Bit 5 */
2056 "Received illegal vector", /* APIC Error Bit 6 */
2057 "Illegal register address", /* APIC Error Bit 7 */
2062 trace_error_apic_entry(ERROR_APIC_VECTOR);
2064 /* First tickle the hardware, only then report what went on. -- REW */
2065 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2066 apic_write(APIC_ESR, 0);
2067 v = apic_read(APIC_ESR);
2069 atomic_inc(&irq_err_count);
2071 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2072 smp_processor_id(), v);
2077 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2082 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2084 trace_error_apic_exit(ERROR_APIC_VECTOR);
2089 * connect_bsp_APIC - attach the APIC to the interrupt system
2091 static void __init connect_bsp_APIC(void)
2093 #ifdef CONFIG_X86_32
2096 * Do not trust the local APIC being empty at bootup.
2100 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2101 * local APIC to INT and NMI lines.
2103 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2104 "enabling APIC mode.\n");
2111 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2112 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2114 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2117 void disconnect_bsp_APIC(int virt_wire_setup)
2121 #ifdef CONFIG_X86_32
2124 * Put the board back into PIC mode (has an effect only on
2125 * certain older boards). Note that APIC interrupts, including
2126 * IPIs, won't work beyond this point! The only exception are
2129 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2130 "entering PIC mode.\n");
2136 /* Go back to Virtual Wire compatibility mode */
2138 /* For the spurious interrupt use vector F, and enable it */
2139 value = apic_read(APIC_SPIV);
2140 value &= ~APIC_VECTOR_MASK;
2141 value |= APIC_SPIV_APIC_ENABLED;
2143 apic_write(APIC_SPIV, value);
2145 if (!virt_wire_setup) {
2147 * For LVT0 make it edge triggered, active high,
2148 * external and enabled
2150 value = apic_read(APIC_LVT0);
2151 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2152 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2153 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2154 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2155 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2156 apic_write(APIC_LVT0, value);
2159 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2163 * For LVT1 make it edge triggered, active high,
2166 value = apic_read(APIC_LVT1);
2167 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2168 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2169 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2170 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2171 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2172 apic_write(APIC_LVT1, value);
2176 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2177 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2178 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2179 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2181 * NOTE: Reserve 0 for BSP.
2183 static int nr_logical_cpuids = 1;
2186 * Used to store mapping between logical CPU IDs and APIC IDs.
2188 static int cpuid_to_apicid[] = {
2189 [0 ... NR_CPUS - 1] = -1,
2193 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2194 * and cpuid_to_apicid[] synchronized.
2196 static int allocate_logical_cpuid(int apicid)
2201 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2202 * check if the kernel has allocated a cpuid for it.
2204 for (i = 0; i < nr_logical_cpuids; i++) {
2205 if (cpuid_to_apicid[i] == apicid)
2209 /* Allocate a new cpuid. */
2210 if (nr_logical_cpuids >= nr_cpu_ids) {
2211 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2212 "Processor %d/0x%x and the rest are ignored.\n",
2213 nr_cpu_ids, nr_logical_cpuids, apicid);
2217 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2218 return nr_logical_cpuids++;
2221 int generic_processor_info(int apicid, int version)
2223 int cpu, max = nr_cpu_ids;
2224 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2225 phys_cpu_present_map);
2228 * boot_cpu_physical_apicid is designed to have the apicid
2229 * returned by read_apic_id(), i.e, the apicid of the
2230 * currently booting-up processor. However, on some platforms,
2231 * it is temporarily modified by the apicid reported as BSP
2232 * through MP table. Concretely:
2234 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2235 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2237 * This function is executed with the modified
2238 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2239 * parameter doesn't work to disable APs on kdump 2nd kernel.
2241 * Since fixing handling of boot_cpu_physical_apicid requires
2242 * another discussion and tests on each platform, we leave it
2243 * for now and here we use read_apic_id() directly in this
2244 * function, generic_processor_info().
2246 if (disabled_cpu_apicid != BAD_APICID &&
2247 disabled_cpu_apicid != read_apic_id() &&
2248 disabled_cpu_apicid == apicid) {
2249 int thiscpu = num_processors + disabled_cpus;
2251 pr_warning("APIC: Disabling requested cpu."
2252 " Processor %d/0x%x ignored.\n",
2260 * If boot cpu has not been detected yet, then only allow upto
2261 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2263 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2264 apicid != boot_cpu_physical_apicid) {
2265 int thiscpu = max + disabled_cpus - 1;
2268 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2269 " reached. Keeping one slot for boot cpu."
2270 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2276 if (num_processors >= nr_cpu_ids) {
2277 int thiscpu = max + disabled_cpus;
2279 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2280 "reached. Processor %d/0x%x ignored.\n",
2281 max, thiscpu, apicid);
2287 if (apicid == boot_cpu_physical_apicid) {
2289 * x86_bios_cpu_apicid is required to have processors listed
2290 * in same order as logical cpu numbers. Hence the first
2291 * entry is BSP, and so on.
2292 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2297 /* Logical cpuid 0 is reserved for BSP. */
2298 cpuid_to_apicid[0] = apicid;
2300 cpu = allocate_logical_cpuid(apicid);
2310 if (version == 0x0) {
2311 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2316 if (version != boot_cpu_apic_version) {
2317 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2318 boot_cpu_apic_version, cpu, version);
2321 if (apicid > max_physical_apicid)
2322 max_physical_apicid = apicid;
2324 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2325 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2326 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2328 #ifdef CONFIG_X86_32
2329 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2330 apic->x86_32_early_logical_apicid(cpu);
2332 set_cpu_possible(cpu, true);
2333 physid_set(apicid, phys_cpu_present_map);
2334 set_cpu_present(cpu, true);
2340 int hard_smp_processor_id(void)
2342 return read_apic_id();
2346 * Override the generic EOI implementation with an optimized version.
2347 * Only called during early boot when only one CPU is active and with
2348 * interrupts disabled, so we know this does not race with actual APIC driver
2351 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2355 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2356 /* Should happen once for each apic */
2357 WARN_ON((*drv)->eoi_write == eoi_write);
2358 (*drv)->native_eoi_write = (*drv)->eoi_write;
2359 (*drv)->eoi_write = eoi_write;
2363 static void __init apic_bsp_up_setup(void)
2365 #ifdef CONFIG_X86_64
2366 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2369 * Hack: In case of kdump, after a crash, kernel might be booting
2370 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2371 * might be zero if read from MP tables. Get it from LAPIC.
2373 # ifdef CONFIG_CRASH_DUMP
2374 boot_cpu_physical_apicid = read_apic_id();
2377 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2381 * apic_bsp_setup - Setup function for local apic and io-apic
2382 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2385 * apic_id of BSP APIC
2387 void __init apic_bsp_setup(bool upmode)
2391 apic_bsp_up_setup();
2395 end_local_APIC_setup();
2396 irq_remap_enable_fault_handling();
2400 #ifdef CONFIG_UP_LATE_INIT
2401 void __init up_late_init(void)
2403 if (apic_intr_mode == APIC_PIC)
2406 /* Setup local timer */
2407 x86_init.timers.setup_percpu_clockev();
2418 * 'active' is true if the local APIC was enabled by us and
2419 * not the BIOS; this signifies that we are also responsible
2420 * for disabling it before entering apm/acpi suspend
2423 /* r/w apic fields */
2424 unsigned int apic_id;
2425 unsigned int apic_taskpri;
2426 unsigned int apic_ldr;
2427 unsigned int apic_dfr;
2428 unsigned int apic_spiv;
2429 unsigned int apic_lvtt;
2430 unsigned int apic_lvtpc;
2431 unsigned int apic_lvt0;
2432 unsigned int apic_lvt1;
2433 unsigned int apic_lvterr;
2434 unsigned int apic_tmict;
2435 unsigned int apic_tdcr;
2436 unsigned int apic_thmr;
2437 unsigned int apic_cmci;
2440 static int lapic_suspend(void)
2442 unsigned long flags;
2445 if (!apic_pm_state.active)
2448 maxlvt = lapic_get_maxlvt();
2450 apic_pm_state.apic_id = apic_read(APIC_ID);
2451 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2452 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2453 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2454 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2455 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2457 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2458 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2459 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2460 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2461 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2462 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2463 #ifdef CONFIG_X86_THERMAL_VECTOR
2465 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2467 #ifdef CONFIG_X86_MCE_INTEL
2469 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2472 local_irq_save(flags);
2473 disable_local_APIC();
2475 irq_remapping_disable();
2477 local_irq_restore(flags);
2481 static void lapic_resume(void)
2484 unsigned long flags;
2487 if (!apic_pm_state.active)
2490 local_irq_save(flags);
2493 * IO-APIC and PIC have their own resume routines.
2494 * We just mask them here to make sure the interrupt
2495 * subsystem is completely quiet while we enable x2apic
2496 * and interrupt-remapping.
2498 mask_ioapic_entries();
2499 legacy_pic->mask_all();
2505 * Make sure the APICBASE points to the right address
2507 * FIXME! This will be wrong if we ever support suspend on
2508 * SMP! We'll need to do this as part of the CPU restore!
2510 if (boot_cpu_data.x86 >= 6) {
2511 rdmsr(MSR_IA32_APICBASE, l, h);
2512 l &= ~MSR_IA32_APICBASE_BASE;
2513 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2514 wrmsr(MSR_IA32_APICBASE, l, h);
2518 maxlvt = lapic_get_maxlvt();
2519 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2520 apic_write(APIC_ID, apic_pm_state.apic_id);
2521 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2522 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2523 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2524 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2525 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2526 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2527 #ifdef CONFIG_X86_THERMAL_VECTOR
2529 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2531 #ifdef CONFIG_X86_MCE_INTEL
2533 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2536 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2537 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2538 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2539 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2540 apic_write(APIC_ESR, 0);
2541 apic_read(APIC_ESR);
2542 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2543 apic_write(APIC_ESR, 0);
2544 apic_read(APIC_ESR);
2546 irq_remapping_reenable(x2apic_mode);
2548 local_irq_restore(flags);
2552 * This device has no shutdown method - fully functioning local APICs
2553 * are needed on every CPU up until machine_halt/restart/poweroff.
2556 static struct syscore_ops lapic_syscore_ops = {
2557 .resume = lapic_resume,
2558 .suspend = lapic_suspend,
2561 static void apic_pm_activate(void)
2563 apic_pm_state.active = 1;
2566 static int __init init_lapic_sysfs(void)
2568 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2569 if (boot_cpu_has(X86_FEATURE_APIC))
2570 register_syscore_ops(&lapic_syscore_ops);
2575 /* local apic needs to resume before other devices access its registers. */
2576 core_initcall(init_lapic_sysfs);
2578 #else /* CONFIG_PM */
2580 static void apic_pm_activate(void) { }
2582 #endif /* CONFIG_PM */
2584 #ifdef CONFIG_X86_64
2586 static int multi_checked;
2589 static int set_multi(const struct dmi_system_id *d)
2593 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2598 static const struct dmi_system_id multi_dmi_table[] = {
2600 .callback = set_multi,
2601 .ident = "IBM System Summit2",
2603 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2604 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2610 static void dmi_check_multi(void)
2615 dmi_check_system(multi_dmi_table);
2620 * apic_is_clustered_box() -- Check if we can expect good TSC
2622 * Thus far, the major user of this is IBM's Summit2 series:
2623 * Clustered boxes may have unsynced TSC problems if they are
2625 * Use DMI to check them
2627 int apic_is_clustered_box(void)
2635 * APIC command line parameters
2637 static int __init setup_disableapic(char *arg)
2640 setup_clear_cpu_cap(X86_FEATURE_APIC);
2643 early_param("disableapic", setup_disableapic);
2645 /* same as disableapic, for compatibility */
2646 static int __init setup_nolapic(char *arg)
2648 return setup_disableapic(arg);
2650 early_param("nolapic", setup_nolapic);
2652 static int __init parse_lapic_timer_c2_ok(char *arg)
2654 local_apic_timer_c2_ok = 1;
2657 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2659 static int __init parse_disable_apic_timer(char *arg)
2661 disable_apic_timer = 1;
2664 early_param("noapictimer", parse_disable_apic_timer);
2666 static int __init parse_nolapic_timer(char *arg)
2668 disable_apic_timer = 1;
2671 early_param("nolapic_timer", parse_nolapic_timer);
2673 static int __init apic_set_verbosity(char *arg)
2676 #ifdef CONFIG_X86_64
2677 skip_ioapic_setup = 0;
2683 if (strcmp("debug", arg) == 0)
2684 apic_verbosity = APIC_DEBUG;
2685 else if (strcmp("verbose", arg) == 0)
2686 apic_verbosity = APIC_VERBOSE;
2687 #ifdef CONFIG_X86_64
2689 pr_warning("APIC Verbosity level %s not recognised"
2690 " use apic=verbose or apic=debug\n", arg);
2697 early_param("apic", apic_set_verbosity);
2699 static int __init lapic_insert_resource(void)
2704 /* Put local APIC into the resource map. */
2705 lapic_resource.start = apic_phys;
2706 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2707 insert_resource(&iomem_resource, &lapic_resource);
2713 * need call insert after e820__reserve_resources()
2714 * that is using request_resource
2716 late_initcall(lapic_insert_resource);
2718 static int __init apic_set_disabled_cpu_apicid(char *arg)
2720 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2725 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2727 static int __init apic_set_extnmi(char *arg)
2732 if (!strncmp("all", arg, 3))
2733 apic_extnmi = APIC_EXTNMI_ALL;
2734 else if (!strncmp("none", arg, 4))
2735 apic_extnmi = APIC_EXTNMI_NONE;
2736 else if (!strncmp("bsp", arg, 3))
2737 apic_extnmi = APIC_EXTNMI_BSP;
2739 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2745 early_param("apic_extnmi", apic_set_extnmi);