1 // SPDX-License-Identifier: GPL-2.0-only
3 * Shared support code for AMD K8 northbridges and derivates.
4 * Copyright 2006 Andi Kleen, SUSE Labs.
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/types.h>
10 #include <linux/slab.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/spinlock.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
18 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480
21 #define PCI_DEVICE_ID_AMD_17H_DF_F4 0x1464
22 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
23 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
24 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
26 /* Protect the PCI config register pairs used for SMN and DF indirect access. */
27 static DEFINE_MUTEX(smn_mutex);
29 static u32 *flush_words;
31 static const struct pci_device_id amd_root_ids[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
33 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
34 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
39 #define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
41 const struct pci_device_id amd_nb_misc_ids[] = {
42 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
43 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
44 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
45 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
46 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
47 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
48 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
49 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
50 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
51 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
52 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
53 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
54 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
57 EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
59 static const struct pci_device_id amd_nb_link_ids[] = {
60 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
63 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
64 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
67 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
68 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
69 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
73 static const struct pci_device_id hygon_root_ids[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
78 static const struct pci_device_id hygon_nb_misc_ids[] = {
79 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
83 static const struct pci_device_id hygon_nb_link_ids[] = {
84 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
88 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
95 static struct amd_northbridge_info amd_northbridges;
99 return amd_northbridges.num;
101 EXPORT_SYMBOL_GPL(amd_nb_num);
103 bool amd_nb_has_feature(unsigned int feature)
105 return ((amd_northbridges.flags & feature) == feature);
107 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
109 struct amd_northbridge *node_to_amd_nb(int node)
111 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
113 EXPORT_SYMBOL_GPL(node_to_amd_nb);
115 static struct pci_dev *next_northbridge(struct pci_dev *dev,
116 const struct pci_device_id *ids)
119 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
122 } while (!pci_match_id(ids, dev));
126 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
128 struct pci_dev *root;
131 if (node >= amd_northbridges.num)
134 root = node_to_amd_nb(node)->root;
138 mutex_lock(&smn_mutex);
140 err = pci_write_config_dword(root, 0x60, address);
142 pr_warn("Error programming SMN address 0x%x.\n", address);
146 err = (write ? pci_write_config_dword(root, 0x64, *value)
147 : pci_read_config_dword(root, 0x64, value));
149 pr_warn("Error %s SMN address 0x%x.\n",
150 (write ? "writing to" : "reading from"), address);
153 mutex_unlock(&smn_mutex);
159 int amd_smn_read(u16 node, u32 address, u32 *value)
161 return __amd_smn_rw(node, address, value, false);
163 EXPORT_SYMBOL_GPL(amd_smn_read);
165 int amd_smn_write(u16 node, u32 address, u32 value)
167 return __amd_smn_rw(node, address, &value, true);
169 EXPORT_SYMBOL_GPL(amd_smn_write);
172 * Data Fabric Indirect Access uses FICAA/FICAD.
174 * Fabric Indirect Configuration Access Address (FICAA): Constructed based
175 * on the device's Instance Id and the PCI function and register offset of
176 * the desired register.
178 * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
179 * and FICAD HI registers but so far we only need the LO register.
181 int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
187 if (node >= amd_northbridges.num)
190 F4 = node_to_amd_nb(node)->link;
195 ficaa |= reg & 0x3FC;
196 ficaa |= (func & 0x7) << 11;
197 ficaa |= instance_id << 16;
199 mutex_lock(&smn_mutex);
201 err = pci_write_config_dword(F4, 0x5C, ficaa);
203 pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
207 err = pci_read_config_dword(F4, 0x98, lo);
209 pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
212 mutex_unlock(&smn_mutex);
217 EXPORT_SYMBOL_GPL(amd_df_indirect_read);
219 int amd_cache_northbridges(void)
221 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
222 const struct pci_device_id *link_ids = amd_nb_link_ids;
223 const struct pci_device_id *root_ids = amd_root_ids;
224 struct pci_dev *root, *misc, *link;
225 struct amd_northbridge *nb;
226 u16 roots_per_misc = 0;
231 if (amd_northbridges.num)
234 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
235 root_ids = hygon_root_ids;
236 misc_ids = hygon_nb_misc_ids;
237 link_ids = hygon_nb_link_ids;
241 while ((misc = next_northbridge(misc, misc_ids)) != NULL)
248 while ((root = next_northbridge(root, root_ids)) != NULL)
252 roots_per_misc = root_count / misc_count;
255 * There should be _exactly_ N roots for each DF/SMN
258 if (!roots_per_misc || (root_count % roots_per_misc)) {
259 pr_info("Unsupported AMD DF/PCI configuration found\n");
264 nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
268 amd_northbridges.nb = nb;
269 amd_northbridges.num = misc_count;
271 link = misc = root = NULL;
272 for (i = 0; i < amd_northbridges.num; i++) {
273 node_to_amd_nb(i)->root = root =
274 next_northbridge(root, root_ids);
275 node_to_amd_nb(i)->misc = misc =
276 next_northbridge(misc, misc_ids);
277 node_to_amd_nb(i)->link = link =
278 next_northbridge(link, link_ids);
281 * If there are more PCI root devices than data fabric/
282 * system management network interfaces, then the (N)
283 * PCI roots per DF/SMN interface are functionally the
284 * same (for DF/SMN access) and N-1 are redundant. N-1
285 * PCI roots should be skipped per DF/SMN interface so
286 * the following DF/SMN interfaces get mapped to
289 for (j = 1; j < roots_per_misc; j++)
290 root = next_northbridge(root, root_ids);
293 if (amd_gart_present())
294 amd_northbridges.flags |= AMD_NB_GART;
297 * Check for L3 cache presence.
299 if (!cpuid_edx(0x80000006))
303 * Some CPU families support L3 Cache Index Disable. There are some
304 * limitations because of E382 and E388 on family 0x10.
306 if (boot_cpu_data.x86 == 0x10 &&
307 boot_cpu_data.x86_model >= 0x8 &&
308 (boot_cpu_data.x86_model > 0x9 ||
309 boot_cpu_data.x86_stepping >= 0x1))
310 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
312 if (boot_cpu_data.x86 == 0x15)
313 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
315 /* L3 cache partitioning is supported on family 0x15 */
316 if (boot_cpu_data.x86 == 0x15)
317 amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
321 EXPORT_SYMBOL_GPL(amd_cache_northbridges);
324 * Ignores subdevice/subvendor but as far as I can figure out
325 * they're useless anyways
327 bool __init early_is_amd_nb(u32 device)
329 const struct pci_device_id *misc_ids = amd_nb_misc_ids;
330 const struct pci_device_id *id;
331 u32 vendor = device & 0xffff;
333 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
334 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
337 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
338 misc_ids = hygon_nb_misc_ids;
341 for (id = misc_ids; id->vendor; id++)
342 if (vendor == id->vendor && device == id->device)
347 struct resource *amd_get_mmconfig_range(struct resource *res)
351 unsigned int segn_busn_bits;
353 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
354 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
357 /* assume all cpus from fam10h have mmconfig */
358 if (boot_cpu_data.x86 < 0x10)
361 address = MSR_FAM10H_MMIO_CONF_BASE;
362 rdmsrl(address, msr);
364 /* mmconfig is not enabled */
365 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
368 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
370 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
371 FAM10H_MMIO_CONF_BUSRANGE_MASK;
373 res->flags = IORESOURCE_MEM;
375 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
379 int amd_get_subcaches(int cpu)
381 struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
384 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
387 pci_read_config_dword(link, 0x1d4, &mask);
389 return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
392 int amd_set_subcaches(int cpu, unsigned long mask)
394 static unsigned int reset, ban;
395 struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
399 if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
402 /* if necessary, collect reset state of L3 partitioning and BAN mode */
404 pci_read_config_dword(nb->link, 0x1d4, &reset);
405 pci_read_config_dword(nb->misc, 0x1b8, &ban);
409 /* deactivate BAN mode if any subcaches are to be disabled */
411 pci_read_config_dword(nb->misc, 0x1b8, ®);
412 pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
415 cuid = cpu_data(cpu).cpu_core_id;
417 mask |= (0xf ^ (1 << cuid)) << 26;
419 pci_write_config_dword(nb->link, 0x1d4, mask);
421 /* reset BAN mode if L3 partitioning returned to reset state */
422 pci_read_config_dword(nb->link, 0x1d4, ®);
424 pci_read_config_dword(nb->misc, 0x1b8, ®);
426 pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
432 static void amd_cache_gart(void)
436 if (!amd_nb_has_feature(AMD_NB_GART))
439 flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
441 amd_northbridges.flags &= ~AMD_NB_GART;
442 pr_notice("Cannot initialize GART flush words, GART support disabled\n");
446 for (i = 0; i != amd_northbridges.num; i++)
447 pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
450 void amd_flush_garts(void)
454 static DEFINE_SPINLOCK(gart_lock);
456 if (!amd_nb_has_feature(AMD_NB_GART))
460 * Avoid races between AGP and IOMMU. In theory it's not needed
461 * but I'm not sure if the hardware won't lose flush requests
462 * when another is pending. This whole thing is so expensive anyways
463 * that it doesn't matter to serialize more. -AK
465 spin_lock_irqsave(&gart_lock, flags);
467 for (i = 0; i < amd_northbridges.num; i++) {
468 pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
472 for (i = 0; i < amd_northbridges.num; i++) {
474 /* Make sure the hardware actually executed the flush*/
476 pci_read_config_dword(node_to_amd_nb(i)->misc,
483 spin_unlock_irqrestore(&gart_lock, flags);
485 pr_notice("nothing to flush?\n");
487 EXPORT_SYMBOL_GPL(amd_flush_garts);
489 static void __fix_erratum_688(void *info)
491 #define MSR_AMD64_IC_CFG 0xC0011021
493 msr_set_bit(MSR_AMD64_IC_CFG, 3);
494 msr_set_bit(MSR_AMD64_IC_CFG, 14);
497 /* Apply erratum 688 fix so machines without a BIOS fix work. */
498 static __init void fix_erratum_688(void)
503 if (boot_cpu_data.x86 != 0x14)
506 if (!amd_northbridges.num)
509 F4 = node_to_amd_nb(0)->link;
513 if (pci_read_config_dword(F4, 0x164, &val))
519 on_each_cpu(__fix_erratum_688, NULL, 0);
521 pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
524 static __init int init_amd_nbs(void)
526 amd_cache_northbridges();
534 /* This has to go after the PCI subsystem */
535 fs_initcall(init_amd_nbs);