2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
36 * definitions for the ACPI scanning code
38 #define IVRS_HEADER_LENGTH 48
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
72 * ACPI table definitions
74 * These data structures are laid over the table to parse the important values
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
92 } __attribute__((packed));
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
103 } __attribute__((packed));
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
118 } __attribute__((packed));
122 static int __initdata amd_iommu_detected;
123 static bool __initdata amd_iommu_disabled;
125 u16 amd_iommu_last_bdf; /* largest PCI device id we have
127 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
129 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
131 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
134 /* Array to assign indices to IOMMUs*/
135 struct amd_iommu *amd_iommus[MAX_IOMMUS];
136 int amd_iommus_present;
138 /* IOMMUs have a non-present cache? */
139 bool amd_iommu_np_cache __read_mostly;
140 bool amd_iommu_iotlb_sup __read_mostly = true;
143 * The ACPI table parsing functions set this variable on an error
145 static int __initdata amd_iommu_init_err;
148 * List of protection domains - used during resume
150 LIST_HEAD(amd_iommu_pd_list);
151 spinlock_t amd_iommu_pd_lock;
154 * Pointer to the device table which is shared by all AMD IOMMUs
155 * it is indexed by the PCI device id or the HT unit id and contains
156 * information about the domain the device belongs to as well as the
157 * page table root pointer.
159 struct dev_table_entry *amd_iommu_dev_table;
162 * The alias table is a driver specific data structure which contains the
163 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
164 * More than one device can share the same requestor id.
166 u16 *amd_iommu_alias_table;
169 * The rlookup table is used to find the IOMMU which is responsible
170 * for a specific device. It is also indexed by the PCI device id.
172 struct amd_iommu **amd_iommu_rlookup_table;
175 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
176 * to know which ones are already in use.
178 unsigned long *amd_iommu_pd_alloc_bitmap;
180 static u32 dev_table_size; /* size of the device table */
181 static u32 alias_table_size; /* size of the alias table */
182 static u32 rlookup_table_size; /* size if the rlookup table */
185 * This function flushes all internal caches of
186 * the IOMMU used by this driver.
188 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
190 static inline void update_last_devid(u16 devid)
192 if (devid > amd_iommu_last_bdf)
193 amd_iommu_last_bdf = devid;
196 static inline unsigned long tbl_size(int entry_size)
198 unsigned shift = PAGE_SHIFT +
199 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
204 /* Access to l1 and l2 indexed register spaces */
206 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
210 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
211 pci_read_config_dword(iommu->dev, 0xfc, &val);
215 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
217 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
218 pci_write_config_dword(iommu->dev, 0xfc, val);
219 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
222 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
226 pci_write_config_dword(iommu->dev, 0xf0, address);
227 pci_read_config_dword(iommu->dev, 0xf4, &val);
231 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
233 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
234 pci_write_config_dword(iommu->dev, 0xf4, val);
237 /****************************************************************************
239 * AMD IOMMU MMIO register space handling functions
241 * These functions are used to program the IOMMU device registers in
242 * MMIO space required for that driver.
244 ****************************************************************************/
247 * This function set the exclusion range in the IOMMU. DMA accesses to the
248 * exclusion range are passed through untranslated
250 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
252 u64 start = iommu->exclusion_start & PAGE_MASK;
253 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
256 if (!iommu->exclusion_start)
259 entry = start | MMIO_EXCL_ENABLE_MASK;
260 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
261 &entry, sizeof(entry));
264 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
265 &entry, sizeof(entry));
268 /* Programs the physical address of the device table into the IOMMU hardware */
269 static void __init iommu_set_device_table(struct amd_iommu *iommu)
273 BUG_ON(iommu->mmio_base == NULL);
275 entry = virt_to_phys(amd_iommu_dev_table);
276 entry |= (dev_table_size >> 12) - 1;
277 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
278 &entry, sizeof(entry));
281 /* Generic functions to enable/disable certain features of the IOMMU. */
282 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
286 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
288 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
291 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
295 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
297 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
300 /* Function to enable the hardware */
301 static void iommu_enable(struct amd_iommu *iommu)
303 static const char * const feat_str[] = {
304 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
305 "IA", "GA", "HE", "PC", NULL
309 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
310 dev_name(&iommu->dev->dev), iommu->cap_ptr);
312 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
313 printk(KERN_CONT " extended features: ");
314 for (i = 0; feat_str[i]; ++i)
315 if (iommu_feature(iommu, (1ULL << i)))
316 printk(KERN_CONT " %s", feat_str[i]);
318 printk(KERN_CONT "\n");
320 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
323 static void iommu_disable(struct amd_iommu *iommu)
325 /* Disable command buffer */
326 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
328 /* Disable event logging and event interrupts */
329 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
330 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
332 /* Disable IOMMU hardware itself */
333 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
337 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
338 * the system has one.
340 static u8 * __init iommu_map_mmio_space(u64 address)
344 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
345 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
347 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
351 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
355 release_mem_region(address, MMIO_REGION_LENGTH);
360 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
362 if (iommu->mmio_base)
363 iounmap(iommu->mmio_base);
364 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
367 /****************************************************************************
369 * The functions below belong to the first pass of AMD IOMMU ACPI table
370 * parsing. In this pass we try to find out the highest device id this
371 * code has to handle. Upon this information the size of the shared data
372 * structures is determined later.
374 ****************************************************************************/
377 * This function calculates the length of a given IVHD entry
379 static inline int ivhd_entry_length(u8 *ivhd)
381 return 0x04 << (*ivhd >> 6);
385 * This function reads the last device id the IOMMU has to handle from the PCI
386 * capability header for this IOMMU
388 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
392 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
393 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
399 * After reading the highest device id from the IOMMU PCI capability header
400 * this function looks if there is a higher device id defined in the ACPI table
402 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
404 u8 *p = (void *)h, *end = (void *)h;
405 struct ivhd_entry *dev;
410 find_last_devid_on_pci(PCI_BUS(h->devid),
416 dev = (struct ivhd_entry *)p;
418 case IVHD_DEV_SELECT:
419 case IVHD_DEV_RANGE_END:
421 case IVHD_DEV_EXT_SELECT:
422 /* all the above subfield types refer to device ids */
423 update_last_devid(dev->devid);
428 p += ivhd_entry_length(p);
437 * Iterate over all IVHD entries in the ACPI table and find the highest device
438 * id which we need to handle. This is the first of three functions which parse
439 * the ACPI table. So we check the checksum here.
441 static int __init find_last_devid_acpi(struct acpi_table_header *table)
444 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
445 struct ivhd_header *h;
448 * Validate checksum here so we don't need to do it when
449 * we actually parse the table
451 for (i = 0; i < table->length; ++i)
454 /* ACPI table corrupt */
455 amd_iommu_init_err = -ENODEV;
459 p += IVRS_HEADER_LENGTH;
461 end += table->length;
463 h = (struct ivhd_header *)p;
466 find_last_devid_from_ivhd(h);
478 /****************************************************************************
480 * The following functions belong the the code path which parses the ACPI table
481 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
482 * data structures, initialize the device/alias/rlookup table and also
483 * basically initialize the hardware.
485 ****************************************************************************/
488 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
489 * write commands to that buffer later and the IOMMU will execute them
492 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
494 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
495 get_order(CMD_BUFFER_SIZE));
500 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
506 * This function resets the command buffer if the IOMMU stopped fetching
509 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
511 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
513 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
514 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
516 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
520 * This function writes the command buffer address to the hardware and
523 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
527 BUG_ON(iommu->cmd_buf == NULL);
529 entry = (u64)virt_to_phys(iommu->cmd_buf);
530 entry |= MMIO_CMD_SIZE_512;
532 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
533 &entry, sizeof(entry));
535 amd_iommu_reset_cmd_buffer(iommu);
536 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
539 static void __init free_command_buffer(struct amd_iommu *iommu)
541 free_pages((unsigned long)iommu->cmd_buf,
542 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
545 /* allocates the memory where the IOMMU will log its events to */
546 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
548 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
549 get_order(EVT_BUFFER_SIZE));
551 if (iommu->evt_buf == NULL)
554 iommu->evt_buf_size = EVT_BUFFER_SIZE;
556 return iommu->evt_buf;
559 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
563 BUG_ON(iommu->evt_buf == NULL);
565 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
567 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
568 &entry, sizeof(entry));
570 /* set head and tail to zero manually */
571 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
572 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
574 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
577 static void __init free_event_buffer(struct amd_iommu *iommu)
579 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
582 /* sets a specific bit in the device table entry. */
583 static void set_dev_entry_bit(u16 devid, u8 bit)
585 int i = (bit >> 5) & 0x07;
586 int _bit = bit & 0x1f;
588 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
591 static int get_dev_entry_bit(u16 devid, u8 bit)
593 int i = (bit >> 5) & 0x07;
594 int _bit = bit & 0x1f;
596 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
600 void amd_iommu_apply_erratum_63(u16 devid)
604 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
605 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
608 set_dev_entry_bit(devid, DEV_ENTRY_IW);
611 /* Writes the specific IOMMU for a device into the rlookup table */
612 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
614 amd_iommu_rlookup_table[devid] = iommu;
618 * This function takes the device specific flags read from the ACPI
619 * table and sets up the device table entry with that information
621 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
622 u16 devid, u32 flags, u32 ext_flags)
624 if (flags & ACPI_DEVFLAG_INITPASS)
625 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
626 if (flags & ACPI_DEVFLAG_EXTINT)
627 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
628 if (flags & ACPI_DEVFLAG_NMI)
629 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
630 if (flags & ACPI_DEVFLAG_SYSMGT1)
631 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
632 if (flags & ACPI_DEVFLAG_SYSMGT2)
633 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
634 if (flags & ACPI_DEVFLAG_LINT0)
635 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
636 if (flags & ACPI_DEVFLAG_LINT1)
637 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
639 amd_iommu_apply_erratum_63(devid);
641 set_iommu_for_device(iommu, devid);
645 * Reads the device exclusion range from ACPI and initialize IOMMU with
648 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
650 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
652 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
657 * We only can configure exclusion ranges per IOMMU, not
658 * per device. But we can enable the exclusion range per
659 * device. This is done here
661 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
662 iommu->exclusion_start = m->range_start;
663 iommu->exclusion_length = m->range_length;
668 * This function reads some important data from the IOMMU PCI space and
669 * initializes the driver data structure with it. It reads the hardware
670 * capabilities and the first/last device entries
672 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
674 int cap_ptr = iommu->cap_ptr;
675 u32 range, misc, low, high;
678 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
680 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
682 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
685 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
687 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
689 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
691 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
692 amd_iommu_iotlb_sup = false;
694 /* read extended feature bits */
695 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
696 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
698 iommu->features = ((u64)high << 32) | low;
700 if (!is_rd890_iommu(iommu->dev))
704 * Some rd890 systems may not be fully reconfigured by the BIOS, so
705 * it's necessary for us to store this information so it can be
706 * reprogrammed on resume
709 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
710 &iommu->stored_addr_lo);
711 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
712 &iommu->stored_addr_hi);
714 /* Low bit locks writes to configuration space */
715 iommu->stored_addr_lo &= ~1;
717 for (i = 0; i < 6; i++)
718 for (j = 0; j < 0x12; j++)
719 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
721 for (i = 0; i < 0x83; i++)
722 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
726 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
727 * initializes the hardware and our data structures with it.
729 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
730 struct ivhd_header *h)
733 u8 *end = p, flags = 0;
734 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
737 struct ivhd_entry *e;
740 * First save the recommended feature enable bits from ACPI
742 iommu->acpi_flags = h->flags;
745 * Done. Now parse the device entries
747 p += sizeof(struct ivhd_header);
752 e = (struct ivhd_entry *)p;
756 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
757 " last device %02x:%02x.%x flags: %02x\n",
758 PCI_BUS(iommu->first_device),
759 PCI_SLOT(iommu->first_device),
760 PCI_FUNC(iommu->first_device),
761 PCI_BUS(iommu->last_device),
762 PCI_SLOT(iommu->last_device),
763 PCI_FUNC(iommu->last_device),
766 for (dev_i = iommu->first_device;
767 dev_i <= iommu->last_device; ++dev_i)
768 set_dev_entry_from_acpi(iommu, dev_i,
771 case IVHD_DEV_SELECT:
773 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
781 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
783 case IVHD_DEV_SELECT_RANGE_START:
785 DUMP_printk(" DEV_SELECT_RANGE_START\t "
786 "devid: %02x:%02x.%x flags: %02x\n",
792 devid_start = e->devid;
799 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
800 "flags: %02x devid_to: %02x:%02x.%x\n",
805 PCI_BUS(e->ext >> 8),
806 PCI_SLOT(e->ext >> 8),
807 PCI_FUNC(e->ext >> 8));
810 devid_to = e->ext >> 8;
811 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
812 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
813 amd_iommu_alias_table[devid] = devid_to;
815 case IVHD_DEV_ALIAS_RANGE:
817 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
818 "devid: %02x:%02x.%x flags: %02x "
819 "devid_to: %02x:%02x.%x\n",
824 PCI_BUS(e->ext >> 8),
825 PCI_SLOT(e->ext >> 8),
826 PCI_FUNC(e->ext >> 8));
828 devid_start = e->devid;
830 devid_to = e->ext >> 8;
834 case IVHD_DEV_EXT_SELECT:
836 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
837 "flags: %02x ext: %08x\n",
844 set_dev_entry_from_acpi(iommu, devid, e->flags,
847 case IVHD_DEV_EXT_SELECT_RANGE:
849 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
850 "%02x:%02x.%x flags: %02x ext: %08x\n",
856 devid_start = e->devid;
861 case IVHD_DEV_RANGE_END:
863 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
869 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
871 amd_iommu_alias_table[dev_i] = devid_to;
872 set_dev_entry_from_acpi(iommu,
873 devid_to, flags, ext_flags);
875 set_dev_entry_from_acpi(iommu, dev_i,
883 p += ivhd_entry_length(p);
887 /* Initializes the device->iommu mapping for the driver */
888 static int __init init_iommu_devices(struct amd_iommu *iommu)
892 for (i = iommu->first_device; i <= iommu->last_device; ++i)
893 set_iommu_for_device(iommu, i);
898 static void __init free_iommu_one(struct amd_iommu *iommu)
900 free_command_buffer(iommu);
901 free_event_buffer(iommu);
902 iommu_unmap_mmio_space(iommu);
905 static void __init free_iommu_all(void)
907 struct amd_iommu *iommu, *next;
909 for_each_iommu_safe(iommu, next) {
910 list_del(&iommu->list);
911 free_iommu_one(iommu);
917 * This function clues the initialization function for one IOMMU
918 * together and also allocates the command buffer and programs the
919 * hardware. It does NOT enable the IOMMU. This is done afterwards.
921 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
923 spin_lock_init(&iommu->lock);
925 /* Add IOMMU to internal data structures */
926 list_add_tail(&iommu->list, &amd_iommu_list);
927 iommu->index = amd_iommus_present++;
929 if (unlikely(iommu->index >= MAX_IOMMUS)) {
930 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
934 /* Index is fine - add IOMMU to the array */
935 amd_iommus[iommu->index] = iommu;
938 * Copy data from ACPI table entry to the iommu struct
940 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
944 iommu->cap_ptr = h->cap_ptr;
945 iommu->pci_seg = h->pci_seg;
946 iommu->mmio_phys = h->mmio_phys;
947 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
948 if (!iommu->mmio_base)
951 iommu->cmd_buf = alloc_command_buffer(iommu);
955 iommu->evt_buf = alloc_event_buffer(iommu);
959 iommu->int_enabled = false;
961 init_iommu_from_pci(iommu);
962 init_iommu_from_acpi(iommu, h);
963 init_iommu_devices(iommu);
965 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
966 amd_iommu_np_cache = true;
968 return pci_enable_device(iommu->dev);
972 * Iterates over all IOMMU entries in the ACPI table, allocates the
973 * IOMMU structure and initializes it with init_iommu_one()
975 static int __init init_iommu_all(struct acpi_table_header *table)
977 u8 *p = (u8 *)table, *end = (u8 *)table;
978 struct ivhd_header *h;
979 struct amd_iommu *iommu;
982 end += table->length;
983 p += IVRS_HEADER_LENGTH;
986 h = (struct ivhd_header *)p;
990 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
991 "seg: %d flags: %01x info %04x\n",
992 PCI_BUS(h->devid), PCI_SLOT(h->devid),
993 PCI_FUNC(h->devid), h->cap_ptr,
994 h->pci_seg, h->flags, h->info);
995 DUMP_printk(" mmio-addr: %016llx\n",
998 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1000 amd_iommu_init_err = -ENOMEM;
1004 ret = init_iommu_one(iommu, h);
1006 amd_iommu_init_err = ret;
1021 /****************************************************************************
1023 * The following functions initialize the MSI interrupts for all IOMMUs
1024 * in the system. Its a bit challenging because there could be multiple
1025 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1028 ****************************************************************************/
1030 static int iommu_setup_msi(struct amd_iommu *iommu)
1034 if (pci_enable_msi(iommu->dev))
1037 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
1043 pci_disable_msi(iommu->dev);
1047 iommu->int_enabled = true;
1048 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1053 static int iommu_init_msi(struct amd_iommu *iommu)
1055 if (iommu->int_enabled)
1058 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1059 return iommu_setup_msi(iommu);
1064 /****************************************************************************
1066 * The next functions belong to the third pass of parsing the ACPI
1067 * table. In this last pass the memory mapping requirements are
1068 * gathered (like exclusion and unity mapping reanges).
1070 ****************************************************************************/
1072 static void __init free_unity_maps(void)
1074 struct unity_map_entry *entry, *next;
1076 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1077 list_del(&entry->list);
1082 /* called when we find an exclusion range definition in ACPI */
1083 static int __init init_exclusion_range(struct ivmd_header *m)
1088 case ACPI_IVMD_TYPE:
1089 set_device_exclusion_range(m->devid, m);
1091 case ACPI_IVMD_TYPE_ALL:
1092 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1093 set_device_exclusion_range(i, m);
1095 case ACPI_IVMD_TYPE_RANGE:
1096 for (i = m->devid; i <= m->aux; ++i)
1097 set_device_exclusion_range(i, m);
1106 /* called for unity map ACPI definition */
1107 static int __init init_unity_map_range(struct ivmd_header *m)
1109 struct unity_map_entry *e = 0;
1112 e = kzalloc(sizeof(*e), GFP_KERNEL);
1120 case ACPI_IVMD_TYPE:
1121 s = "IVMD_TYPEi\t\t\t";
1122 e->devid_start = e->devid_end = m->devid;
1124 case ACPI_IVMD_TYPE_ALL:
1125 s = "IVMD_TYPE_ALL\t\t";
1127 e->devid_end = amd_iommu_last_bdf;
1129 case ACPI_IVMD_TYPE_RANGE:
1130 s = "IVMD_TYPE_RANGE\t\t";
1131 e->devid_start = m->devid;
1132 e->devid_end = m->aux;
1135 e->address_start = PAGE_ALIGN(m->range_start);
1136 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1137 e->prot = m->flags >> 1;
1139 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1140 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1141 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1142 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1143 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1144 e->address_start, e->address_end, m->flags);
1146 list_add_tail(&e->list, &amd_iommu_unity_map);
1151 /* iterates over all memory definitions we find in the ACPI table */
1152 static int __init init_memory_definitions(struct acpi_table_header *table)
1154 u8 *p = (u8 *)table, *end = (u8 *)table;
1155 struct ivmd_header *m;
1157 end += table->length;
1158 p += IVRS_HEADER_LENGTH;
1161 m = (struct ivmd_header *)p;
1162 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1163 init_exclusion_range(m);
1164 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1165 init_unity_map_range(m);
1174 * Init the device table to not allow DMA access for devices and
1175 * suppress all page faults
1177 static void init_device_table(void)
1181 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1182 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1183 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1187 static void iommu_init_flags(struct amd_iommu *iommu)
1189 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1190 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1191 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1193 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1194 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1195 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1197 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1198 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1199 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1201 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1202 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1203 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1206 * make IOMMU memory accesses cache coherent
1208 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1211 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1214 u32 ioc_feature_control;
1215 struct pci_dev *pdev = NULL;
1217 /* RD890 BIOSes may not have completely reconfigured the iommu */
1218 if (!is_rd890_iommu(iommu->dev))
1222 * First, we need to ensure that the iommu is enabled. This is
1223 * controlled by a register in the northbridge
1225 pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
1230 /* Select Northbridge indirect register 0x75 and enable writing */
1231 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1232 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1234 /* Enable the iommu */
1235 if (!(ioc_feature_control & 0x1))
1236 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1240 /* Restore the iommu BAR */
1241 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1242 iommu->stored_addr_lo);
1243 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1244 iommu->stored_addr_hi);
1246 /* Restore the l1 indirect regs for each of the 6 l1s */
1247 for (i = 0; i < 6; i++)
1248 for (j = 0; j < 0x12; j++)
1249 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1251 /* Restore the l2 indirect regs */
1252 for (i = 0; i < 0x83; i++)
1253 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1255 /* Lock PCI setup registers */
1256 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1257 iommu->stored_addr_lo | 1);
1261 * This function finally enables all IOMMUs found in the system after
1262 * they have been initialized
1264 static void enable_iommus(void)
1266 struct amd_iommu *iommu;
1268 for_each_iommu(iommu) {
1269 iommu_disable(iommu);
1270 iommu_init_flags(iommu);
1271 iommu_set_device_table(iommu);
1272 iommu_enable_command_buffer(iommu);
1273 iommu_enable_event_buffer(iommu);
1274 iommu_set_exclusion_range(iommu);
1275 iommu_init_msi(iommu);
1276 iommu_enable(iommu);
1277 iommu_flush_all_caches(iommu);
1281 static void disable_iommus(void)
1283 struct amd_iommu *iommu;
1285 for_each_iommu(iommu)
1286 iommu_disable(iommu);
1290 * Suspend/Resume support
1291 * disable suspend until real resume implemented
1294 static void amd_iommu_resume(void)
1296 struct amd_iommu *iommu;
1298 for_each_iommu(iommu)
1299 iommu_apply_resume_quirks(iommu);
1301 /* re-load the hardware */
1305 * we have to flush after the IOMMUs are enabled because a
1306 * disabled IOMMU will never execute the commands we send
1308 for_each_iommu(iommu)
1309 iommu_flush_all_caches(iommu);
1312 static int amd_iommu_suspend(void)
1314 /* disable IOMMUs to go out of the way for BIOS */
1320 static struct syscore_ops amd_iommu_syscore_ops = {
1321 .suspend = amd_iommu_suspend,
1322 .resume = amd_iommu_resume,
1326 * This is the core init function for AMD IOMMU hardware in the system.
1327 * This function is called from the generic x86 DMA layer initialization
1330 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1333 * 1 pass) Find the highest PCI device id the driver has to handle.
1334 * Upon this information the size of the data structures is
1335 * determined that needs to be allocated.
1337 * 2 pass) Initialize the data structures just allocated with the
1338 * information in the ACPI table about available AMD IOMMUs
1339 * in the system. It also maps the PCI devices in the
1340 * system to specific IOMMUs
1342 * 3 pass) After the basic data structures are allocated and
1343 * initialized we update them with information about memory
1344 * remapping requirements parsed out of the ACPI table in
1347 * After that the hardware is initialized and ready to go. In the last
1348 * step we do some Linux specific things like registering the driver in
1349 * the dma_ops interface and initializing the suspend/resume support
1350 * functions. Finally it prints some information about AMD IOMMUs and
1351 * the driver state and enables the hardware.
1353 static int __init amd_iommu_init(void)
1358 * First parse ACPI tables to find the largest Bus/Dev/Func
1359 * we need to handle. Upon this information the shared data
1360 * structures for the IOMMUs in the system will be allocated
1362 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1365 ret = amd_iommu_init_err;
1369 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1370 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1371 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1375 /* Device table - directly used by all IOMMUs */
1376 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1377 get_order(dev_table_size));
1378 if (amd_iommu_dev_table == NULL)
1382 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1383 * IOMMU see for that device
1385 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1386 get_order(alias_table_size));
1387 if (amd_iommu_alias_table == NULL)
1390 /* IOMMU rlookup table - find the IOMMU for a specific device */
1391 amd_iommu_rlookup_table = (void *)__get_free_pages(
1392 GFP_KERNEL | __GFP_ZERO,
1393 get_order(rlookup_table_size));
1394 if (amd_iommu_rlookup_table == NULL)
1397 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1398 GFP_KERNEL | __GFP_ZERO,
1399 get_order(MAX_DOMAIN_ID/8));
1400 if (amd_iommu_pd_alloc_bitmap == NULL)
1403 /* init the device table */
1404 init_device_table();
1407 * let all alias entries point to itself
1409 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1410 amd_iommu_alias_table[i] = i;
1413 * never allocate domain 0 because its used as the non-allocated and
1414 * error value placeholder
1416 amd_iommu_pd_alloc_bitmap[0] = 1;
1418 spin_lock_init(&amd_iommu_pd_lock);
1421 * now the data structures are allocated and basically initialized
1422 * start the real acpi table scan
1425 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1428 if (amd_iommu_init_err) {
1429 ret = amd_iommu_init_err;
1433 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1436 if (amd_iommu_init_err) {
1437 ret = amd_iommu_init_err;
1441 ret = amd_iommu_init_devices();
1447 if (iommu_pass_through)
1448 ret = amd_iommu_init_passthrough();
1450 ret = amd_iommu_init_dma_ops();
1455 amd_iommu_init_api();
1457 amd_iommu_init_notifier();
1459 register_syscore_ops(&amd_iommu_syscore_ops);
1461 if (iommu_pass_through)
1464 if (amd_iommu_unmap_flush)
1465 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1467 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1469 x86_platform.iommu_shutdown = disable_iommus;
1477 amd_iommu_uninit_devices();
1479 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1480 get_order(MAX_DOMAIN_ID/8));
1482 free_pages((unsigned long)amd_iommu_rlookup_table,
1483 get_order(rlookup_table_size));
1485 free_pages((unsigned long)amd_iommu_alias_table,
1486 get_order(alias_table_size));
1488 free_pages((unsigned long)amd_iommu_dev_table,
1489 get_order(dev_table_size));
1495 #ifdef CONFIG_GART_IOMMU
1497 * We failed to initialize the AMD IOMMU - try fallback to GART
1507 /****************************************************************************
1509 * Early detect code. This code runs at IOMMU detection time in the DMA
1510 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1513 ****************************************************************************/
1514 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1519 int __init amd_iommu_detect(void)
1521 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1524 if (amd_iommu_disabled)
1527 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1529 amd_iommu_detected = 1;
1530 x86_init.iommu.iommu_init = amd_iommu_init;
1532 /* Make sure ACS will be enabled */
1539 /****************************************************************************
1541 * Parsing functions for the AMD IOMMU specific kernel command line
1544 ****************************************************************************/
1546 static int __init parse_amd_iommu_dump(char *str)
1548 amd_iommu_dump = true;
1553 static int __init parse_amd_iommu_options(char *str)
1555 for (; *str; ++str) {
1556 if (strncmp(str, "fullflush", 9) == 0)
1557 amd_iommu_unmap_flush = true;
1558 if (strncmp(str, "off", 3) == 0)
1559 amd_iommu_disabled = true;
1565 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1566 __setup("amd_iommu=", parse_amd_iommu_options);
1568 IOMMU_INIT_FINISH(amd_iommu_detect,
1569 gart_iommu_hole_init,