1 // SPDX-License-Identifier: GPL-2.0-only
3 * Dynamic DMA mapping support for AMD Hammer.
5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
6 * This allows to use PCI devices that only support 32bit addresses on systems
9 * See Documentation/DMA-API-HOWTO.txt for the interface specification.
11 * Copyright 2002 Andi Kleen, SuSE Labs.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/string.h>
22 #include <linux/spinlock.h>
23 #include <linux/pci.h>
24 #include <linux/topology.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitmap.h>
27 #include <linux/kdebug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/iommu-helper.h>
30 #include <linux/syscore_ops.h>
32 #include <linux/gfp.h>
33 #include <linux/atomic.h>
34 #include <linux/dma-direct.h>
36 #include <asm/proto.h>
37 #include <asm/iommu.h>
39 #include <asm/set_memory.h>
40 #include <asm/swiotlb.h>
42 #include <asm/amd_nb.h>
43 #include <asm/x86_init.h>
44 #include <asm/iommu_table.h>
46 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
47 static unsigned long iommu_size; /* size of remapping area bytes */
48 static unsigned long iommu_pages; /* .. and in pages */
50 static u32 *iommu_gatt_base; /* Remapping table */
53 * If this is disabled the IOMMU will use an optimized flushing strategy
54 * of only flushing when an mapping is reused. With it true the GART is
55 * flushed for every mapping. Problem is that doing the lazy flush seems
56 * to trigger bugs with some popular PCI cards, in particular 3ware (but
57 * has been also also seen with Qlogic at least).
59 static int iommu_fullflush = 1;
61 /* Allocation bitmap for the remapping area: */
62 static DEFINE_SPINLOCK(iommu_bitmap_lock);
63 /* Guarded by iommu_bitmap_lock: */
64 static unsigned long *iommu_gart_bitmap;
66 static u32 gart_unmapped_entry;
69 #define GPTE_COHERENT 2
70 #define GPTE_ENCODE(x) \
71 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
72 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
75 #define AGPEXTERN extern
80 /* GART can only remap to physical addresses < 1TB */
81 #define GART_MAX_PHYS_ADDR (1ULL << 40)
83 /* backdoor interface to AGP driver */
84 AGPEXTERN int agp_memory_reserved;
85 AGPEXTERN __u32 *agp_gatt_table;
87 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
88 static bool need_flush; /* global flush state. set for each gart wrap */
90 static unsigned long alloc_iommu(struct device *dev, int size,
91 unsigned long align_mask)
93 unsigned long offset, flags;
94 unsigned long boundary_size;
95 unsigned long base_index;
97 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
98 PAGE_SIZE) >> PAGE_SHIFT;
99 boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1,
100 PAGE_SIZE) >> PAGE_SHIFT;
102 spin_lock_irqsave(&iommu_bitmap_lock, flags);
103 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
104 size, base_index, boundary_size, align_mask);
107 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
108 size, base_index, boundary_size,
112 next_bit = offset+size;
113 if (next_bit >= iommu_pages) {
120 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
125 static void free_iommu(unsigned long offset, int size)
129 spin_lock_irqsave(&iommu_bitmap_lock, flags);
130 bitmap_clear(iommu_gart_bitmap, offset, size);
131 if (offset >= next_bit)
132 next_bit = offset + size;
133 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
137 * Use global flush state to avoid races with multiple flushers.
139 static void flush_gart(void)
143 spin_lock_irqsave(&iommu_bitmap_lock, flags);
148 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
151 #ifdef CONFIG_IOMMU_LEAK
152 /* Debugging aid for drivers that don't free their IOMMU tables */
153 static void dump_leak(void)
161 show_stack(NULL, NULL, KERN_ERR);
162 debug_dma_dump_mappings(NULL);
166 static void iommu_full(struct device *dev, size_t size, int dir)
169 * Ran out of IOMMU space for this operation. This is very bad.
170 * Unfortunately the drivers cannot handle this operation properly.
171 * Return some non mapped prereserved space in the aperture and
172 * let the Northbridge deal with it. This will result in garbage
173 * in the IO operation. When the size exceeds the prereserved space
174 * memory corruption will occur or random memory will be DMAed
175 * out. Hopefully no network devices use single mappings that big.
178 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
179 #ifdef CONFIG_IOMMU_LEAK
185 need_iommu(struct device *dev, unsigned long addr, size_t size)
187 return force_iommu || !dma_capable(dev, addr, size, true);
191 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
193 return !dma_capable(dev, addr, size, true);
196 /* Map a single continuous physical area into the IOMMU.
197 * Caller needs to check if the iommu is needed and flush.
199 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
200 size_t size, int dir, unsigned long align_mask)
202 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
203 unsigned long iommu_page;
206 if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR))
207 return DMA_MAPPING_ERROR;
209 iommu_page = alloc_iommu(dev, npages, align_mask);
210 if (iommu_page == -1) {
211 if (!nonforced_iommu(dev, phys_mem, size))
213 if (panic_on_overflow)
214 panic("dma_map_area overflow %lu bytes\n", size);
215 iommu_full(dev, size, dir);
216 return DMA_MAPPING_ERROR;
219 for (i = 0; i < npages; i++) {
220 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
221 phys_mem += PAGE_SIZE;
223 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
226 /* Map a single area into the IOMMU */
227 static dma_addr_t gart_map_page(struct device *dev, struct page *page,
228 unsigned long offset, size_t size,
229 enum dma_data_direction dir,
233 phys_addr_t paddr = page_to_phys(page) + offset;
235 if (!need_iommu(dev, paddr, size))
238 bus = dma_map_area(dev, paddr, size, dir, 0);
245 * Free a DMA mapping.
247 static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
248 size_t size, enum dma_data_direction dir,
251 unsigned long iommu_page;
255 if (WARN_ON_ONCE(dma_addr == DMA_MAPPING_ERROR))
259 * This driver will not always use a GART mapping, but might have
260 * created a direct mapping instead. If that is the case there is
261 * nothing to unmap here.
263 if (dma_addr < iommu_bus_base ||
264 dma_addr >= iommu_bus_base + iommu_size)
267 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
268 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
269 for (i = 0; i < npages; i++) {
270 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
272 free_iommu(iommu_page, npages);
276 * Wrapper for pci_unmap_single working with scatterlists.
278 static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
279 enum dma_data_direction dir, unsigned long attrs)
281 struct scatterlist *s;
284 for_each_sg(sg, s, nents, i) {
285 if (!s->dma_length || !s->length)
287 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, 0);
291 /* Fallback for dma_map_sg in case of overflow */
292 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
295 struct scatterlist *s;
298 #ifdef CONFIG_IOMMU_DEBUG
299 pr_debug("dma_map_sg overflow\n");
302 for_each_sg(sg, s, nents, i) {
303 unsigned long addr = sg_phys(s);
305 if (nonforced_iommu(dev, addr, s->length)) {
306 addr = dma_map_area(dev, addr, s->length, dir, 0);
307 if (addr == DMA_MAPPING_ERROR) {
309 gart_unmap_sg(dev, sg, i, dir, 0);
311 sg[0].dma_length = 0;
315 s->dma_address = addr;
316 s->dma_length = s->length;
323 /* Map multiple scatterlist entries continuous into the first. */
324 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
325 int nelems, struct scatterlist *sout,
328 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
329 unsigned long iommu_page = iommu_start;
330 struct scatterlist *s;
333 if (iommu_start == -1)
336 for_each_sg(start, s, nelems, i) {
337 unsigned long pages, addr;
338 unsigned long phys_addr = s->dma_address;
340 BUG_ON(s != start && s->offset);
342 sout->dma_address = iommu_bus_base;
343 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
344 sout->dma_length = s->length;
346 sout->dma_length += s->length;
350 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
352 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
357 BUG_ON(iommu_page - iommu_start != pages);
363 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
364 struct scatterlist *sout, unsigned long pages, int need)
368 sout->dma_address = start->dma_address;
369 sout->dma_length = start->length;
372 return __dma_map_cont(dev, start, nelems, sout, pages);
376 * DMA map all entries in a scatterlist.
377 * Merge chunks that have page aligned sizes into a continuous mapping.
379 static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
380 enum dma_data_direction dir, unsigned long attrs)
382 struct scatterlist *s, *ps, *start_sg, *sgmap;
383 int need = 0, nextneed, i, out, start;
384 unsigned long pages = 0;
385 unsigned int seg_size;
386 unsigned int max_seg_size;
396 max_seg_size = dma_get_max_seg_size(dev);
397 ps = NULL; /* shut up gcc */
399 for_each_sg(sg, s, nents, i) {
400 dma_addr_t addr = sg_phys(s);
402 s->dma_address = addr;
403 BUG_ON(s->length == 0);
405 nextneed = need_iommu(dev, addr, s->length);
407 /* Handle the previous not yet processed entries */
410 * Can only merge when the last chunk ends on a
411 * page boundary and the new one doesn't have an
414 if (!iommu_merge || !nextneed || !need || s->offset ||
415 (s->length + seg_size > max_seg_size) ||
416 (ps->offset + ps->length) % PAGE_SIZE) {
417 if (dma_map_cont(dev, start_sg, i - start,
418 sgmap, pages, need) < 0)
423 sgmap = sg_next(sgmap);
430 seg_size += s->length;
432 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
435 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
440 sgmap = sg_next(sgmap);
441 sgmap->dma_length = 0;
447 gart_unmap_sg(dev, sg, out, dir, 0);
449 /* When it was forced or merged try again in a dumb way */
450 if (force_iommu || iommu_merge) {
451 out = dma_map_sg_nonforce(dev, sg, nents, dir);
455 if (panic_on_overflow)
456 panic("dma_map_sg: overflow on %lu pages\n", pages);
458 iommu_full(dev, pages << PAGE_SHIFT, dir);
459 for_each_sg(sg, s, nents, i)
460 s->dma_address = DMA_MAPPING_ERROR;
464 /* allocate and map a coherent mapping */
466 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
467 gfp_t flag, unsigned long attrs)
471 vaddr = dma_direct_alloc_pages(dev, size, dma_addr, flag, attrs);
473 !force_iommu || dev->coherent_dma_mask <= DMA_BIT_MASK(24))
476 *dma_addr = dma_map_area(dev, virt_to_phys(vaddr), size,
477 DMA_BIDIRECTIONAL, (1UL << get_order(size)) - 1);
479 if (unlikely(*dma_addr == DMA_MAPPING_ERROR))
483 dma_direct_free_pages(dev, size, vaddr, *dma_addr, attrs);
487 /* free a coherent mapping */
489 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
490 dma_addr_t dma_addr, unsigned long attrs)
492 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, 0);
493 dma_direct_free_pages(dev, size, vaddr, dma_addr, attrs);
498 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
503 iommu_size = aper_size;
508 a = aper + iommu_size;
509 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
511 if (iommu_size < 64*1024*1024) {
512 pr_warn("PCI-DMA: Warning: Small IOMMU %luMB."
513 " Consider increasing the AGP aperture in BIOS\n",
520 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
522 unsigned aper_size = 0, aper_base_32, aper_order;
525 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
526 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
527 aper_order = (aper_order >> 1) & 7;
529 aper_base = aper_base_32 & 0x7fff;
532 aper_size = (32 * 1024 * 1024) << aper_order;
533 if (aper_base + aper_size > 0x100000000UL || !aper_size)
540 static void enable_gart_translations(void)
544 if (!amd_nb_has_feature(AMD_NB_GART))
547 for (i = 0; i < amd_nb_num(); i++) {
548 struct pci_dev *dev = node_to_amd_nb(i)->misc;
550 enable_gart_translation(dev, __pa(agp_gatt_table));
553 /* Flush the GART-TLB to remove stale entries */
558 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
559 * resume in the same way as they are handled in gart_iommu_hole_init().
561 static bool fix_up_north_bridges;
562 static u32 aperture_order;
563 static u32 aperture_alloc;
565 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
567 fix_up_north_bridges = true;
568 aperture_order = aper_order;
569 aperture_alloc = aper_alloc;
572 static void gart_fixup_northbridges(void)
576 if (!fix_up_north_bridges)
579 if (!amd_nb_has_feature(AMD_NB_GART))
582 pr_info("PCI-DMA: Restoring GART aperture settings\n");
584 for (i = 0; i < amd_nb_num(); i++) {
585 struct pci_dev *dev = node_to_amd_nb(i)->misc;
588 * Don't enable translations just yet. That is the next
589 * step. Restore the pre-suspend aperture settings.
591 gart_set_size_and_enable(dev, aperture_order);
592 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25);
596 static void gart_resume(void)
598 pr_info("PCI-DMA: Resuming GART IOMMU\n");
600 gart_fixup_northbridges();
602 enable_gart_translations();
605 static struct syscore_ops gart_syscore_ops = {
606 .resume = gart_resume,
611 * Private Northbridge GATT initialization in case we cannot use the
612 * AGP driver for some reason.
614 static __init int init_amd_gatt(struct agp_kern_info *info)
616 unsigned aper_size, gatt_size, new_aper_size;
617 unsigned aper_base, new_aper_base;
622 pr_info("PCI-DMA: Disabling AGP.\n");
624 aper_size = aper_base = info->aper_size = 0;
626 for (i = 0; i < amd_nb_num(); i++) {
627 dev = node_to_amd_nb(i)->misc;
628 new_aper_base = read_aperture(dev, &new_aper_size);
633 aper_size = new_aper_size;
634 aper_base = new_aper_base;
636 if (aper_size != new_aper_size || aper_base != new_aper_base)
642 info->aper_base = aper_base;
643 info->aper_size = aper_size >> 20;
645 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
646 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
647 get_order(gatt_size));
649 panic("Cannot allocate GATT table");
650 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
651 panic("Could not set GART PTEs to uncacheable pages");
653 agp_gatt_table = gatt;
655 register_syscore_ops(&gart_syscore_ops);
659 pr_info("PCI-DMA: aperture base @ %x size %u KB\n",
660 aper_base, aper_size>>10);
665 /* Should not happen anymore */
666 pr_warn("PCI-DMA: More than 4GB of RAM and no IOMMU - falling back to iommu=soft.\n");
670 static const struct dma_map_ops gart_dma_ops = {
671 .map_sg = gart_map_sg,
672 .unmap_sg = gart_unmap_sg,
673 .map_page = gart_map_page,
674 .unmap_page = gart_unmap_page,
675 .alloc = gart_alloc_coherent,
676 .free = gart_free_coherent,
677 .mmap = dma_common_mmap,
678 .get_sgtable = dma_common_get_sgtable,
679 .dma_supported = dma_direct_supported,
680 .get_required_mask = dma_direct_get_required_mask,
683 static void gart_iommu_shutdown(void)
688 /* don't shutdown it if there is AGP installed */
692 if (!amd_nb_has_feature(AMD_NB_GART))
695 for (i = 0; i < amd_nb_num(); i++) {
698 dev = node_to_amd_nb(i)->misc;
699 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
703 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
707 int __init gart_iommu_init(void)
709 struct agp_kern_info info;
710 unsigned long iommu_start;
711 unsigned long aper_base, aper_size;
712 unsigned long start_pfn, end_pfn;
713 unsigned long scratch;
715 if (!amd_nb_has_feature(AMD_NB_GART))
718 #ifndef CONFIG_AGP_AMD64
721 /* Makefile puts PCI initialization via subsys_initcall first. */
722 /* Add other AMD AGP bridge drivers here */
724 (agp_amd64_init() < 0) ||
725 (agp_copy_info(agp_bridge, &info) < 0);
729 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
730 !gart_iommu_aperture ||
731 (no_agp && init_amd_gatt(&info) < 0)) {
732 if (max_pfn > MAX_DMA32_PFN) {
733 pr_warn("More than 4GB of memory but GART IOMMU not available.\n");
734 pr_warn("falling back to iommu=soft.\n");
739 /* need to map that range */
740 aper_size = info.aper_size << 20;
741 aper_base = info.aper_base;
742 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
744 start_pfn = PFN_DOWN(aper_base);
745 if (!pfn_range_is_mapped(start_pfn, end_pfn))
746 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT,
749 pr_info("PCI-DMA: using GART IOMMU.\n");
750 iommu_size = check_iommu_size(info.aper_base, aper_size);
751 iommu_pages = iommu_size >> PAGE_SHIFT;
753 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
754 get_order(iommu_pages/8));
755 if (!iommu_gart_bitmap)
756 panic("Cannot allocate iommu bitmap\n");
758 pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
761 agp_memory_reserved = iommu_size;
762 iommu_start = aper_size - iommu_size;
763 iommu_bus_base = info.aper_base + iommu_start;
764 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
767 * Unmap the IOMMU part of the GART. The alias of the page is
768 * always mapped with cache enabled and there is no full cache
769 * coherency across the GART remapping. The unmapping avoids
770 * automatic prefetches from the CPU allocating cache lines in
771 * there. All CPU accesses are done via the direct mapping to
772 * the backing memory. The GART address is only used by PCI
775 set_memory_np((unsigned long)__va(iommu_bus_base),
776 iommu_size >> PAGE_SHIFT);
778 * Tricky. The GART table remaps the physical memory range,
779 * so the CPU wont notice potential aliases and if the memory
780 * is remapped to UC later on, we might surprise the PCI devices
781 * with a stray writeout of a cacheline. So play it sure and
782 * do an explicit, full-scale wbinvd() _after_ having marked all
783 * the pages as Not-Present:
788 * Now all caches are flushed and we can safely enable
789 * GART hardware. Doing it early leaves the possibility
790 * of stale cache entries that can lead to GART PTE
793 enable_gart_translations();
796 * Try to workaround a bug (thanks to BenH):
797 * Set unmapped entries to a scratch page instead of 0.
798 * Any prefetches that hit unmapped entries won't get an bus abort
799 * then. (P2P bridge may be prefetching on DMA reads).
801 scratch = get_zeroed_page(GFP_KERNEL);
803 panic("Cannot allocate iommu scratch page");
804 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
807 dma_ops = &gart_dma_ops;
808 x86_platform.iommu_shutdown = gart_iommu_shutdown;
814 void __init gart_parse_options(char *p)
818 if (isdigit(*p) && get_option(&p, &arg))
820 if (!strncmp(p, "fullflush", 9))
822 if (!strncmp(p, "nofullflush", 11))
824 if (!strncmp(p, "noagp", 5))
826 if (!strncmp(p, "noaperture", 10))
828 /* duplicated from pci-dma.c */
829 if (!strncmp(p, "force", 5))
830 gart_iommu_aperture_allowed = 1;
831 if (!strncmp(p, "allowed", 7))
832 gart_iommu_aperture_allowed = 1;
833 if (!strncmp(p, "memaper", 7)) {
834 fallback_aper_force = 1;
838 if (get_option(&p, &arg))
839 fallback_aper_order = arg;
843 IOMMU_INIT_POST(gart_iommu_hole_init);