1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
4 #include <linux/module.h>
5 #include <linux/sched.h>
6 #include <linux/perf_event.h>
7 #include <linux/mutex.h>
8 #include <linux/list.h>
9 #include <linux/stringify.h>
10 #include <linux/highmem.h>
12 #include <linux/vmalloc.h>
13 #include <linux/memory.h>
14 #include <linux/stop_machine.h>
15 #include <linux/slab.h>
16 #include <linux/kdebug.h>
17 #include <linux/kprobes.h>
18 #include <linux/mmu_context.h>
19 #include <linux/bsearch.h>
20 #include <linux/sync_core.h>
21 #include <asm/text-patching.h>
22 #include <asm/alternative.h>
23 #include <asm/sections.h>
26 #include <asm/cacheflush.h>
27 #include <asm/tlbflush.h>
30 #include <asm/fixmap.h>
31 #include <asm/paravirt.h>
32 #include <asm/asm-prototypes.h>
35 int __read_mostly alternatives_patched;
37 EXPORT_SYMBOL_GPL(alternatives_patched);
39 #define MAX_PATCH_LEN (255-1)
44 #define DA_RETPOLINE 0x04
48 static unsigned int debug_alternative;
50 static int __init debug_alt(char *str)
52 if (str && *str == '=')
55 if (!str || kstrtouint(str, 0, &debug_alternative))
56 debug_alternative = DA_ALL;
60 __setup("debug-alternative", debug_alt);
62 static int noreplace_smp;
64 static int __init setup_noreplace_smp(char *str)
69 __setup("noreplace-smp", setup_noreplace_smp);
71 #define DPRINTK(type, fmt, args...) \
73 if (debug_alternative & DA_##type) \
74 printk(KERN_DEBUG pr_fmt(fmt) "\n", ##args); \
77 #define DUMP_BYTES(type, buf, len, fmt, args...) \
79 if (unlikely(debug_alternative & DA_##type)) { \
85 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
86 for (j = 0; j < (len) - 1; j++) \
87 printk(KERN_CONT "%02hhx ", buf[j]); \
88 printk(KERN_CONT "%02hhx\n", buf[j]); \
92 static const unsigned char x86nops[] =
109 const unsigned char * const x86_nops[ASM_NOP_MAX+1] =
116 x86nops + 1 + 2 + 3 + 4,
117 x86nops + 1 + 2 + 3 + 4 + 5,
118 x86nops + 1 + 2 + 3 + 4 + 5 + 6,
119 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
121 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
122 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9,
123 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10,
128 * Fill the buffer with a single effective instruction of size @len.
130 * In order not to issue an ORC stack depth tracking CFI entry (Call Frame Info)
131 * for every single-byte NOP, try to generate the maximally available NOP of
132 * size <= ASM_NOP_MAX such that only a single CFI entry is generated (vs one for
133 * each single-byte NOPs). If @len to fill out is > ASM_NOP_MAX, pad with INT3 and
134 * *jump* over instead of executing long and daft NOPs.
136 static void add_nop(u8 *instr, unsigned int len)
138 u8 *target = instr + len;
143 if (len <= ASM_NOP_MAX) {
144 memcpy(instr, x86_nops[len], len);
149 __text_gen_insn(instr, JMP8_INSN_OPCODE, instr, target, JMP8_INSN_SIZE);
150 instr += JMP8_INSN_SIZE;
152 __text_gen_insn(instr, JMP32_INSN_OPCODE, instr, target, JMP32_INSN_SIZE);
153 instr += JMP32_INSN_SIZE;
156 for (;instr < target; instr++)
157 *instr = INT3_INSN_OPCODE;
160 extern s32 __retpoline_sites[], __retpoline_sites_end[];
161 extern s32 __return_sites[], __return_sites_end[];
162 extern s32 __cfi_sites[], __cfi_sites_end[];
163 extern s32 __ibt_endbr_seal[], __ibt_endbr_seal_end[];
164 extern s32 __smp_locks[], __smp_locks_end[];
165 void text_poke_early(void *addr, const void *opcode, size_t len);
168 * Matches NOP and NOPL, not any of the other possible NOPs.
170 static bool insn_is_nop(struct insn *insn)
172 /* Anything NOP, but no REP NOP */
173 if (insn->opcode.bytes[0] == 0x90 &&
174 (!insn->prefixes.nbytes || insn->prefixes.bytes[0] != 0xF3))
178 if (insn->opcode.bytes[0] == 0x0F && insn->opcode.bytes[1] == 0x1F)
181 /* TODO: more nops */
187 * Find the offset of the first non-NOP instruction starting at @offset
188 * but no further than @len.
190 static int skip_nops(u8 *instr, int offset, int len)
194 for (; offset < len; offset += insn.length) {
195 if (insn_decode_kernel(&insn, &instr[offset]))
198 if (!insn_is_nop(&insn))
206 * Optimize a sequence of NOPs, possibly preceded by an unconditional jump
207 * to the end of the NOP sequence into a single NOP.
210 __optimize_nops(u8 *instr, size_t len, struct insn *insn, int *next, int *prev, int *target)
212 int i = *next - insn->length;
214 switch (insn->opcode.bytes[0]) {
215 case JMP8_INSN_OPCODE:
216 case JMP32_INSN_OPCODE:
218 *target = *next + insn->immediate.value;
222 if (insn_is_nop(insn)) {
225 *next = skip_nops(instr, *next, len);
226 if (*target && *next == *target)
229 add_nop(instr + nop, *next - nop);
230 DUMP_BYTES(ALT, instr, len, "%px: [%d:%d) optimized NOPs: ", instr, nop, *next);
239 * "noinline" to cause control flow change and thus invalidate I$ and
240 * cause refetch after modification.
242 static void __init_or_module noinline optimize_nops(u8 *instr, size_t len)
244 int prev, target = 0;
246 for (int next, i = 0; i < len; i = next) {
249 if (insn_decode_kernel(&insn, &instr[i]))
252 next = i + insn.length;
254 __optimize_nops(instr, len, &insn, &next, &prev, &target);
258 static void __init_or_module noinline optimize_nops_inplace(u8 *instr, size_t len)
262 local_irq_save(flags);
263 optimize_nops(instr, len);
265 local_irq_restore(flags);
269 * In this context, "source" is where the instructions are placed in the
270 * section .altinstr_replacement, for example during kernel build by the
272 * "Destination" is where the instructions are being patched in by this
275 * The source offset is:
277 * src_imm = target - src_next_ip (1)
279 * and the target offset is:
281 * dst_imm = target - dst_next_ip (2)
283 * so rework (1) as an expression for target like:
285 * target = src_imm + src_next_ip (1a)
287 * and substitute in (2) to get:
289 * dst_imm = (src_imm + src_next_ip) - dst_next_ip (3)
291 * Now, since the instruction stream is 'identical' at src and dst (it
292 * is being copied after all) it can be stated that:
294 * src_next_ip = src + ip_offset
295 * dst_next_ip = dst + ip_offset (4)
297 * Substitute (4) in (3) and observe ip_offset being cancelled out to
300 * dst_imm = src_imm + (src + ip_offset) - (dst + ip_offset)
301 * = src_imm + src - dst + ip_offset - ip_offset
302 * = src_imm + src - dst (5)
304 * IOW, only the relative displacement of the code block matters.
307 #define apply_reloc_n(n_, p_, d_) \
309 s32 v = *(s##n_ *)(p_); \
311 BUG_ON((v >> 31) != (v >> (n_-1))); \
312 *(s##n_ *)(p_) = (s##n_)v; \
316 static __always_inline
317 void apply_reloc(int n, void *ptr, uintptr_t diff)
320 case 1: apply_reloc_n(8, ptr, diff); break;
321 case 2: apply_reloc_n(16, ptr, diff); break;
322 case 4: apply_reloc_n(32, ptr, diff); break;
327 static __always_inline
328 bool need_reloc(unsigned long offset, u8 *src, size_t src_len)
330 u8 *target = src + offset;
332 * If the target is inside the patched block, it's relative to the
333 * block itself and does not need relocation.
335 return (target < src || target > src + src_len);
338 void apply_relocation(u8 *buf, size_t len, u8 *dest, u8 *src, size_t src_len)
340 int prev, target = 0;
342 for (int next, i = 0; i < len; i = next) {
345 if (WARN_ON_ONCE(insn_decode_kernel(&insn, &buf[i])))
348 next = i + insn.length;
350 if (__optimize_nops(buf, len, &insn, &next, &prev, &target))
353 switch (insn.opcode.bytes[0]) {
355 if (insn.opcode.bytes[1] < 0x80 ||
356 insn.opcode.bytes[1] > 0x8f)
359 fallthrough; /* Jcc.d32 */
360 case 0x70 ... 0x7f: /* Jcc.d8 */
361 case JMP8_INSN_OPCODE:
362 case JMP32_INSN_OPCODE:
363 case CALL_INSN_OPCODE:
364 if (need_reloc(next + insn.immediate.value, src, src_len)) {
365 apply_reloc(insn.immediate.nbytes,
366 buf + i + insn_offset_immediate(&insn),
371 * Where possible, convert JMP.d32 into JMP.d8.
373 if (insn.opcode.bytes[0] == JMP32_INSN_OPCODE) {
374 s32 imm = insn.immediate.value;
376 imm += JMP32_INSN_SIZE - JMP8_INSN_SIZE;
377 if ((imm >> 31) == (imm >> 7)) {
378 buf[i+0] = JMP8_INSN_OPCODE;
381 memset(&buf[i+2], INT3_INSN_OPCODE, insn.length - 2);
387 if (insn_rip_relative(&insn)) {
388 if (need_reloc(next + insn.displacement.value, src, src_len)) {
389 apply_reloc(insn.displacement.nbytes,
390 buf + i + insn_offset_displacement(&insn),
397 /* Low-level backend functions usable from alternative code replacements. */
398 DEFINE_ASM_FUNC(nop_func, "", .entry.text);
399 EXPORT_SYMBOL_GPL(nop_func);
401 noinstr void BUG_func(void)
405 EXPORT_SYMBOL(BUG_func);
407 #define CALL_RIP_REL_OPCODE 0xff
408 #define CALL_RIP_REL_MODRM 0x15
411 * Rewrite the "call BUG_func" replacement to point to the target of the
412 * indirect pv_ops call "call *disp(%ip)".
414 static int alt_replace_call(u8 *instr, u8 *insn_buff, struct alt_instr *a)
416 void *target, *bug = &BUG_func;
419 if (a->replacementlen != 5 || insn_buff[0] != CALL_INSN_OPCODE) {
420 pr_err("ALT_FLAG_DIRECT_CALL set for a non-call replacement instruction\n");
424 if (a->instrlen != 6 ||
425 instr[0] != CALL_RIP_REL_OPCODE ||
426 instr[1] != CALL_RIP_REL_MODRM) {
427 pr_err("ALT_FLAG_DIRECT_CALL set for unrecognized indirect call\n");
431 /* Skip CALL_RIP_REL_OPCODE and CALL_RIP_REL_MODRM */
432 disp = *(s32 *)(instr + 2);
434 /* ff 15 00 00 00 00 call *0x0(%rip) */
435 /* target address is stored at "next instruction + disp". */
436 target = *(void **)(instr + a->instrlen + disp);
438 /* ff 15 00 00 00 00 call *0x0 */
439 /* target address is stored at disp. */
440 target = *(void **)disp;
445 /* (BUG_func - .) + (target - BUG_func) := target - . */
446 *(s32 *)(insn_buff + 1) += target - bug;
448 if (target == &nop_func)
455 * Replace instructions with better alternatives for this CPU type. This runs
456 * before SMP is initialized to avoid SMP problems with self modifying code.
457 * This implies that asymmetric systems where APs have less capabilities than
458 * the boot processor are not handled. Tough. Make sure you disable such
461 * Marked "noinline" to cause control flow change and thus insn cache
462 * to refetch changed I$ lines.
464 void __init_or_module noinline apply_alternatives(struct alt_instr *start,
465 struct alt_instr *end)
468 u8 *instr, *replacement;
469 u8 insn_buff[MAX_PATCH_LEN];
471 DPRINTK(ALT, "alt table %px, -> %px", start, end);
474 * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using
475 * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
476 * During the process, KASAN becomes confused seeing partial LA57
477 * conversion and triggers a false-positive out-of-bound report.
479 * Disable KASAN until the patching is complete.
481 kasan_disable_current();
484 * The scan order should be from start to end. A later scanned
485 * alternative code can overwrite previously scanned alternative code.
486 * Some kernel functions (e.g. memcpy, memset, etc) use this order to
489 * So be careful if you want to change the scan order to any other
492 for (a = start; a < end; a++) {
493 int insn_buff_sz = 0;
495 instr = (u8 *)&a->instr_offset + a->instr_offset;
496 replacement = (u8 *)&a->repl_offset + a->repl_offset;
497 BUG_ON(a->instrlen > sizeof(insn_buff));
498 BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
502 * - feature is present
503 * - feature not present but ALT_FLAG_NOT is set to mean,
504 * patch if feature is *NOT* present.
506 if (!boot_cpu_has(a->cpuid) == !(a->flags & ALT_FLAG_NOT)) {
507 optimize_nops_inplace(instr, a->instrlen);
511 DPRINTK(ALT, "feat: %d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d) flags: 0x%x",
514 instr, instr, a->instrlen,
515 replacement, a->replacementlen, a->flags);
517 memcpy(insn_buff, replacement, a->replacementlen);
518 insn_buff_sz = a->replacementlen;
520 if (a->flags & ALT_FLAG_DIRECT_CALL) {
521 insn_buff_sz = alt_replace_call(instr, insn_buff, a);
522 if (insn_buff_sz < 0)
526 for (; insn_buff_sz < a->instrlen; insn_buff_sz++)
527 insn_buff[insn_buff_sz] = 0x90;
529 apply_relocation(insn_buff, a->instrlen, instr, replacement, a->replacementlen);
531 DUMP_BYTES(ALT, instr, a->instrlen, "%px: old_insn: ", instr);
532 DUMP_BYTES(ALT, replacement, a->replacementlen, "%px: rpl_insn: ", replacement);
533 DUMP_BYTES(ALT, insn_buff, insn_buff_sz, "%px: final_insn: ", instr);
535 text_poke_early(instr, insn_buff, insn_buff_sz);
538 kasan_enable_current();
541 static inline bool is_jcc32(struct insn *insn)
543 /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */
544 return insn->opcode.bytes[0] == 0x0f && (insn->opcode.bytes[1] & 0xf0) == 0x80;
547 #if defined(CONFIG_MITIGATION_RETPOLINE) && defined(CONFIG_OBJTOOL)
552 static int emit_indirect(int op, int reg, u8 *bytes)
558 case CALL_INSN_OPCODE:
559 modrm = 0x10; /* Reg = 2; CALL r/m */
562 case JMP32_INSN_OPCODE:
563 modrm = 0x20; /* Reg = 4; JMP r/m */
572 bytes[i++] = 0x41; /* REX.B prefix */
576 modrm |= 0xc0; /* Mod = 3 */
579 bytes[i++] = 0xff; /* opcode */
585 static int emit_call_track_retpoline(void *addr, struct insn *insn, int reg, u8 *bytes)
587 u8 op = insn->opcode.bytes[0];
591 * Clang does 'weird' Jcc __x86_indirect_thunk_r11 conditional
592 * tail-calls. Deal with them.
594 if (is_jcc32(insn)) {
596 op = insn->opcode.bytes[1];
600 if (insn->length == 6)
601 bytes[i++] = 0x2e; /* CS-prefix */
604 case CALL_INSN_OPCODE:
605 __text_gen_insn(bytes+i, op, addr+i,
606 __x86_indirect_call_thunk_array[reg],
611 case JMP32_INSN_OPCODE:
613 __text_gen_insn(bytes+i, op, addr+i,
614 __x86_indirect_jump_thunk_array[reg],
616 i += JMP32_INSN_SIZE;
620 WARN(1, "%pS %px %*ph\n", addr, addr, 6, addr);
624 WARN_ON_ONCE(i != insn->length);
630 * Rewrite the compiler generated retpoline thunk calls.
632 * For spectre_v2=off (!X86_FEATURE_RETPOLINE), rewrite them into immediate
633 * indirect instructions, avoiding the extra indirection.
635 * For example, convert:
637 * CALL __x86_indirect_thunk_\reg
643 * It also tries to inline spectre_v2=retpoline,lfence when size permits.
645 static int patch_retpoline(void *addr, struct insn *insn, u8 *bytes)
647 retpoline_thunk_t *target;
651 target = addr + insn->length + insn->immediate.value;
652 reg = target - __x86_indirect_thunk_array;
654 if (WARN_ON_ONCE(reg & ~0xf))
657 /* If anyone ever does: CALL/JMP *%rsp, we're in deep trouble. */
660 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) &&
661 !cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
662 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH))
663 return emit_call_track_retpoline(addr, insn, reg, bytes);
668 op = insn->opcode.bytes[0];
673 * Jcc.d32 __x86_indirect_thunk_\reg
683 if (is_jcc32(insn)) {
684 cc = insn->opcode.bytes[1] & 0xf;
685 cc ^= 1; /* invert condition */
687 bytes[i++] = 0x70 + cc; /* Jcc.d8 */
688 bytes[i++] = insn->length - 2; /* sizeof(Jcc.d8) == 2 */
690 /* Continue as if: JMP.d32 __x86_indirect_thunk_\reg */
691 op = JMP32_INSN_OPCODE;
695 * For RETPOLINE_LFENCE: prepend the indirect CALL/JMP with an LFENCE.
697 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
700 bytes[i++] = 0xe8; /* LFENCE */
703 ret = emit_indirect(op, reg, bytes + i);
709 * The compiler is supposed to EMIT an INT3 after every unconditional
710 * JMP instruction due to AMD BTC. However, if the compiler is too old
711 * or MITIGATION_SLS isn't enabled, we still need an INT3 after
712 * indirect JMPs even on Intel.
714 if (op == JMP32_INSN_OPCODE && i < insn->length)
715 bytes[i++] = INT3_INSN_OPCODE;
717 for (; i < insn->length;)
718 bytes[i++] = BYTES_NOP1;
724 * Generated by 'objtool --retpoline'.
726 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end)
730 for (s = start; s < end; s++) {
731 void *addr = (void *)s + *s;
737 ret = insn_decode_kernel(&insn, addr);
738 if (WARN_ON_ONCE(ret < 0))
741 op1 = insn.opcode.bytes[0];
742 op2 = insn.opcode.bytes[1];
745 case CALL_INSN_OPCODE:
746 case JMP32_INSN_OPCODE:
749 case 0x0f: /* escape */
750 if (op2 >= 0x80 && op2 <= 0x8f)
758 DPRINTK(RETPOLINE, "retpoline at: %pS (%px) len: %d to: %pS",
759 addr, addr, insn.length,
760 addr + insn.length + insn.immediate.value);
762 len = patch_retpoline(addr, &insn, bytes);
763 if (len == insn.length) {
764 optimize_nops(bytes, len);
765 DUMP_BYTES(RETPOLINE, ((u8*)addr), len, "%px: orig: ", addr);
766 DUMP_BYTES(RETPOLINE, ((u8*)bytes), len, "%px: repl: ", addr);
767 text_poke_early(addr, bytes, len);
772 #ifdef CONFIG_MITIGATION_RETHUNK
775 * Rewrite the compiler generated return thunk tail-calls.
777 * For example, convert:
779 * JMP __x86_return_thunk
785 static int patch_return(void *addr, struct insn *insn, u8 *bytes)
789 /* Patch the custom return thunks... */
790 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
792 __text_gen_insn(bytes, JMP32_INSN_OPCODE, addr, x86_return_thunk, i);
794 /* ... or patch them out if not needed. */
795 bytes[i++] = RET_INSN_OPCODE;
798 for (; i < insn->length;)
799 bytes[i++] = INT3_INSN_OPCODE;
803 void __init_or_module noinline apply_returns(s32 *start, s32 *end)
807 if (cpu_feature_enabled(X86_FEATURE_RETHUNK))
808 static_call_force_reinit();
810 for (s = start; s < end; s++) {
811 void *dest = NULL, *addr = (void *)s + *s;
817 ret = insn_decode_kernel(&insn, addr);
818 if (WARN_ON_ONCE(ret < 0))
821 op = insn.opcode.bytes[0];
822 if (op == JMP32_INSN_OPCODE)
823 dest = addr + insn.length + insn.immediate.value;
825 if (__static_call_fixup(addr, op, dest) ||
826 WARN_ONCE(dest != &__x86_return_thunk,
827 "missing return thunk: %pS-%pS: %*ph",
828 addr, dest, 5, addr))
831 DPRINTK(RET, "return thunk at: %pS (%px) len: %d to: %pS",
832 addr, addr, insn.length,
833 addr + insn.length + insn.immediate.value);
835 len = patch_return(addr, &insn, bytes);
836 if (len == insn.length) {
837 DUMP_BYTES(RET, ((u8*)addr), len, "%px: orig: ", addr);
838 DUMP_BYTES(RET, ((u8*)bytes), len, "%px: repl: ", addr);
839 text_poke_early(addr, bytes, len);
844 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { }
845 #endif /* CONFIG_MITIGATION_RETHUNK */
847 #else /* !CONFIG_MITIGATION_RETPOLINE || !CONFIG_OBJTOOL */
849 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) { }
850 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { }
852 #endif /* CONFIG_MITIGATION_RETPOLINE && CONFIG_OBJTOOL */
854 #ifdef CONFIG_X86_KERNEL_IBT
856 static void poison_cfi(void *addr);
858 static void __init_or_module poison_endbr(void *addr, bool warn)
860 u32 endbr, poison = gen_endbr_poison();
862 if (WARN_ON_ONCE(get_kernel_nofault(endbr, addr)))
865 if (!is_endbr(endbr)) {
870 DPRINTK(ENDBR, "ENDBR at: %pS (%px)", addr, addr);
873 * When we have IBT, the lack of ENDBR will trigger #CP
875 DUMP_BYTES(ENDBR, ((u8*)addr), 4, "%px: orig: ", addr);
876 DUMP_BYTES(ENDBR, ((u8*)&poison), 4, "%px: repl: ", addr);
877 text_poke_early(addr, &poison, 4);
881 * Generated by: objtool --ibt
883 * Seal the functions for indirect calls by clobbering the ENDBR instructions
884 * and the kCFI hash value.
886 void __init_or_module noinline apply_seal_endbr(s32 *start, s32 *end)
890 for (s = start; s < end; s++) {
891 void *addr = (void *)s + *s;
893 poison_endbr(addr, true);
894 if (IS_ENABLED(CONFIG_FINEIBT))
895 poison_cfi(addr - 16);
901 void __init_or_module apply_seal_endbr(s32 *start, s32 *end) { }
903 #endif /* CONFIG_X86_KERNEL_IBT */
905 #ifdef CONFIG_FINEIBT
906 #define __CFI_DEFAULT CFI_DEFAULT
907 #elif defined(CONFIG_CFI_CLANG)
908 #define __CFI_DEFAULT CFI_KCFI
910 #define __CFI_DEFAULT CFI_OFF
913 enum cfi_mode cfi_mode __ro_after_init = __CFI_DEFAULT;
915 #ifdef CONFIG_CFI_CLANG
918 /* Must match bpf_func_t / DEFINE_BPF_PROG_RUN() */
919 extern unsigned int __bpf_prog_runX(const void *ctx,
920 const struct bpf_insn *insn);
923 * Force a reference to the external symbol so the compiler generates
926 __ADDRESSABLE(__bpf_prog_runX);
928 /* u32 __ro_after_init cfi_bpf_hash = __kcfi_typeid___bpf_prog_runX; */
930 " .pushsection .data..ro_after_init,\"aw\",@progbits \n"
931 " .type cfi_bpf_hash,@object \n"
932 " .globl cfi_bpf_hash \n"
933 " .p2align 2, 0x0 \n"
935 " .long __kcfi_typeid___bpf_prog_runX \n"
936 " .size cfi_bpf_hash, 4 \n"
940 /* Must match bpf_callback_t */
941 extern u64 __bpf_callback_fn(u64, u64, u64, u64, u64);
943 __ADDRESSABLE(__bpf_callback_fn);
945 /* u32 __ro_after_init cfi_bpf_subprog_hash = __kcfi_typeid___bpf_callback_fn; */
947 " .pushsection .data..ro_after_init,\"aw\",@progbits \n"
948 " .type cfi_bpf_subprog_hash,@object \n"
949 " .globl cfi_bpf_subprog_hash \n"
950 " .p2align 2, 0x0 \n"
951 "cfi_bpf_subprog_hash: \n"
952 " .long __kcfi_typeid___bpf_callback_fn \n"
953 " .size cfi_bpf_subprog_hash, 4 \n"
957 u32 cfi_get_func_hash(void *func)
961 func -= cfi_get_offset();
973 if (get_kernel_nofault(hash, func))
980 #ifdef CONFIG_FINEIBT
982 static bool cfi_rand __ro_after_init = true;
983 static u32 cfi_seed __ro_after_init;
986 * Re-hash the CFI hash with a boot-time seed while making sure the result is
987 * not a valid ENDBR instruction.
989 static u32 cfi_rehash(u32 hash)
992 while (unlikely(is_endbr(hash) || is_endbr(-hash))) {
1001 static __init int cfi_parse_cmdline(char *str)
1007 char *next = strchr(str, ',');
1013 if (!strcmp(str, "auto")) {
1014 cfi_mode = CFI_DEFAULT;
1015 } else if (!strcmp(str, "off")) {
1018 } else if (!strcmp(str, "kcfi")) {
1019 cfi_mode = CFI_KCFI;
1020 } else if (!strcmp(str, "fineibt")) {
1021 cfi_mode = CFI_FINEIBT;
1022 } else if (!strcmp(str, "norand")) {
1025 pr_err("Ignoring unknown cfi option (%s).", str);
1033 early_param("cfi", cfi_parse_cmdline);
1038 * __cfi_\func: __cfi_\func:
1039 * movl $0x12345678,%eax // 5 endbr64 // 4
1040 * nop subl $0x12345678,%r10d // 7
1054 * movl $(-0x12345678),%r10d // 6 movl $0x12345678,%r10d // 6
1055 * addl $-15(%r11),%r10d // 4 sub $16,%r11 // 4
1056 * je 1f // 2 nop4 // 4
1058 * 1: call __x86_indirect_thunk_r11 // 5 call *%r11; nop2; // 5
1062 asm( ".pushsection .rodata \n"
1063 "fineibt_preamble_start: \n"
1065 " subl $0x12345678, %r10d \n"
1066 " je fineibt_preamble_end \n"
1069 "fineibt_preamble_end: \n"
1073 extern u8 fineibt_preamble_start[];
1074 extern u8 fineibt_preamble_end[];
1076 #define fineibt_preamble_size (fineibt_preamble_end - fineibt_preamble_start)
1077 #define fineibt_preamble_hash 7
1079 asm( ".pushsection .rodata \n"
1080 "fineibt_caller_start: \n"
1081 " movl $0x12345678, %r10d \n"
1084 "fineibt_caller_end: \n"
1088 extern u8 fineibt_caller_start[];
1089 extern u8 fineibt_caller_end[];
1091 #define fineibt_caller_size (fineibt_caller_end - fineibt_caller_start)
1092 #define fineibt_caller_hash 2
1094 #define fineibt_caller_jmp (fineibt_caller_size - 2)
1096 static u32 decode_preamble_hash(void *addr)
1100 /* b8 78 56 34 12 mov $0x12345678,%eax */
1102 return *(u32 *)(addr + 1);
1104 return 0; /* invalid hash value */
1107 static u32 decode_caller_hash(void *addr)
1111 /* 41 ba 78 56 34 12 mov $0x12345678,%r10d */
1112 if (p[0] == 0x41 && p[1] == 0xba)
1113 return -*(u32 *)(addr + 2);
1115 /* e8 0c 78 56 34 12 jmp.d8 +12 */
1116 if (p[0] == JMP8_INSN_OPCODE && p[1] == fineibt_caller_jmp)
1117 return -*(u32 *)(addr + 2);
1119 return 0; /* invalid hash value */
1122 /* .retpoline_sites */
1123 static int cfi_disable_callers(s32 *start, s32 *end)
1126 * Disable kCFI by patching in a JMP.d8, this leaves the hash immediate
1127 * in tact for later usage. Also see decode_caller_hash() and
1128 * cfi_rewrite_callers().
1130 const u8 jmp[] = { JMP8_INSN_OPCODE, fineibt_caller_jmp };
1133 for (s = start; s < end; s++) {
1134 void *addr = (void *)s + *s;
1137 addr -= fineibt_caller_size;
1138 hash = decode_caller_hash(addr);
1139 if (!hash) /* nocfi callers */
1142 text_poke_early(addr, jmp, 2);
1148 static int cfi_enable_callers(s32 *start, s32 *end)
1151 * Re-enable kCFI, undo what cfi_disable_callers() did.
1153 const u8 mov[] = { 0x41, 0xba };
1156 for (s = start; s < end; s++) {
1157 void *addr = (void *)s + *s;
1160 addr -= fineibt_caller_size;
1161 hash = decode_caller_hash(addr);
1162 if (!hash) /* nocfi callers */
1165 text_poke_early(addr, mov, 2);
1172 static int cfi_rand_preamble(s32 *start, s32 *end)
1176 for (s = start; s < end; s++) {
1177 void *addr = (void *)s + *s;
1180 hash = decode_preamble_hash(addr);
1181 if (WARN(!hash, "no CFI hash found at: %pS %px %*ph\n",
1182 addr, addr, 5, addr))
1185 hash = cfi_rehash(hash);
1186 text_poke_early(addr + 1, &hash, 4);
1192 static int cfi_rewrite_preamble(s32 *start, s32 *end)
1196 for (s = start; s < end; s++) {
1197 void *addr = (void *)s + *s;
1200 hash = decode_preamble_hash(addr);
1201 if (WARN(!hash, "no CFI hash found at: %pS %px %*ph\n",
1202 addr, addr, 5, addr))
1205 text_poke_early(addr, fineibt_preamble_start, fineibt_preamble_size);
1206 WARN_ON(*(u32 *)(addr + fineibt_preamble_hash) != 0x12345678);
1207 text_poke_early(addr + fineibt_preamble_hash, &hash, 4);
1213 static void cfi_rewrite_endbr(s32 *start, s32 *end)
1217 for (s = start; s < end; s++) {
1218 void *addr = (void *)s + *s;
1220 poison_endbr(addr+16, false);
1224 /* .retpoline_sites */
1225 static int cfi_rand_callers(s32 *start, s32 *end)
1229 for (s = start; s < end; s++) {
1230 void *addr = (void *)s + *s;
1233 addr -= fineibt_caller_size;
1234 hash = decode_caller_hash(addr);
1236 hash = -cfi_rehash(hash);
1237 text_poke_early(addr + 2, &hash, 4);
1244 static int cfi_rewrite_callers(s32 *start, s32 *end)
1248 for (s = start; s < end; s++) {
1249 void *addr = (void *)s + *s;
1252 addr -= fineibt_caller_size;
1253 hash = decode_caller_hash(addr);
1255 text_poke_early(addr, fineibt_caller_start, fineibt_caller_size);
1256 WARN_ON(*(u32 *)(addr + fineibt_caller_hash) != 0x12345678);
1257 text_poke_early(addr + fineibt_caller_hash, &hash, 4);
1259 /* rely on apply_retpolines() */
1265 static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
1266 s32 *start_cfi, s32 *end_cfi, bool builtin)
1270 if (WARN_ONCE(fineibt_preamble_size != 16,
1271 "FineIBT preamble wrong size: %ld", fineibt_preamble_size))
1274 if (cfi_mode == CFI_DEFAULT) {
1275 cfi_mode = CFI_KCFI;
1276 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1277 cfi_mode = CFI_FINEIBT;
1281 * Rewrite the callers to not use the __cfi_ stubs, such that we might
1282 * rewrite them. This disables all CFI. If this succeeds but any of the
1283 * later stages fails, we're without CFI.
1285 ret = cfi_disable_callers(start_retpoline, end_retpoline);
1291 cfi_seed = get_random_u32();
1292 cfi_bpf_hash = cfi_rehash(cfi_bpf_hash);
1293 cfi_bpf_subprog_hash = cfi_rehash(cfi_bpf_subprog_hash);
1296 ret = cfi_rand_preamble(start_cfi, end_cfi);
1300 ret = cfi_rand_callers(start_retpoline, end_retpoline);
1308 pr_info("Disabling CFI\n");
1312 ret = cfi_enable_callers(start_retpoline, end_retpoline);
1317 pr_info("Using kCFI\n");
1321 /* place the FineIBT preamble at func()-16 */
1322 ret = cfi_rewrite_preamble(start_cfi, end_cfi);
1326 /* rewrite the callers to target func()-16 */
1327 ret = cfi_rewrite_callers(start_retpoline, end_retpoline);
1331 /* now that nobody targets func()+0, remove ENDBR there */
1332 cfi_rewrite_endbr(start_cfi, end_cfi);
1335 pr_info("Using FineIBT CFI\n");
1343 pr_err("Something went horribly wrong trying to rewrite the CFI implementation.\n");
1346 static inline void poison_hash(void *addr)
1351 static void poison_cfi(void *addr)
1363 poison_endbr(addr, false);
1364 poison_hash(addr + fineibt_preamble_hash);
1373 poison_hash(addr + 1);
1383 static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
1384 s32 *start_cfi, s32 *end_cfi, bool builtin)
1388 #ifdef CONFIG_X86_KERNEL_IBT
1389 static void poison_cfi(void *addr) { }
1394 void apply_fineibt(s32 *start_retpoline, s32 *end_retpoline,
1395 s32 *start_cfi, s32 *end_cfi)
1397 return __apply_fineibt(start_retpoline, end_retpoline,
1399 /* .builtin = */ false);
1403 static void alternatives_smp_lock(const s32 *start, const s32 *end,
1404 u8 *text, u8 *text_end)
1408 for (poff = start; poff < end; poff++) {
1409 u8 *ptr = (u8 *)poff + *poff;
1411 if (!*poff || ptr < text || ptr >= text_end)
1413 /* turn DS segment override prefix into lock prefix */
1415 text_poke(ptr, ((unsigned char []){0xf0}), 1);
1419 static void alternatives_smp_unlock(const s32 *start, const s32 *end,
1420 u8 *text, u8 *text_end)
1424 for (poff = start; poff < end; poff++) {
1425 u8 *ptr = (u8 *)poff + *poff;
1427 if (!*poff || ptr < text || ptr >= text_end)
1429 /* turn lock prefix into DS segment override prefix */
1431 text_poke(ptr, ((unsigned char []){0x3E}), 1);
1435 struct smp_alt_module {
1436 /* what is this ??? */
1440 /* ptrs to lock prefixes */
1442 const s32 *locks_end;
1444 /* .text segment, needed to avoid patching init code ;) */
1448 struct list_head next;
1450 static LIST_HEAD(smp_alt_modules);
1451 static bool uniproc_patched = false; /* protected by text_mutex */
1453 void __init_or_module alternatives_smp_module_add(struct module *mod,
1455 void *locks, void *locks_end,
1456 void *text, void *text_end)
1458 struct smp_alt_module *smp;
1460 mutex_lock(&text_mutex);
1461 if (!uniproc_patched)
1464 if (num_possible_cpus() == 1)
1465 /* Don't bother remembering, we'll never have to undo it. */
1468 smp = kzalloc(sizeof(*smp), GFP_KERNEL);
1470 /* we'll run the (safe but slow) SMP code then ... */
1476 smp->locks_end = locks_end;
1478 smp->text_end = text_end;
1479 DPRINTK(SMP, "locks %p -> %p, text %p -> %p, name %s\n",
1480 smp->locks, smp->locks_end,
1481 smp->text, smp->text_end, smp->name);
1483 list_add_tail(&smp->next, &smp_alt_modules);
1485 alternatives_smp_unlock(locks, locks_end, text, text_end);
1487 mutex_unlock(&text_mutex);
1490 void __init_or_module alternatives_smp_module_del(struct module *mod)
1492 struct smp_alt_module *item;
1494 mutex_lock(&text_mutex);
1495 list_for_each_entry(item, &smp_alt_modules, next) {
1496 if (mod != item->mod)
1498 list_del(&item->next);
1502 mutex_unlock(&text_mutex);
1505 void alternatives_enable_smp(void)
1507 struct smp_alt_module *mod;
1509 /* Why bother if there are no other CPUs? */
1510 BUG_ON(num_possible_cpus() == 1);
1512 mutex_lock(&text_mutex);
1514 if (uniproc_patched) {
1515 pr_info("switching to SMP code\n");
1516 BUG_ON(num_online_cpus() != 1);
1517 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
1518 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
1519 list_for_each_entry(mod, &smp_alt_modules, next)
1520 alternatives_smp_lock(mod->locks, mod->locks_end,
1521 mod->text, mod->text_end);
1522 uniproc_patched = false;
1524 mutex_unlock(&text_mutex);
1528 * Return 1 if the address range is reserved for SMP-alternatives.
1529 * Must hold text_mutex.
1531 int alternatives_text_reserved(void *start, void *end)
1533 struct smp_alt_module *mod;
1535 u8 *text_start = start;
1538 lockdep_assert_held(&text_mutex);
1540 list_for_each_entry(mod, &smp_alt_modules, next) {
1541 if (mod->text > text_end || mod->text_end < text_start)
1543 for (poff = mod->locks; poff < mod->locks_end; poff++) {
1544 const u8 *ptr = (const u8 *)poff + *poff;
1546 if (text_start <= ptr && text_end > ptr)
1553 #endif /* CONFIG_SMP */
1556 * Self-test for the INT3 based CALL emulation code.
1558 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up
1559 * properly and that there is a stack gap between the INT3 frame and the
1560 * previous context. Without this gap doing a virtual PUSH on the interrupted
1561 * stack would corrupt the INT3 IRET frame.
1563 * See entry_{32,64}.S for more details.
1567 * We define the int3_magic() function in assembly to control the calling
1568 * convention such that we can 'call' it from assembly.
1571 extern void int3_magic(unsigned int *ptr); /* defined in asm */
1574 " .pushsection .init.text, \"ax\", @progbits\n"
1575 " .type int3_magic, @function\n"
1578 " movl $1, (%" _ASM_ARG1 ")\n"
1580 " .size int3_magic, .-int3_magic\n"
1584 extern void int3_selftest_ip(void); /* defined in asm below */
1587 int3_exception_notify(struct notifier_block *self, unsigned long val, void *data)
1589 unsigned long selftest = (unsigned long)&int3_selftest_ip;
1590 struct die_args *args = data;
1591 struct pt_regs *regs = args->regs;
1593 OPTIMIZER_HIDE_VAR(selftest);
1595 if (!regs || user_mode(regs))
1598 if (val != DIE_INT3)
1601 if (regs->ip - INT3_INSN_SIZE != selftest)
1604 int3_emulate_call(regs, (unsigned long)&int3_magic);
1608 /* Must be noinline to ensure uniqueness of int3_selftest_ip. */
1609 static noinline void __init int3_selftest(void)
1611 static __initdata struct notifier_block int3_exception_nb = {
1612 .notifier_call = int3_exception_notify,
1613 .priority = INT_MAX-1, /* last */
1615 unsigned int val = 0;
1617 BUG_ON(register_die_notifier(&int3_exception_nb));
1620 * Basically: int3_magic(&val); but really complicated :-)
1622 * INT3 padded with NOP to CALL_INSN_SIZE. The int3_exception_nb
1623 * notifier above will emulate CALL for us.
1625 asm volatile ("int3_selftest_ip:\n\t"
1627 " int3; nop; nop; nop; nop\n\t"
1628 : ASM_CALL_CONSTRAINT
1629 : __ASM_SEL_RAW(a, D) (&val)
1634 unregister_die_notifier(&int3_exception_nb);
1637 static __initdata int __alt_reloc_selftest_addr;
1639 extern void __init __alt_reloc_selftest(void *arg);
1640 __visible noinline void __init __alt_reloc_selftest(void *arg)
1642 WARN_ON(arg != &__alt_reloc_selftest_addr);
1645 static noinline void __init alt_reloc_selftest(void)
1648 * Tests apply_relocation().
1650 * This has a relative immediate (CALL) in a place other than the first
1651 * instruction and additionally on x86_64 we get a RIP-relative LEA:
1653 * lea 0x0(%rip),%rdi # 5d0: R_X86_64_PC32 .init.data+0x5566c
1654 * call +0 # 5d5: R_X86_64_PLT32 __alt_reloc_selftest-0x4
1656 * Getting this wrong will either crash and burn or tickle the WARN
1659 asm_inline volatile (
1660 ALTERNATIVE("", "lea %[mem], %%" _ASM_ARG1 "; call __alt_reloc_selftest;", X86_FEATURE_ALWAYS)
1662 : [mem] "m" (__alt_reloc_selftest_addr)
1667 void __init alternative_instructions(void)
1672 * The patching is not fully atomic, so try to avoid local
1673 * interruptions that might execute the to be patched code.
1674 * Other CPUs are not running.
1679 * Don't stop machine check exceptions while patching.
1680 * MCEs only happen when something got corrupted and in this
1681 * case we must do something about the corruption.
1682 * Ignoring it is worse than an unlikely patching race.
1683 * Also machine checks tend to be broadcast and if one CPU
1684 * goes into machine check the others follow quickly, so we don't
1685 * expect a machine check to cause undue problems during to code
1690 * Make sure to set (artificial) features depending on used paravirt
1691 * functions which can later influence alternative patching.
1695 __apply_fineibt(__retpoline_sites, __retpoline_sites_end,
1696 __cfi_sites, __cfi_sites_end, true);
1699 * Rewrite the retpolines, must be done before alternatives since
1700 * those can rewrite the retpoline thunks.
1702 apply_retpolines(__retpoline_sites, __retpoline_sites_end);
1703 apply_returns(__return_sites, __return_sites_end);
1705 apply_alternatives(__alt_instructions, __alt_instructions_end);
1708 * Now all calls are established. Apply the call thunks if
1711 callthunks_patch_builtin_calls();
1714 * Seal all functions that do not have their address taken.
1716 apply_seal_endbr(__ibt_endbr_seal, __ibt_endbr_seal_end);
1719 /* Patch to UP if other cpus not imminent. */
1720 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
1721 uniproc_patched = true;
1722 alternatives_smp_module_add(NULL, "core kernel",
1723 __smp_locks, __smp_locks_end,
1727 if (!uniproc_patched || num_possible_cpus() == 1) {
1728 free_init_pages("SMP alternatives",
1729 (unsigned long)__smp_locks,
1730 (unsigned long)__smp_locks_end);
1735 alternatives_patched = 1;
1737 alt_reloc_selftest();
1741 * text_poke_early - Update instructions on a live kernel at boot time
1742 * @addr: address to modify
1743 * @opcode: source of the copy
1744 * @len: length to copy
1746 * When you use this code to patch more than one byte of an instruction
1747 * you need to make sure that other CPUs cannot execute this code in parallel.
1748 * Also no thread must be currently preempted in the middle of these
1749 * instructions. And on the local CPU you need to be protected against NMI or
1750 * MCE handlers seeing an inconsistent instruction while you patch.
1752 void __init_or_module text_poke_early(void *addr, const void *opcode,
1755 unsigned long flags;
1757 if (boot_cpu_has(X86_FEATURE_NX) &&
1758 is_module_text_address((unsigned long)addr)) {
1760 * Modules text is marked initially as non-executable, so the
1761 * code cannot be running and speculative code-fetches are
1762 * prevented. Just change the code.
1764 memcpy(addr, opcode, len);
1766 local_irq_save(flags);
1767 memcpy(addr, opcode, len);
1769 local_irq_restore(flags);
1772 * Could also do a CLFLUSH here to speed up CPU recovery; but
1773 * that causes hangs on some VIA CPUs.
1779 struct mm_struct *mm;
1783 * Using a temporary mm allows to set temporary mappings that are not accessible
1784 * by other CPUs. Such mappings are needed to perform sensitive memory writes
1785 * that override the kernel memory protections (e.g., W^X), without exposing the
1786 * temporary page-table mappings that are required for these write operations to
1787 * other CPUs. Using a temporary mm also allows to avoid TLB shootdowns when the
1788 * mapping is torn down.
1790 * Context: The temporary mm needs to be used exclusively by a single core. To
1791 * harden security IRQs must be disabled while the temporary mm is
1792 * loaded, thereby preventing interrupt handler bugs from overriding
1793 * the kernel memory protection.
1795 static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm)
1797 temp_mm_state_t temp_state;
1799 lockdep_assert_irqs_disabled();
1802 * Make sure not to be in TLB lazy mode, as otherwise we'll end up
1803 * with a stale address space WITHOUT being in lazy mode after
1804 * restoring the previous mm.
1806 if (this_cpu_read(cpu_tlbstate_shared.is_lazy))
1807 leave_mm(smp_processor_id());
1809 temp_state.mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1810 switch_mm_irqs_off(NULL, mm, current);
1813 * If breakpoints are enabled, disable them while the temporary mm is
1814 * used. Userspace might set up watchpoints on addresses that are used
1815 * in the temporary mm, which would lead to wrong signals being sent or
1818 * Note that breakpoints are not disabled selectively, which also causes
1819 * kernel breakpoints (e.g., perf's) to be disabled. This might be
1820 * undesirable, but still seems reasonable as the code that runs in the
1821 * temporary mm should be short.
1823 if (hw_breakpoint_active())
1824 hw_breakpoint_disable();
1829 static inline void unuse_temporary_mm(temp_mm_state_t prev_state)
1831 lockdep_assert_irqs_disabled();
1832 switch_mm_irqs_off(NULL, prev_state.mm, current);
1835 * Restore the breakpoints if they were disabled before the temporary mm
1838 if (hw_breakpoint_active())
1839 hw_breakpoint_restore();
1842 __ro_after_init struct mm_struct *poking_mm;
1843 __ro_after_init unsigned long poking_addr;
1845 static void text_poke_memcpy(void *dst, const void *src, size_t len)
1847 memcpy(dst, src, len);
1850 static void text_poke_memset(void *dst, const void *src, size_t len)
1852 int c = *(const int *)src;
1854 memset(dst, c, len);
1857 typedef void text_poke_f(void *dst, const void *src, size_t len);
1859 static void *__text_poke(text_poke_f func, void *addr, const void *src, size_t len)
1861 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE;
1862 struct page *pages[2] = {NULL};
1863 temp_mm_state_t prev;
1864 unsigned long flags;
1870 * While boot memory allocator is running we cannot use struct pages as
1871 * they are not yet initialized. There is no way to recover.
1873 BUG_ON(!after_bootmem);
1875 if (!core_kernel_text((unsigned long)addr)) {
1876 pages[0] = vmalloc_to_page(addr);
1877 if (cross_page_boundary)
1878 pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
1880 pages[0] = virt_to_page(addr);
1881 WARN_ON(!PageReserved(pages[0]));
1882 if (cross_page_boundary)
1883 pages[1] = virt_to_page(addr + PAGE_SIZE);
1886 * If something went wrong, crash and burn since recovery paths are not
1889 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1]));
1892 * Map the page without the global bit, as TLB flushing is done with
1893 * flush_tlb_mm_range(), which is intended for non-global PTEs.
1895 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL);
1898 * The lock is not really needed, but this allows to avoid open-coding.
1900 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
1903 * This must not fail; preallocated in poking_init().
1907 local_irq_save(flags);
1909 pte = mk_pte(pages[0], pgprot);
1910 set_pte_at(poking_mm, poking_addr, ptep, pte);
1912 if (cross_page_boundary) {
1913 pte = mk_pte(pages[1], pgprot);
1914 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
1918 * Loading the temporary mm behaves as a compiler barrier, which
1919 * guarantees that the PTE will be set at the time memcpy() is done.
1921 prev = use_temporary_mm(poking_mm);
1923 kasan_disable_current();
1924 func((u8 *)poking_addr + offset_in_page(addr), src, len);
1925 kasan_enable_current();
1928 * Ensure that the PTE is only cleared after the instructions of memcpy
1929 * were issued by using a compiler barrier.
1933 pte_clear(poking_mm, poking_addr, ptep);
1934 if (cross_page_boundary)
1935 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1);
1938 * Loading the previous page-table hierarchy requires a serializing
1939 * instruction that already allows the core to see the updated version.
1940 * Xen-PV is assumed to serialize execution in a similar manner.
1942 unuse_temporary_mm(prev);
1945 * Flushing the TLB might involve IPIs, which would require enabled
1946 * IRQs, but not if the mm is not used, as it is in this point.
1948 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr +
1949 (cross_page_boundary ? 2 : 1) * PAGE_SIZE,
1952 if (func == text_poke_memcpy) {
1954 * If the text does not match what we just wrote then something is
1955 * fundamentally screwy; there's nothing we can really do about that.
1957 BUG_ON(memcmp(addr, src, len));
1960 local_irq_restore(flags);
1961 pte_unmap_unlock(ptep, ptl);
1966 * text_poke - Update instructions on a live kernel
1967 * @addr: address to modify
1968 * @opcode: source of the copy
1969 * @len: length to copy
1971 * Only atomic text poke/set should be allowed when not doing early patching.
1972 * It means the size must be writable atomically and the address must be aligned
1973 * in a way that permits an atomic write. It also makes sure we fit on a single
1976 * Note that the caller must ensure that if the modified code is part of a
1977 * module, the module would not be removed during poking. This can be achieved
1978 * by registering a module notifier, and ordering module removal and patching
1981 void *text_poke(void *addr, const void *opcode, size_t len)
1983 lockdep_assert_held(&text_mutex);
1985 return __text_poke(text_poke_memcpy, addr, opcode, len);
1989 * text_poke_kgdb - Update instructions on a live kernel by kgdb
1990 * @addr: address to modify
1991 * @opcode: source of the copy
1992 * @len: length to copy
1994 * Only atomic text poke/set should be allowed when not doing early patching.
1995 * It means the size must be writable atomically and the address must be aligned
1996 * in a way that permits an atomic write. It also makes sure we fit on a single
1999 * Context: should only be used by kgdb, which ensures no other core is running,
2000 * despite the fact it does not hold the text_mutex.
2002 void *text_poke_kgdb(void *addr, const void *opcode, size_t len)
2004 return __text_poke(text_poke_memcpy, addr, opcode, len);
2007 void *text_poke_copy_locked(void *addr, const void *opcode, size_t len,
2010 unsigned long start = (unsigned long)addr;
2013 if (WARN_ON_ONCE(!core_ok && core_kernel_text(start)))
2016 while (patched < len) {
2017 unsigned long ptr = start + patched;
2020 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched);
2022 __text_poke(text_poke_memcpy, (void *)ptr, opcode + patched, s);
2029 * text_poke_copy - Copy instructions into (an unused part of) RX memory
2030 * @addr: address to modify
2031 * @opcode: source of the copy
2032 * @len: length to copy, could be more than 2x PAGE_SIZE
2034 * Not safe against concurrent execution; useful for JITs to dump
2035 * new code blocks into unused regions of RX memory. Can be used in
2036 * conjunction with synchronize_rcu_tasks() to wait for existing
2037 * execution to quiesce after having made sure no existing functions
2038 * pointers are live.
2040 void *text_poke_copy(void *addr, const void *opcode, size_t len)
2042 mutex_lock(&text_mutex);
2043 addr = text_poke_copy_locked(addr, opcode, len, false);
2044 mutex_unlock(&text_mutex);
2049 * text_poke_set - memset into (an unused part of) RX memory
2050 * @addr: address to modify
2051 * @c: the byte to fill the area with
2052 * @len: length to copy, could be more than 2x PAGE_SIZE
2054 * This is useful to overwrite unused regions of RX memory with illegal
2057 void *text_poke_set(void *addr, int c, size_t len)
2059 unsigned long start = (unsigned long)addr;
2062 if (WARN_ON_ONCE(core_kernel_text(start)))
2065 mutex_lock(&text_mutex);
2066 while (patched < len) {
2067 unsigned long ptr = start + patched;
2070 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched);
2072 __text_poke(text_poke_memset, (void *)ptr, (void *)&c, s);
2075 mutex_unlock(&text_mutex);
2079 static void do_sync_core(void *info)
2084 void text_poke_sync(void)
2086 on_each_cpu(do_sync_core, NULL, 1);
2090 * NOTE: crazy scheme to allow patching Jcc.d32 but not increase the size of
2091 * this thing. When len == 6 everything is prefixed with 0x0f and we map
2092 * opcode to Jcc.d8, using len to distinguish.
2094 struct text_poke_loc {
2095 /* addr := _stext + rel_addr */
2100 const u8 text[POKE_MAX_OPCODE_SIZE];
2101 /* see text_poke_bp_batch() */
2105 struct bp_patching_desc {
2106 struct text_poke_loc *vec;
2111 static struct bp_patching_desc bp_desc;
2113 static __always_inline
2114 struct bp_patching_desc *try_get_desc(void)
2116 struct bp_patching_desc *desc = &bp_desc;
2118 if (!raw_atomic_inc_not_zero(&desc->refs))
2124 static __always_inline void put_desc(void)
2126 struct bp_patching_desc *desc = &bp_desc;
2128 smp_mb__before_atomic();
2129 raw_atomic_dec(&desc->refs);
2132 static __always_inline void *text_poke_addr(struct text_poke_loc *tp)
2134 return _stext + tp->rel_addr;
2137 static __always_inline int patch_cmp(const void *key, const void *elt)
2139 struct text_poke_loc *tp = (struct text_poke_loc *) elt;
2141 if (key < text_poke_addr(tp))
2143 if (key > text_poke_addr(tp))
2148 noinstr int poke_int3_handler(struct pt_regs *regs)
2150 struct bp_patching_desc *desc;
2151 struct text_poke_loc *tp;
2155 if (user_mode(regs))
2159 * Having observed our INT3 instruction, we now must observe
2160 * bp_desc with non-zero refcount:
2162 * bp_desc.refs = 1 INT3
2164 * write INT3 if (bp_desc.refs != 0)
2168 desc = try_get_desc();
2173 * Discount the INT3. See text_poke_bp_batch().
2175 ip = (void *) regs->ip - INT3_INSN_SIZE;
2178 * Skip the binary search if there is a single member in the vector.
2180 if (unlikely(desc->nr_entries > 1)) {
2181 tp = __inline_bsearch(ip, desc->vec, desc->nr_entries,
2182 sizeof(struct text_poke_loc),
2188 if (text_poke_addr(tp) != ip)
2194 switch (tp->opcode) {
2195 case INT3_INSN_OPCODE:
2197 * Someone poked an explicit INT3, they'll want to handle it,
2202 case RET_INSN_OPCODE:
2203 int3_emulate_ret(regs);
2206 case CALL_INSN_OPCODE:
2207 int3_emulate_call(regs, (long)ip + tp->disp);
2210 case JMP32_INSN_OPCODE:
2211 case JMP8_INSN_OPCODE:
2212 int3_emulate_jmp(regs, (long)ip + tp->disp);
2215 case 0x70 ... 0x7f: /* Jcc */
2216 int3_emulate_jcc(regs, tp->opcode & 0xf, (long)ip, tp->disp);
2230 #define TP_VEC_MAX (PAGE_SIZE / sizeof(struct text_poke_loc))
2231 static struct text_poke_loc tp_vec[TP_VEC_MAX];
2232 static int tp_vec_nr;
2235 * text_poke_bp_batch() -- update instructions on live kernel on SMP
2236 * @tp: vector of instructions to patch
2237 * @nr_entries: number of entries in the vector
2239 * Modify multi-byte instruction by using int3 breakpoint on SMP.
2240 * We completely avoid stop_machine() here, and achieve the
2241 * synchronization using int3 breakpoint.
2243 * The way it is done:
2244 * - For each entry in the vector:
2245 * - add a int3 trap to the address that will be patched
2247 * - For each entry in the vector:
2248 * - update all but the first byte of the patched range
2250 * - For each entry in the vector:
2251 * - replace the first byte (int3) by the first byte of
2255 static void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries)
2257 unsigned char int3 = INT3_INSN_OPCODE;
2261 lockdep_assert_held(&text_mutex);
2264 bp_desc.nr_entries = nr_entries;
2267 * Corresponds to the implicit memory barrier in try_get_desc() to
2268 * ensure reading a non-zero refcount provides up to date bp_desc data.
2270 atomic_set_release(&bp_desc.refs, 1);
2273 * Function tracing can enable thousands of places that need to be
2274 * updated. This can take quite some time, and with full kernel debugging
2275 * enabled, this could cause the softlockup watchdog to trigger.
2276 * This function gets called every 256 entries added to be patched.
2277 * Call cond_resched() here to make sure that other tasks can get scheduled
2278 * while processing all the functions being patched.
2283 * Corresponding read barrier in int3 notifier for making sure the
2284 * nr_entries and handler are correctly ordered wrt. patching.
2289 * First step: add a int3 trap to the address that will be patched.
2291 for (i = 0; i < nr_entries; i++) {
2292 tp[i].old = *(u8 *)text_poke_addr(&tp[i]);
2293 text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE);
2299 * Second step: update all but the first byte of the patched range.
2301 for (do_sync = 0, i = 0; i < nr_entries; i++) {
2302 u8 old[POKE_MAX_OPCODE_SIZE+1] = { tp[i].old, };
2303 u8 _new[POKE_MAX_OPCODE_SIZE+1];
2304 const u8 *new = tp[i].text;
2305 int len = tp[i].len;
2307 if (len - INT3_INSN_SIZE > 0) {
2308 memcpy(old + INT3_INSN_SIZE,
2309 text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
2310 len - INT3_INSN_SIZE);
2314 memcpy(_new + 1, new, 5);
2318 text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
2319 new + INT3_INSN_SIZE,
2320 len - INT3_INSN_SIZE);
2326 * Emit a perf event to record the text poke, primarily to
2327 * support Intel PT decoding which must walk the executable code
2328 * to reconstruct the trace. The flow up to here is:
2331 * - write instruction tail
2332 * At this point the actual control flow will be through the
2333 * INT3 and handler and not hit the old or new instruction.
2334 * Intel PT outputs FUP/TIP packets for the INT3, so the flow
2335 * can still be decoded. Subsequently:
2336 * - emit RECORD_TEXT_POKE with the new instruction
2338 * - write first byte
2340 * So before the text poke event timestamp, the decoder will see
2341 * either the old instruction flow or FUP/TIP of INT3. After the
2342 * text poke event timestamp, the decoder will see either the
2343 * new instruction flow or FUP/TIP of INT3. Thus decoders can
2344 * use the timestamp as the point at which to modify the
2346 * The old instruction is recorded so that the event can be
2347 * processed forwards or backwards.
2349 perf_event_text_poke(text_poke_addr(&tp[i]), old, len, new, len);
2354 * According to Intel, this core syncing is very likely
2355 * not necessary and we'd be safe even without it. But
2356 * better safe than sorry (plus there's not only Intel).
2362 * Third step: replace the first byte (int3) by the first byte of
2365 for (do_sync = 0, i = 0; i < nr_entries; i++) {
2366 u8 byte = tp[i].text[0];
2371 if (byte == INT3_INSN_OPCODE)
2374 text_poke(text_poke_addr(&tp[i]), &byte, INT3_INSN_SIZE);
2382 * Remove and wait for refs to be zero.
2384 if (!atomic_dec_and_test(&bp_desc.refs))
2385 atomic_cond_read_acquire(&bp_desc.refs, !VAL);
2388 static void text_poke_loc_init(struct text_poke_loc *tp, void *addr,
2389 const void *opcode, size_t len, const void *emulate)
2396 memcpy((void *)tp->text, opcode+i, len-i);
2400 ret = insn_decode_kernel(&insn, emulate);
2403 tp->rel_addr = addr - (void *)_stext;
2405 tp->opcode = insn.opcode.bytes[0];
2407 if (is_jcc32(&insn)) {
2409 * Map Jcc.d32 onto Jcc.d8 and use len to distinguish.
2411 tp->opcode = insn.opcode.bytes[1] - 0x10;
2414 switch (tp->opcode) {
2415 case RET_INSN_OPCODE:
2416 case JMP32_INSN_OPCODE:
2417 case JMP8_INSN_OPCODE:
2419 * Control flow instructions without implied execution of the
2420 * next instruction can be padded with INT3.
2422 for (i = insn.length; i < len; i++)
2423 BUG_ON(tp->text[i] != INT3_INSN_OPCODE);
2427 BUG_ON(len != insn.length);
2430 switch (tp->opcode) {
2431 case INT3_INSN_OPCODE:
2432 case RET_INSN_OPCODE:
2435 case CALL_INSN_OPCODE:
2436 case JMP32_INSN_OPCODE:
2437 case JMP8_INSN_OPCODE:
2438 case 0x70 ... 0x7f: /* Jcc */
2439 tp->disp = insn.immediate.value;
2442 default: /* assume NOP */
2444 case 2: /* NOP2 -- emulate as JMP8+0 */
2445 BUG_ON(memcmp(emulate, x86_nops[len], len));
2446 tp->opcode = JMP8_INSN_OPCODE;
2450 case 5: /* NOP5 -- emulate as JMP32+0 */
2451 BUG_ON(memcmp(emulate, x86_nops[len], len));
2452 tp->opcode = JMP32_INSN_OPCODE;
2456 default: /* unknown instruction */
2464 * We hard rely on the tp_vec being ordered; ensure this is so by flushing
2467 static bool tp_order_fail(void *addr)
2469 struct text_poke_loc *tp;
2474 if (!addr) /* force */
2477 tp = &tp_vec[tp_vec_nr - 1];
2478 if ((unsigned long)text_poke_addr(tp) > (unsigned long)addr)
2484 static void text_poke_flush(void *addr)
2486 if (tp_vec_nr == TP_VEC_MAX || tp_order_fail(addr)) {
2487 text_poke_bp_batch(tp_vec, tp_vec_nr);
2492 void text_poke_finish(void)
2494 text_poke_flush(NULL);
2497 void __ref text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate)
2499 struct text_poke_loc *tp;
2501 text_poke_flush(addr);
2503 tp = &tp_vec[tp_vec_nr++];
2504 text_poke_loc_init(tp, addr, opcode, len, emulate);
2508 * text_poke_bp() -- update instructions on live kernel on SMP
2509 * @addr: address to patch
2510 * @opcode: opcode of new instruction
2511 * @len: length to copy
2512 * @emulate: instruction to be emulated
2514 * Update a single instruction with the vector in the stack, avoiding
2515 * dynamically allocated memory. This function should be used when it is
2516 * not possible to allocate memory.
2518 void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate)
2520 struct text_poke_loc tp;
2522 text_poke_loc_init(&tp, addr, opcode, len, emulate);
2523 text_poke_bp_batch(&tp, 1);