1 // SPDX-License-Identifier: GPL-2.0-only
2 #define pr_fmt(fmt) "SMP alternatives: " fmt
4 #include <linux/module.h>
5 #include <linux/sched.h>
6 #include <linux/mutex.h>
7 #include <linux/list.h>
8 #include <linux/stringify.h>
10 #include <linux/vmalloc.h>
11 #include <linux/memory.h>
12 #include <linux/stop_machine.h>
13 #include <linux/slab.h>
14 #include <linux/kdebug.h>
15 #include <linux/kprobes.h>
16 #include <linux/mmu_context.h>
17 #include <linux/bsearch.h>
18 #include <asm/text-patching.h>
19 #include <asm/alternative.h>
20 #include <asm/sections.h>
23 #include <asm/cacheflush.h>
24 #include <asm/tlbflush.h>
27 #include <asm/fixmap.h>
29 int __read_mostly alternatives_patched;
31 EXPORT_SYMBOL_GPL(alternatives_patched);
33 #define MAX_PATCH_LEN (255-1)
35 static int __initdata_or_module debug_alternative;
37 static int __init debug_alt(char *str)
39 debug_alternative = 1;
42 __setup("debug-alternative", debug_alt);
44 static int noreplace_smp;
46 static int __init setup_noreplace_smp(char *str)
51 __setup("noreplace-smp", setup_noreplace_smp);
53 #define DPRINTK(fmt, args...) \
55 if (debug_alternative) \
56 printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
59 #define DUMP_BYTES(buf, len, fmt, args...) \
61 if (unlikely(debug_alternative)) { \
67 printk(KERN_DEBUG fmt, ##args); \
68 for (j = 0; j < (len) - 1; j++) \
69 printk(KERN_CONT "%02hhx ", buf[j]); \
70 printk(KERN_CONT "%02hhx\n", buf[j]); \
75 * Each GENERIC_NOPX is of X bytes, and defined as an array of bytes
76 * that correspond to that nop. Getting from one nop to the next, we
77 * add to the array the offset that is equal to the sum of all sizes of
78 * nops preceding the one we are after.
80 * Note: The GENERIC_NOP5_ATOMIC is at the end, as it breaks the
81 * nice symmetry of sizes of the previous nops.
83 #if defined(GENERIC_NOP1) && !defined(CONFIG_X86_64)
84 static const unsigned char intelnops[] =
96 static const unsigned char * const intel_nops[ASM_NOP_MAX+2] =
102 intelnops + 1 + 2 + 3,
103 intelnops + 1 + 2 + 3 + 4,
104 intelnops + 1 + 2 + 3 + 4 + 5,
105 intelnops + 1 + 2 + 3 + 4 + 5 + 6,
106 intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
107 intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
112 static const unsigned char k8nops[] =
124 static const unsigned char * const k8_nops[ASM_NOP_MAX+2] =
131 k8nops + 1 + 2 + 3 + 4,
132 k8nops + 1 + 2 + 3 + 4 + 5,
133 k8nops + 1 + 2 + 3 + 4 + 5 + 6,
134 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
135 k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
139 #if defined(K7_NOP1) && !defined(CONFIG_X86_64)
140 static const unsigned char k7nops[] =
152 static const unsigned char * const k7_nops[ASM_NOP_MAX+2] =
159 k7nops + 1 + 2 + 3 + 4,
160 k7nops + 1 + 2 + 3 + 4 + 5,
161 k7nops + 1 + 2 + 3 + 4 + 5 + 6,
162 k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
163 k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
168 static const unsigned char p6nops[] =
180 static const unsigned char * const p6_nops[ASM_NOP_MAX+2] =
187 p6nops + 1 + 2 + 3 + 4,
188 p6nops + 1 + 2 + 3 + 4 + 5,
189 p6nops + 1 + 2 + 3 + 4 + 5 + 6,
190 p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
191 p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
195 /* Initialize these to a safe default */
197 const unsigned char * const *ideal_nops = p6_nops;
199 const unsigned char * const *ideal_nops = intel_nops;
202 void __init arch_init_ideal_nops(void)
204 switch (boot_cpu_data.x86_vendor) {
205 case X86_VENDOR_INTEL:
207 * Due to a decoder implementation quirk, some
208 * specific Intel CPUs actually perform better with
209 * the "k8_nops" than with the SDM-recommended NOPs.
211 if (boot_cpu_data.x86 == 6 &&
212 boot_cpu_data.x86_model >= 0x0f &&
213 boot_cpu_data.x86_model != 0x1c &&
214 boot_cpu_data.x86_model != 0x26 &&
215 boot_cpu_data.x86_model != 0x27 &&
216 boot_cpu_data.x86_model < 0x30) {
217 ideal_nops = k8_nops;
218 } else if (boot_cpu_has(X86_FEATURE_NOPL)) {
219 ideal_nops = p6_nops;
222 ideal_nops = k8_nops;
224 ideal_nops = intel_nops;
229 case X86_VENDOR_HYGON:
230 ideal_nops = p6_nops;
234 if (boot_cpu_data.x86 > 0xf) {
235 ideal_nops = p6_nops;
243 ideal_nops = k8_nops;
245 if (boot_cpu_has(X86_FEATURE_K8))
246 ideal_nops = k8_nops;
247 else if (boot_cpu_has(X86_FEATURE_K7))
248 ideal_nops = k7_nops;
250 ideal_nops = intel_nops;
255 /* Use this to add nops to a buffer, then text_poke the whole buffer. */
256 static void __init_or_module add_nops(void *insns, unsigned int len)
259 unsigned int noplen = len;
260 if (noplen > ASM_NOP_MAX)
261 noplen = ASM_NOP_MAX;
262 memcpy(insns, ideal_nops[noplen], noplen);
268 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
269 extern s32 __smp_locks[], __smp_locks_end[];
270 void text_poke_early(void *addr, const void *opcode, size_t len);
273 * Are we looking at a near JMP with a 1 or 4-byte displacement.
275 static inline bool is_jmp(const u8 opcode)
277 return opcode == 0xeb || opcode == 0xe9;
280 static void __init_or_module
281 recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insn_buff)
283 u8 *next_rip, *tgt_rip;
287 if (a->replacementlen != 5)
290 o_dspl = *(s32 *)(insn_buff + 1);
292 /* next_rip of the replacement JMP */
293 next_rip = repl_insn + a->replacementlen;
294 /* target rip of the replacement JMP */
295 tgt_rip = next_rip + o_dspl;
296 n_dspl = tgt_rip - orig_insn;
298 DPRINTK("target RIP: %px, new_displ: 0x%x", tgt_rip, n_dspl);
300 if (tgt_rip - orig_insn >= 0) {
301 if (n_dspl - 2 <= 127)
305 /* negative offset */
307 if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
317 insn_buff[1] = (s8)n_dspl;
318 add_nops(insn_buff + 2, 3);
327 *(s32 *)&insn_buff[1] = n_dspl;
333 DPRINTK("final displ: 0x%08x, JMP 0x%lx",
334 n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
338 * "noinline" to cause control flow change and thus invalidate I$ and
339 * cause refetch after modification.
341 static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 *instr)
346 for (i = 0; i < a->padlen; i++) {
347 if (instr[i] != 0x90)
351 local_irq_save(flags);
352 add_nops(instr + (a->instrlen - a->padlen), a->padlen);
353 local_irq_restore(flags);
355 DUMP_BYTES(instr, a->instrlen, "%px: [%d:%d) optimized NOPs: ",
356 instr, a->instrlen - a->padlen, a->padlen);
360 * Replace instructions with better alternatives for this CPU type. This runs
361 * before SMP is initialized to avoid SMP problems with self modifying code.
362 * This implies that asymmetric systems where APs have less capabilities than
363 * the boot processor are not handled. Tough. Make sure you disable such
366 * Marked "noinline" to cause control flow change and thus insn cache
367 * to refetch changed I$ lines.
369 void __init_or_module noinline apply_alternatives(struct alt_instr *start,
370 struct alt_instr *end)
373 u8 *instr, *replacement;
374 u8 insn_buff[MAX_PATCH_LEN];
376 DPRINTK("alt table %px, -> %px", start, end);
378 * The scan order should be from start to end. A later scanned
379 * alternative code can overwrite previously scanned alternative code.
380 * Some kernel functions (e.g. memcpy, memset, etc) use this order to
383 * So be careful if you want to change the scan order to any other
386 for (a = start; a < end; a++) {
387 int insn_buff_sz = 0;
389 instr = (u8 *)&a->instr_offset + a->instr_offset;
390 replacement = (u8 *)&a->repl_offset + a->repl_offset;
391 BUG_ON(a->instrlen > sizeof(insn_buff));
392 BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
393 if (!boot_cpu_has(a->cpuid)) {
395 optimize_nops(a, instr);
400 DPRINTK("feat: %d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d), pad: %d",
403 instr, instr, a->instrlen,
404 replacement, a->replacementlen, a->padlen);
406 DUMP_BYTES(instr, a->instrlen, "%px: old_insn: ", instr);
407 DUMP_BYTES(replacement, a->replacementlen, "%px: rpl_insn: ", replacement);
409 memcpy(insn_buff, replacement, a->replacementlen);
410 insn_buff_sz = a->replacementlen;
413 * 0xe8 is a relative jump; fix the offset.
415 * Instruction length is checked before the opcode to avoid
416 * accessing uninitialized bytes for zero-length replacements.
418 if (a->replacementlen == 5 && *insn_buff == 0xe8) {
419 *(s32 *)(insn_buff + 1) += replacement - instr;
420 DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
421 *(s32 *)(insn_buff + 1),
422 (unsigned long)instr + *(s32 *)(insn_buff + 1) + 5);
425 if (a->replacementlen && is_jmp(replacement[0]))
426 recompute_jump(a, instr, replacement, insn_buff);
428 if (a->instrlen > a->replacementlen) {
429 add_nops(insn_buff + a->replacementlen,
430 a->instrlen - a->replacementlen);
431 insn_buff_sz += a->instrlen - a->replacementlen;
433 DUMP_BYTES(insn_buff, insn_buff_sz, "%px: final_insn: ", instr);
435 text_poke_early(instr, insn_buff, insn_buff_sz);
440 static void alternatives_smp_lock(const s32 *start, const s32 *end,
441 u8 *text, u8 *text_end)
445 for (poff = start; poff < end; poff++) {
446 u8 *ptr = (u8 *)poff + *poff;
448 if (!*poff || ptr < text || ptr >= text_end)
450 /* turn DS segment override prefix into lock prefix */
452 text_poke(ptr, ((unsigned char []){0xf0}), 1);
456 static void alternatives_smp_unlock(const s32 *start, const s32 *end,
457 u8 *text, u8 *text_end)
461 for (poff = start; poff < end; poff++) {
462 u8 *ptr = (u8 *)poff + *poff;
464 if (!*poff || ptr < text || ptr >= text_end)
466 /* turn lock prefix into DS segment override prefix */
468 text_poke(ptr, ((unsigned char []){0x3E}), 1);
472 struct smp_alt_module {
473 /* what is this ??? */
477 /* ptrs to lock prefixes */
479 const s32 *locks_end;
481 /* .text segment, needed to avoid patching init code ;) */
485 struct list_head next;
487 static LIST_HEAD(smp_alt_modules);
488 static bool uniproc_patched = false; /* protected by text_mutex */
490 void __init_or_module alternatives_smp_module_add(struct module *mod,
492 void *locks, void *locks_end,
493 void *text, void *text_end)
495 struct smp_alt_module *smp;
497 mutex_lock(&text_mutex);
498 if (!uniproc_patched)
501 if (num_possible_cpus() == 1)
502 /* Don't bother remembering, we'll never have to undo it. */
505 smp = kzalloc(sizeof(*smp), GFP_KERNEL);
507 /* we'll run the (safe but slow) SMP code then ... */
513 smp->locks_end = locks_end;
515 smp->text_end = text_end;
516 DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
517 smp->locks, smp->locks_end,
518 smp->text, smp->text_end, smp->name);
520 list_add_tail(&smp->next, &smp_alt_modules);
522 alternatives_smp_unlock(locks, locks_end, text, text_end);
524 mutex_unlock(&text_mutex);
527 void __init_or_module alternatives_smp_module_del(struct module *mod)
529 struct smp_alt_module *item;
531 mutex_lock(&text_mutex);
532 list_for_each_entry(item, &smp_alt_modules, next) {
533 if (mod != item->mod)
535 list_del(&item->next);
539 mutex_unlock(&text_mutex);
542 void alternatives_enable_smp(void)
544 struct smp_alt_module *mod;
546 /* Why bother if there are no other CPUs? */
547 BUG_ON(num_possible_cpus() == 1);
549 mutex_lock(&text_mutex);
551 if (uniproc_patched) {
552 pr_info("switching to SMP code\n");
553 BUG_ON(num_online_cpus() != 1);
554 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
555 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
556 list_for_each_entry(mod, &smp_alt_modules, next)
557 alternatives_smp_lock(mod->locks, mod->locks_end,
558 mod->text, mod->text_end);
559 uniproc_patched = false;
561 mutex_unlock(&text_mutex);
565 * Return 1 if the address range is reserved for SMP-alternatives.
566 * Must hold text_mutex.
568 int alternatives_text_reserved(void *start, void *end)
570 struct smp_alt_module *mod;
572 u8 *text_start = start;
575 lockdep_assert_held(&text_mutex);
577 list_for_each_entry(mod, &smp_alt_modules, next) {
578 if (mod->text > text_end || mod->text_end < text_start)
580 for (poff = mod->locks; poff < mod->locks_end; poff++) {
581 const u8 *ptr = (const u8 *)poff + *poff;
583 if (text_start <= ptr && text_end > ptr)
590 #endif /* CONFIG_SMP */
592 #ifdef CONFIG_PARAVIRT
593 void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
594 struct paravirt_patch_site *end)
596 struct paravirt_patch_site *p;
597 char insn_buff[MAX_PATCH_LEN];
599 for (p = start; p < end; p++) {
602 BUG_ON(p->len > MAX_PATCH_LEN);
603 /* prep the buffer with the original instructions */
604 memcpy(insn_buff, p->instr, p->len);
605 used = pv_ops.init.patch(p->type, insn_buff, (unsigned long)p->instr, p->len);
607 BUG_ON(used > p->len);
609 /* Pad the rest with nops */
610 add_nops(insn_buff + used, p->len - used);
611 text_poke_early(p->instr, insn_buff, p->len);
614 extern struct paravirt_patch_site __start_parainstructions[],
615 __stop_parainstructions[];
616 #endif /* CONFIG_PARAVIRT */
619 * Self-test for the INT3 based CALL emulation code.
621 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up
622 * properly and that there is a stack gap between the INT3 frame and the
623 * previous context. Without this gap doing a virtual PUSH on the interrupted
624 * stack would corrupt the INT3 IRET frame.
626 * See entry_{32,64}.S for more details.
630 * We define the int3_magic() function in assembly to control the calling
631 * convention such that we can 'call' it from assembly.
634 extern void int3_magic(unsigned int *ptr); /* defined in asm */
637 " .pushsection .init.text, \"ax\", @progbits\n"
638 " .type int3_magic, @function\n"
640 " movl $1, (%" _ASM_ARG1 ")\n"
642 " .size int3_magic, .-int3_magic\n"
646 extern __initdata unsigned long int3_selftest_ip; /* defined in asm below */
649 int3_exception_notify(struct notifier_block *self, unsigned long val, void *data)
651 struct die_args *args = data;
652 struct pt_regs *regs = args->regs;
654 if (!regs || user_mode(regs))
660 if (regs->ip - INT3_INSN_SIZE != int3_selftest_ip)
663 int3_emulate_call(regs, (unsigned long)&int3_magic);
667 static void __init int3_selftest(void)
669 static __initdata struct notifier_block int3_exception_nb = {
670 .notifier_call = int3_exception_notify,
671 .priority = INT_MAX-1, /* last */
673 unsigned int val = 0;
675 BUG_ON(register_die_notifier(&int3_exception_nb));
678 * Basically: int3_magic(&val); but really complicated :-)
680 * Stick the address of the INT3 instruction into int3_selftest_ip,
681 * then trigger the INT3, padded with NOPs to match a CALL instruction
684 asm volatile ("1: int3; nop; nop; nop; nop\n\t"
685 ".pushsection .init.data,\"aw\"\n\t"
686 ".align " __ASM_SEL(4, 8) "\n\t"
687 ".type int3_selftest_ip, @object\n\t"
688 ".size int3_selftest_ip, " __ASM_SEL(4, 8) "\n\t"
689 "int3_selftest_ip:\n\t"
690 __ASM_SEL(.long, .quad) " 1b\n\t"
692 : ASM_CALL_CONSTRAINT
693 : __ASM_SEL_RAW(a, D) (&val)
698 unregister_die_notifier(&int3_exception_nb);
701 void __init alternative_instructions(void)
706 * The patching is not fully atomic, so try to avoid local
707 * interruptions that might execute the to be patched code.
708 * Other CPUs are not running.
713 * Don't stop machine check exceptions while patching.
714 * MCEs only happen when something got corrupted and in this
715 * case we must do something about the corruption.
716 * Ignoring it is worse than an unlikely patching race.
717 * Also machine checks tend to be broadcast and if one CPU
718 * goes into machine check the others follow quickly, so we don't
719 * expect a machine check to cause undue problems during to code
723 apply_alternatives(__alt_instructions, __alt_instructions_end);
726 /* Patch to UP if other cpus not imminent. */
727 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
728 uniproc_patched = true;
729 alternatives_smp_module_add(NULL, "core kernel",
730 __smp_locks, __smp_locks_end,
734 if (!uniproc_patched || num_possible_cpus() == 1) {
735 free_init_pages("SMP alternatives",
736 (unsigned long)__smp_locks,
737 (unsigned long)__smp_locks_end);
741 apply_paravirt(__parainstructions, __parainstructions_end);
744 alternatives_patched = 1;
748 * text_poke_early - Update instructions on a live kernel at boot time
749 * @addr: address to modify
750 * @opcode: source of the copy
751 * @len: length to copy
753 * When you use this code to patch more than one byte of an instruction
754 * you need to make sure that other CPUs cannot execute this code in parallel.
755 * Also no thread must be currently preempted in the middle of these
756 * instructions. And on the local CPU you need to be protected against NMI or
757 * MCE handlers seeing an inconsistent instruction while you patch.
759 void __init_or_module text_poke_early(void *addr, const void *opcode,
764 if (boot_cpu_has(X86_FEATURE_NX) &&
765 is_module_text_address((unsigned long)addr)) {
767 * Modules text is marked initially as non-executable, so the
768 * code cannot be running and speculative code-fetches are
769 * prevented. Just change the code.
771 memcpy(addr, opcode, len);
773 local_irq_save(flags);
774 memcpy(addr, opcode, len);
775 local_irq_restore(flags);
779 * Could also do a CLFLUSH here to speed up CPU recovery; but
780 * that causes hangs on some VIA CPUs.
786 struct mm_struct *mm;
790 * Using a temporary mm allows to set temporary mappings that are not accessible
791 * by other CPUs. Such mappings are needed to perform sensitive memory writes
792 * that override the kernel memory protections (e.g., W^X), without exposing the
793 * temporary page-table mappings that are required for these write operations to
794 * other CPUs. Using a temporary mm also allows to avoid TLB shootdowns when the
795 * mapping is torn down.
797 * Context: The temporary mm needs to be used exclusively by a single core. To
798 * harden security IRQs must be disabled while the temporary mm is
799 * loaded, thereby preventing interrupt handler bugs from overriding
800 * the kernel memory protection.
802 static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm)
804 temp_mm_state_t temp_state;
806 lockdep_assert_irqs_disabled();
807 temp_state.mm = this_cpu_read(cpu_tlbstate.loaded_mm);
808 switch_mm_irqs_off(NULL, mm, current);
811 * If breakpoints are enabled, disable them while the temporary mm is
812 * used. Userspace might set up watchpoints on addresses that are used
813 * in the temporary mm, which would lead to wrong signals being sent or
816 * Note that breakpoints are not disabled selectively, which also causes
817 * kernel breakpoints (e.g., perf's) to be disabled. This might be
818 * undesirable, but still seems reasonable as the code that runs in the
819 * temporary mm should be short.
821 if (hw_breakpoint_active())
822 hw_breakpoint_disable();
827 static inline void unuse_temporary_mm(temp_mm_state_t prev_state)
829 lockdep_assert_irqs_disabled();
830 switch_mm_irqs_off(NULL, prev_state.mm, current);
833 * Restore the breakpoints if they were disabled before the temporary mm
836 if (hw_breakpoint_active())
837 hw_breakpoint_restore();
840 __ro_after_init struct mm_struct *poking_mm;
841 __ro_after_init unsigned long poking_addr;
843 static void *__text_poke(void *addr, const void *opcode, size_t len)
845 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE;
846 struct page *pages[2] = {NULL};
847 temp_mm_state_t prev;
854 * While boot memory allocator is running we cannot use struct pages as
855 * they are not yet initialized. There is no way to recover.
857 BUG_ON(!after_bootmem);
859 if (!core_kernel_text((unsigned long)addr)) {
860 pages[0] = vmalloc_to_page(addr);
861 if (cross_page_boundary)
862 pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
864 pages[0] = virt_to_page(addr);
865 WARN_ON(!PageReserved(pages[0]));
866 if (cross_page_boundary)
867 pages[1] = virt_to_page(addr + PAGE_SIZE);
870 * If something went wrong, crash and burn since recovery paths are not
873 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1]));
875 local_irq_save(flags);
878 * Map the page without the global bit, as TLB flushing is done with
879 * flush_tlb_mm_range(), which is intended for non-global PTEs.
881 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL);
884 * The lock is not really needed, but this allows to avoid open-coding.
886 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
889 * This must not fail; preallocated in poking_init().
893 pte = mk_pte(pages[0], pgprot);
894 set_pte_at(poking_mm, poking_addr, ptep, pte);
896 if (cross_page_boundary) {
897 pte = mk_pte(pages[1], pgprot);
898 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte);
902 * Loading the temporary mm behaves as a compiler barrier, which
903 * guarantees that the PTE will be set at the time memcpy() is done.
905 prev = use_temporary_mm(poking_mm);
907 kasan_disable_current();
908 memcpy((u8 *)poking_addr + offset_in_page(addr), opcode, len);
909 kasan_enable_current();
912 * Ensure that the PTE is only cleared after the instructions of memcpy
913 * were issued by using a compiler barrier.
917 pte_clear(poking_mm, poking_addr, ptep);
918 if (cross_page_boundary)
919 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1);
922 * Loading the previous page-table hierarchy requires a serializing
923 * instruction that already allows the core to see the updated version.
924 * Xen-PV is assumed to serialize execution in a similar manner.
926 unuse_temporary_mm(prev);
929 * Flushing the TLB might involve IPIs, which would require enabled
930 * IRQs, but not if the mm is not used, as it is in this point.
932 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr +
933 (cross_page_boundary ? 2 : 1) * PAGE_SIZE,
937 * If the text does not match what we just wrote then something is
938 * fundamentally screwy; there's nothing we can really do about that.
940 BUG_ON(memcmp(addr, opcode, len));
942 pte_unmap_unlock(ptep, ptl);
943 local_irq_restore(flags);
948 * text_poke - Update instructions on a live kernel
949 * @addr: address to modify
950 * @opcode: source of the copy
951 * @len: length to copy
953 * Only atomic text poke/set should be allowed when not doing early patching.
954 * It means the size must be writable atomically and the address must be aligned
955 * in a way that permits an atomic write. It also makes sure we fit on a single
958 * Note that the caller must ensure that if the modified code is part of a
959 * module, the module would not be removed during poking. This can be achieved
960 * by registering a module notifier, and ordering module removal and patching
963 void *text_poke(void *addr, const void *opcode, size_t len)
965 lockdep_assert_held(&text_mutex);
967 return __text_poke(addr, opcode, len);
971 * text_poke_kgdb - Update instructions on a live kernel by kgdb
972 * @addr: address to modify
973 * @opcode: source of the copy
974 * @len: length to copy
976 * Only atomic text poke/set should be allowed when not doing early patching.
977 * It means the size must be writable atomically and the address must be aligned
978 * in a way that permits an atomic write. It also makes sure we fit on a single
981 * Context: should only be used by kgdb, which ensures no other core is running,
982 * despite the fact it does not hold the text_mutex.
984 void *text_poke_kgdb(void *addr, const void *opcode, size_t len)
986 return __text_poke(addr, opcode, len);
989 static void do_sync_core(void *info)
994 void text_poke_sync(void)
996 on_each_cpu(do_sync_core, NULL, 1);
999 struct text_poke_loc {
1000 s32 rel_addr; /* addr := _stext + rel_addr */
1003 const u8 text[POKE_MAX_OPCODE_SIZE];
1006 struct bp_patching_desc {
1007 struct text_poke_loc *vec;
1012 static struct bp_patching_desc *bp_desc;
1014 static inline struct bp_patching_desc *try_get_desc(struct bp_patching_desc **descp)
1016 struct bp_patching_desc *desc = READ_ONCE(*descp); /* rcu_dereference */
1018 if (!desc || !atomic_inc_not_zero(&desc->refs))
1024 static inline void put_desc(struct bp_patching_desc *desc)
1026 smp_mb__before_atomic();
1027 atomic_dec(&desc->refs);
1030 static inline void *text_poke_addr(struct text_poke_loc *tp)
1032 return _stext + tp->rel_addr;
1035 static int notrace patch_cmp(const void *key, const void *elt)
1037 struct text_poke_loc *tp = (struct text_poke_loc *) elt;
1039 if (key < text_poke_addr(tp))
1041 if (key > text_poke_addr(tp))
1045 NOKPROBE_SYMBOL(patch_cmp);
1047 int notrace poke_int3_handler(struct pt_regs *regs)
1049 struct bp_patching_desc *desc;
1050 struct text_poke_loc *tp;
1054 if (user_mode(regs))
1058 * Having observed our INT3 instruction, we now must observe
1061 * bp_desc = desc INT3
1063 * write INT3 if (desc)
1067 desc = try_get_desc(&bp_desc);
1072 * Discount the INT3. See text_poke_bp_batch().
1074 ip = (void *) regs->ip - INT3_INSN_SIZE;
1077 * Skip the binary search if there is a single member in the vector.
1079 if (unlikely(desc->nr_entries > 1)) {
1080 tp = bsearch(ip, desc->vec, desc->nr_entries,
1081 sizeof(struct text_poke_loc),
1087 if (text_poke_addr(tp) != ip)
1091 len = text_opcode_size(tp->opcode);
1094 switch (tp->opcode) {
1095 case INT3_INSN_OPCODE:
1097 * Someone poked an explicit INT3, they'll want to handle it,
1102 case CALL_INSN_OPCODE:
1103 int3_emulate_call(regs, (long)ip + tp->rel32);
1106 case JMP32_INSN_OPCODE:
1107 case JMP8_INSN_OPCODE:
1108 int3_emulate_jmp(regs, (long)ip + tp->rel32);
1121 NOKPROBE_SYMBOL(poke_int3_handler);
1123 #define TP_VEC_MAX (PAGE_SIZE / sizeof(struct text_poke_loc))
1124 static struct text_poke_loc tp_vec[TP_VEC_MAX];
1125 static int tp_vec_nr;
1128 * text_poke_bp_batch() -- update instructions on live kernel on SMP
1129 * @tp: vector of instructions to patch
1130 * @nr_entries: number of entries in the vector
1132 * Modify multi-byte instruction by using int3 breakpoint on SMP.
1133 * We completely avoid stop_machine() here, and achieve the
1134 * synchronization using int3 breakpoint.
1136 * The way it is done:
1137 * - For each entry in the vector:
1138 * - add a int3 trap to the address that will be patched
1140 * - For each entry in the vector:
1141 * - update all but the first byte of the patched range
1143 * - For each entry in the vector:
1144 * - replace the first byte (int3) by the first byte of
1148 static void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries)
1150 struct bp_patching_desc desc = {
1152 .nr_entries = nr_entries,
1153 .refs = ATOMIC_INIT(1),
1155 unsigned char int3 = INT3_INSN_OPCODE;
1159 lockdep_assert_held(&text_mutex);
1161 smp_store_release(&bp_desc, &desc); /* rcu_assign_pointer */
1164 * Corresponding read barrier in int3 notifier for making sure the
1165 * nr_entries and handler are correctly ordered wrt. patching.
1170 * First step: add a int3 trap to the address that will be patched.
1172 for (i = 0; i < nr_entries; i++)
1173 text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE);
1178 * Second step: update all but the first byte of the patched range.
1180 for (do_sync = 0, i = 0; i < nr_entries; i++) {
1181 int len = text_opcode_size(tp[i].opcode);
1183 if (len - INT3_INSN_SIZE > 0) {
1184 text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE,
1185 (const char *)tp[i].text + INT3_INSN_SIZE,
1186 len - INT3_INSN_SIZE);
1193 * According to Intel, this core syncing is very likely
1194 * not necessary and we'd be safe even without it. But
1195 * better safe than sorry (plus there's not only Intel).
1201 * Third step: replace the first byte (int3) by the first byte of
1204 for (do_sync = 0, i = 0; i < nr_entries; i++) {
1205 if (tp[i].text[0] == INT3_INSN_OPCODE)
1208 text_poke(text_poke_addr(&tp[i]), tp[i].text, INT3_INSN_SIZE);
1216 * Remove and synchronize_rcu(), except we have a very primitive
1217 * refcount based completion.
1219 WRITE_ONCE(bp_desc, NULL); /* RCU_INIT_POINTER */
1220 if (!atomic_dec_and_test(&desc.refs))
1221 atomic_cond_read_acquire(&desc.refs, !VAL);
1224 static void text_poke_loc_init(struct text_poke_loc *tp, void *addr,
1225 const void *opcode, size_t len, const void *emulate)
1229 memcpy((void *)tp->text, opcode, len);
1233 kernel_insn_init(&insn, emulate, MAX_INSN_SIZE);
1234 insn_get_length(&insn);
1236 BUG_ON(!insn_complete(&insn));
1237 BUG_ON(len != insn.length);
1239 tp->rel_addr = addr - (void *)_stext;
1240 tp->opcode = insn.opcode.bytes[0];
1242 switch (tp->opcode) {
1243 case INT3_INSN_OPCODE:
1246 case CALL_INSN_OPCODE:
1247 case JMP32_INSN_OPCODE:
1248 case JMP8_INSN_OPCODE:
1249 tp->rel32 = insn.immediate.value;
1252 default: /* assume NOP */
1254 case 2: /* NOP2 -- emulate as JMP8+0 */
1255 BUG_ON(memcmp(emulate, ideal_nops[len], len));
1256 tp->opcode = JMP8_INSN_OPCODE;
1260 case 5: /* NOP5 -- emulate as JMP32+0 */
1261 BUG_ON(memcmp(emulate, ideal_nops[NOP_ATOMIC5], len));
1262 tp->opcode = JMP32_INSN_OPCODE;
1266 default: /* unknown instruction */
1274 * We hard rely on the tp_vec being ordered; ensure this is so by flushing
1277 static bool tp_order_fail(void *addr)
1279 struct text_poke_loc *tp;
1284 if (!addr) /* force */
1287 tp = &tp_vec[tp_vec_nr - 1];
1288 if ((unsigned long)text_poke_addr(tp) > (unsigned long)addr)
1294 static void text_poke_flush(void *addr)
1296 if (tp_vec_nr == TP_VEC_MAX || tp_order_fail(addr)) {
1297 text_poke_bp_batch(tp_vec, tp_vec_nr);
1302 void text_poke_finish(void)
1304 text_poke_flush(NULL);
1307 void __ref text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate)
1309 struct text_poke_loc *tp;
1311 if (unlikely(system_state == SYSTEM_BOOTING)) {
1312 text_poke_early(addr, opcode, len);
1316 text_poke_flush(addr);
1318 tp = &tp_vec[tp_vec_nr++];
1319 text_poke_loc_init(tp, addr, opcode, len, emulate);
1323 * text_poke_bp() -- update instructions on live kernel on SMP
1324 * @addr: address to patch
1325 * @opcode: opcode of new instruction
1326 * @len: length to copy
1327 * @handler: address to jump to when the temporary breakpoint is hit
1329 * Update a single instruction with the vector in the stack, avoiding
1330 * dynamically allocated memory. This function should be used when it is
1331 * not possible to allocate memory.
1333 void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate)
1335 struct text_poke_loc tp;
1337 if (unlikely(system_state == SYSTEM_BOOTING)) {
1338 text_poke_early(addr, opcode, len);
1342 text_poke_loc_init(&tp, addr, opcode, len, emulate);
1343 text_poke_bp_batch(&tp, 1);