1 #ifndef _ASM_X86_MSR_INDEX_H
2 #define _ASM_X86_MSR_INDEX_H
4 /* CPU model specific register (MSR) numbers */
6 /* x86-64 specific MSRs */
7 #define MSR_EFER 0xc0000080 /* extended feature register */
8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
19 #define _EFER_LME 8 /* Long mode enable */
20 #define _EFER_LMA 10 /* Long mode active (read-only) */
21 #define _EFER_NX 11 /* No execute enable */
22 #define _EFER_SVME 12 /* Enable virtualization */
23 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
24 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
26 #define EFER_SCE (1<<_EFER_SCE)
27 #define EFER_LME (1<<_EFER_LME)
28 #define EFER_LMA (1<<_EFER_LMA)
29 #define EFER_NX (1<<_EFER_NX)
30 #define EFER_SVME (1<<_EFER_SVME)
31 #define EFER_LMSLE (1<<_EFER_LMSLE)
32 #define EFER_FFXSR (1<<_EFER_FFXSR)
34 /* Intel MSRs. Some also available on other CPUs */
35 #define MSR_IA32_PERFCTR0 0x000000c1
36 #define MSR_IA32_PERFCTR1 0x000000c2
37 #define MSR_FSB_FREQ 0x000000cd
38 #define MSR_NHM_PLATFORM_INFO 0x000000ce
40 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
41 #define NHM_C3_AUTO_DEMOTE (1UL << 25)
42 #define NHM_C1_AUTO_DEMOTE (1UL << 26)
43 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
44 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
45 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
47 #define MSR_PLATFORM_INFO 0x000000ce
48 #define MSR_MTRRcap 0x000000fe
49 #define MSR_IA32_BBL_CR_CTL 0x00000119
50 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
52 #define MSR_IA32_SYSENTER_CS 0x00000174
53 #define MSR_IA32_SYSENTER_ESP 0x00000175
54 #define MSR_IA32_SYSENTER_EIP 0x00000176
56 #define MSR_IA32_MCG_CAP 0x00000179
57 #define MSR_IA32_MCG_STATUS 0x0000017a
58 #define MSR_IA32_MCG_CTL 0x0000017b
60 #define MSR_OFFCORE_RSP_0 0x000001a6
61 #define MSR_OFFCORE_RSP_1 0x000001a7
62 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
63 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
65 #define MSR_LBR_SELECT 0x000001c8
66 #define MSR_LBR_TOS 0x000001c9
67 #define MSR_LBR_NHM_FROM 0x00000680
68 #define MSR_LBR_NHM_TO 0x000006c0
69 #define MSR_LBR_CORE_FROM 0x00000040
70 #define MSR_LBR_CORE_TO 0x00000060
72 #define MSR_IA32_PEBS_ENABLE 0x000003f1
73 #define MSR_IA32_DS_AREA 0x00000600
74 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
75 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
77 #define MSR_MTRRfix64K_00000 0x00000250
78 #define MSR_MTRRfix16K_80000 0x00000258
79 #define MSR_MTRRfix16K_A0000 0x00000259
80 #define MSR_MTRRfix4K_C0000 0x00000268
81 #define MSR_MTRRfix4K_C8000 0x00000269
82 #define MSR_MTRRfix4K_D0000 0x0000026a
83 #define MSR_MTRRfix4K_D8000 0x0000026b
84 #define MSR_MTRRfix4K_E0000 0x0000026c
85 #define MSR_MTRRfix4K_E8000 0x0000026d
86 #define MSR_MTRRfix4K_F0000 0x0000026e
87 #define MSR_MTRRfix4K_F8000 0x0000026f
88 #define MSR_MTRRdefType 0x000002ff
90 #define MSR_IA32_CR_PAT 0x00000277
92 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
93 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
94 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
95 #define MSR_IA32_LASTINTFROMIP 0x000001dd
96 #define MSR_IA32_LASTINTTOIP 0x000001de
98 /* DEBUGCTLMSR bits (others vary by model): */
99 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
100 #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
101 #define DEBUGCTLMSR_TR (1UL << 6)
102 #define DEBUGCTLMSR_BTS (1UL << 7)
103 #define DEBUGCTLMSR_BTINT (1UL << 8)
104 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
105 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
106 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
108 #define MSR_IA32_POWER_CTL 0x000001fc
110 #define MSR_IA32_MC0_CTL 0x00000400
111 #define MSR_IA32_MC0_STATUS 0x00000401
112 #define MSR_IA32_MC0_ADDR 0x00000402
113 #define MSR_IA32_MC0_MISC 0x00000403
115 /* C-state Residency Counters */
116 #define MSR_PKG_C3_RESIDENCY 0x000003f8
117 #define MSR_PKG_C6_RESIDENCY 0x000003f9
118 #define MSR_PKG_C7_RESIDENCY 0x000003fa
119 #define MSR_CORE_C3_RESIDENCY 0x000003fc
120 #define MSR_CORE_C6_RESIDENCY 0x000003fd
121 #define MSR_CORE_C7_RESIDENCY 0x000003fe
122 #define MSR_PKG_C2_RESIDENCY 0x0000060d
123 #define MSR_PKG_C8_RESIDENCY 0x00000630
124 #define MSR_PKG_C9_RESIDENCY 0x00000631
125 #define MSR_PKG_C10_RESIDENCY 0x00000632
127 /* Run Time Average Power Limiting (RAPL) Interface */
129 #define MSR_RAPL_POWER_UNIT 0x00000606
131 #define MSR_PKG_POWER_LIMIT 0x00000610
132 #define MSR_PKG_ENERGY_STATUS 0x00000611
133 #define MSR_PKG_PERF_STATUS 0x00000613
134 #define MSR_PKG_POWER_INFO 0x00000614
136 #define MSR_DRAM_POWER_LIMIT 0x00000618
137 #define MSR_DRAM_ENERGY_STATUS 0x00000619
138 #define MSR_DRAM_PERF_STATUS 0x0000061b
139 #define MSR_DRAM_POWER_INFO 0x0000061c
141 #define MSR_PP0_POWER_LIMIT 0x00000638
142 #define MSR_PP0_ENERGY_STATUS 0x00000639
143 #define MSR_PP0_POLICY 0x0000063a
144 #define MSR_PP0_PERF_STATUS 0x0000063b
146 #define MSR_PP1_POWER_LIMIT 0x00000640
147 #define MSR_PP1_ENERGY_STATUS 0x00000641
148 #define MSR_PP1_POLICY 0x00000642
150 #define MSR_AMD64_MC0_MASK 0xc0010044
152 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
153 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
154 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
155 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
157 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
159 /* These are consecutive and not in the normal 4er MCE bank block */
160 #define MSR_IA32_MC0_CTL2 0x00000280
161 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
163 #define MSR_P6_PERFCTR0 0x000000c1
164 #define MSR_P6_PERFCTR1 0x000000c2
165 #define MSR_P6_EVNTSEL0 0x00000186
166 #define MSR_P6_EVNTSEL1 0x00000187
168 #define MSR_KNC_PERFCTR0 0x00000020
169 #define MSR_KNC_PERFCTR1 0x00000021
170 #define MSR_KNC_EVNTSEL0 0x00000028
171 #define MSR_KNC_EVNTSEL1 0x00000029
173 /* AMD64 MSRs. Not complete. See the architecture manual for a more
176 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
177 #define MSR_AMD64_TSC_RATIO 0xc0000104
178 #define MSR_AMD64_NB_CFG 0xc001001f
179 #define MSR_AMD64_PATCH_LOADER 0xc0010020
180 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
181 #define MSR_AMD64_OSVW_STATUS 0xc0010141
182 #define MSR_AMD64_DC_CFG 0xc0011022
183 #define MSR_AMD64_BU_CFG2 0xc001102a
184 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
185 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
186 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
187 #define MSR_AMD64_IBSFETCH_REG_COUNT 3
188 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
189 #define MSR_AMD64_IBSOPCTL 0xc0011033
190 #define MSR_AMD64_IBSOPRIP 0xc0011034
191 #define MSR_AMD64_IBSOPDATA 0xc0011035
192 #define MSR_AMD64_IBSOPDATA2 0xc0011036
193 #define MSR_AMD64_IBSOPDATA3 0xc0011037
194 #define MSR_AMD64_IBSDCLINAD 0xc0011038
195 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
196 #define MSR_AMD64_IBSOP_REG_COUNT 7
197 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
198 #define MSR_AMD64_IBSCTL 0xc001103a
199 #define MSR_AMD64_IBSBRTARGET 0xc001103b
200 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
203 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
204 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
207 #define MSR_F15H_PERF_CTL 0xc0010200
208 #define MSR_F15H_PERF_CTR 0xc0010201
209 #define MSR_F15H_NB_PERF_CTL 0xc0010240
210 #define MSR_F15H_NB_PERF_CTR 0xc0010241
213 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
214 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
215 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
216 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
217 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
218 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
219 #define MSR_FAM10H_NODE_ID 0xc001100c
222 #define MSR_K8_TOP_MEM1 0xc001001a
223 #define MSR_K8_TOP_MEM2 0xc001001d
224 #define MSR_K8_SYSCFG 0xc0010010
225 #define MSR_K8_INT_PENDING_MSG 0xc0010055
226 /* C1E active bits in int pending message */
227 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
228 #define MSR_K8_TSEG_ADDR 0xc0010112
229 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
230 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
231 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
234 #define MSR_K7_EVNTSEL0 0xc0010000
235 #define MSR_K7_PERFCTR0 0xc0010004
236 #define MSR_K7_EVNTSEL1 0xc0010001
237 #define MSR_K7_PERFCTR1 0xc0010005
238 #define MSR_K7_EVNTSEL2 0xc0010002
239 #define MSR_K7_PERFCTR2 0xc0010006
240 #define MSR_K7_EVNTSEL3 0xc0010003
241 #define MSR_K7_PERFCTR3 0xc0010007
242 #define MSR_K7_CLK_CTL 0xc001001b
243 #define MSR_K7_HWCR 0xc0010015
244 #define MSR_K7_FID_VID_CTL 0xc0010041
245 #define MSR_K7_FID_VID_STATUS 0xc0010042
248 #define MSR_K6_WHCR 0xc0000082
249 #define MSR_K6_UWCCR 0xc0000085
250 #define MSR_K6_EPMR 0xc0000086
251 #define MSR_K6_PSOR 0xc0000087
252 #define MSR_K6_PFIR 0xc0000088
254 /* Centaur-Hauls/IDT defined MSRs. */
255 #define MSR_IDT_FCR1 0x00000107
256 #define MSR_IDT_FCR2 0x00000108
257 #define MSR_IDT_FCR3 0x00000109
258 #define MSR_IDT_FCR4 0x0000010a
260 #define MSR_IDT_MCR0 0x00000110
261 #define MSR_IDT_MCR1 0x00000111
262 #define MSR_IDT_MCR2 0x00000112
263 #define MSR_IDT_MCR3 0x00000113
264 #define MSR_IDT_MCR4 0x00000114
265 #define MSR_IDT_MCR5 0x00000115
266 #define MSR_IDT_MCR6 0x00000116
267 #define MSR_IDT_MCR7 0x00000117
268 #define MSR_IDT_MCR_CTRL 0x00000120
270 /* VIA Cyrix defined MSRs*/
271 #define MSR_VIA_FCR 0x00001107
272 #define MSR_VIA_LONGHAUL 0x0000110a
273 #define MSR_VIA_RNG 0x0000110b
274 #define MSR_VIA_BCR2 0x00001147
276 /* Transmeta defined MSRs */
277 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
278 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
279 #define MSR_TMTA_LRTI_READOUT 0x80868018
280 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
282 /* Intel defined MSRs. */
283 #define MSR_IA32_P5_MC_ADDR 0x00000000
284 #define MSR_IA32_P5_MC_TYPE 0x00000001
285 #define MSR_IA32_TSC 0x00000010
286 #define MSR_IA32_PLATFORM_ID 0x00000017
287 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
288 #define MSR_EBC_FREQUENCY_ID 0x0000002c
289 #define MSR_SMI_COUNT 0x00000034
290 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
291 #define MSR_IA32_TSC_ADJUST 0x0000003b
293 #define FEATURE_CONTROL_LOCKED (1<<0)
294 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
295 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
297 #define MSR_IA32_APICBASE 0x0000001b
298 #define MSR_IA32_APICBASE_BSP (1<<8)
299 #define MSR_IA32_APICBASE_ENABLE (1<<11)
300 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
302 #define MSR_IA32_TSCDEADLINE 0x000006e0
304 #define MSR_IA32_UCODE_WRITE 0x00000079
305 #define MSR_IA32_UCODE_REV 0x0000008b
307 #define MSR_IA32_PERF_STATUS 0x00000198
308 #define MSR_IA32_PERF_CTL 0x00000199
309 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
310 #define MSR_AMD_PERF_STATUS 0xc0010063
311 #define MSR_AMD_PERF_CTL 0xc0010062
313 #define MSR_IA32_MPERF 0x000000e7
314 #define MSR_IA32_APERF 0x000000e8
316 #define MSR_IA32_THERM_CONTROL 0x0000019a
317 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
319 #define THERM_INT_HIGH_ENABLE (1 << 0)
320 #define THERM_INT_LOW_ENABLE (1 << 1)
321 #define THERM_INT_PLN_ENABLE (1 << 24)
323 #define MSR_IA32_THERM_STATUS 0x0000019c
325 #define THERM_STATUS_PROCHOT (1 << 0)
326 #define THERM_STATUS_POWER_LIMIT (1 << 10)
328 #define MSR_THERM2_CTL 0x0000019d
330 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
332 #define MSR_IA32_MISC_ENABLE 0x000001a0
334 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
336 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
337 #define ENERGY_PERF_BIAS_PERFORMANCE 0
338 #define ENERGY_PERF_BIAS_NORMAL 6
339 #define ENERGY_PERF_BIAS_POWERSAVE 15
341 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
343 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
344 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
346 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
348 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
349 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
350 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
352 /* Thermal Thresholds Support */
353 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
354 #define THERM_SHIFT_THRESHOLD0 8
355 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
356 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
357 #define THERM_SHIFT_THRESHOLD1 16
358 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
359 #define THERM_STATUS_THRESHOLD0 (1 << 6)
360 #define THERM_LOG_THRESHOLD0 (1 << 7)
361 #define THERM_STATUS_THRESHOLD1 (1 << 8)
362 #define THERM_LOG_THRESHOLD1 (1 << 9)
364 /* MISC_ENABLE bits: architectural */
365 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
366 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
367 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
368 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
369 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
370 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
371 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
372 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
373 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
374 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
376 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
377 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
378 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
379 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
380 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
381 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
382 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
383 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
384 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
385 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
386 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
387 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
388 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
389 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
390 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
391 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
393 #define MSR_IA32_TSC_DEADLINE 0x000006E0
395 /* P4/Xeon+ specific */
396 #define MSR_IA32_MCG_EAX 0x00000180
397 #define MSR_IA32_MCG_EBX 0x00000181
398 #define MSR_IA32_MCG_ECX 0x00000182
399 #define MSR_IA32_MCG_EDX 0x00000183
400 #define MSR_IA32_MCG_ESI 0x00000184
401 #define MSR_IA32_MCG_EDI 0x00000185
402 #define MSR_IA32_MCG_EBP 0x00000186
403 #define MSR_IA32_MCG_ESP 0x00000187
404 #define MSR_IA32_MCG_EFLAGS 0x00000188
405 #define MSR_IA32_MCG_EIP 0x00000189
406 #define MSR_IA32_MCG_RESERVED 0x0000018a
408 /* Pentium IV performance counter MSRs */
409 #define MSR_P4_BPU_PERFCTR0 0x00000300
410 #define MSR_P4_BPU_PERFCTR1 0x00000301
411 #define MSR_P4_BPU_PERFCTR2 0x00000302
412 #define MSR_P4_BPU_PERFCTR3 0x00000303
413 #define MSR_P4_MS_PERFCTR0 0x00000304
414 #define MSR_P4_MS_PERFCTR1 0x00000305
415 #define MSR_P4_MS_PERFCTR2 0x00000306
416 #define MSR_P4_MS_PERFCTR3 0x00000307
417 #define MSR_P4_FLAME_PERFCTR0 0x00000308
418 #define MSR_P4_FLAME_PERFCTR1 0x00000309
419 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
420 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
421 #define MSR_P4_IQ_PERFCTR0 0x0000030c
422 #define MSR_P4_IQ_PERFCTR1 0x0000030d
423 #define MSR_P4_IQ_PERFCTR2 0x0000030e
424 #define MSR_P4_IQ_PERFCTR3 0x0000030f
425 #define MSR_P4_IQ_PERFCTR4 0x00000310
426 #define MSR_P4_IQ_PERFCTR5 0x00000311
427 #define MSR_P4_BPU_CCCR0 0x00000360
428 #define MSR_P4_BPU_CCCR1 0x00000361
429 #define MSR_P4_BPU_CCCR2 0x00000362
430 #define MSR_P4_BPU_CCCR3 0x00000363
431 #define MSR_P4_MS_CCCR0 0x00000364
432 #define MSR_P4_MS_CCCR1 0x00000365
433 #define MSR_P4_MS_CCCR2 0x00000366
434 #define MSR_P4_MS_CCCR3 0x00000367
435 #define MSR_P4_FLAME_CCCR0 0x00000368
436 #define MSR_P4_FLAME_CCCR1 0x00000369
437 #define MSR_P4_FLAME_CCCR2 0x0000036a
438 #define MSR_P4_FLAME_CCCR3 0x0000036b
439 #define MSR_P4_IQ_CCCR0 0x0000036c
440 #define MSR_P4_IQ_CCCR1 0x0000036d
441 #define MSR_P4_IQ_CCCR2 0x0000036e
442 #define MSR_P4_IQ_CCCR3 0x0000036f
443 #define MSR_P4_IQ_CCCR4 0x00000370
444 #define MSR_P4_IQ_CCCR5 0x00000371
445 #define MSR_P4_ALF_ESCR0 0x000003ca
446 #define MSR_P4_ALF_ESCR1 0x000003cb
447 #define MSR_P4_BPU_ESCR0 0x000003b2
448 #define MSR_P4_BPU_ESCR1 0x000003b3
449 #define MSR_P4_BSU_ESCR0 0x000003a0
450 #define MSR_P4_BSU_ESCR1 0x000003a1
451 #define MSR_P4_CRU_ESCR0 0x000003b8
452 #define MSR_P4_CRU_ESCR1 0x000003b9
453 #define MSR_P4_CRU_ESCR2 0x000003cc
454 #define MSR_P4_CRU_ESCR3 0x000003cd
455 #define MSR_P4_CRU_ESCR4 0x000003e0
456 #define MSR_P4_CRU_ESCR5 0x000003e1
457 #define MSR_P4_DAC_ESCR0 0x000003a8
458 #define MSR_P4_DAC_ESCR1 0x000003a9
459 #define MSR_P4_FIRM_ESCR0 0x000003a4
460 #define MSR_P4_FIRM_ESCR1 0x000003a5
461 #define MSR_P4_FLAME_ESCR0 0x000003a6
462 #define MSR_P4_FLAME_ESCR1 0x000003a7
463 #define MSR_P4_FSB_ESCR0 0x000003a2
464 #define MSR_P4_FSB_ESCR1 0x000003a3
465 #define MSR_P4_IQ_ESCR0 0x000003ba
466 #define MSR_P4_IQ_ESCR1 0x000003bb
467 #define MSR_P4_IS_ESCR0 0x000003b4
468 #define MSR_P4_IS_ESCR1 0x000003b5
469 #define MSR_P4_ITLB_ESCR0 0x000003b6
470 #define MSR_P4_ITLB_ESCR1 0x000003b7
471 #define MSR_P4_IX_ESCR0 0x000003c8
472 #define MSR_P4_IX_ESCR1 0x000003c9
473 #define MSR_P4_MOB_ESCR0 0x000003aa
474 #define MSR_P4_MOB_ESCR1 0x000003ab
475 #define MSR_P4_MS_ESCR0 0x000003c0
476 #define MSR_P4_MS_ESCR1 0x000003c1
477 #define MSR_P4_PMH_ESCR0 0x000003ac
478 #define MSR_P4_PMH_ESCR1 0x000003ad
479 #define MSR_P4_RAT_ESCR0 0x000003bc
480 #define MSR_P4_RAT_ESCR1 0x000003bd
481 #define MSR_P4_SAAT_ESCR0 0x000003ae
482 #define MSR_P4_SAAT_ESCR1 0x000003af
483 #define MSR_P4_SSU_ESCR0 0x000003be
484 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
486 #define MSR_P4_TBPU_ESCR0 0x000003c2
487 #define MSR_P4_TBPU_ESCR1 0x000003c3
488 #define MSR_P4_TC_ESCR0 0x000003c4
489 #define MSR_P4_TC_ESCR1 0x000003c5
490 #define MSR_P4_U2L_ESCR0 0x000003b0
491 #define MSR_P4_U2L_ESCR1 0x000003b1
493 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
495 /* Intel Core-based CPU performance counters */
496 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
497 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
498 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
499 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
500 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
501 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
502 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
504 /* Geode defined MSRs */
505 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
508 #define MSR_IA32_VMX_BASIC 0x00000480
509 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
510 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
511 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
512 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
513 #define MSR_IA32_VMX_MISC 0x00000485
514 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
515 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
516 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
517 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
518 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
519 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
520 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
521 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
522 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
523 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
524 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
526 /* VMX_BASIC bits and bitmasks */
527 #define VMX_BASIC_VMCS_SIZE_SHIFT 32
528 #define VMX_BASIC_64 0x0001000000000000LLU
529 #define VMX_BASIC_MEM_TYPE_SHIFT 50
530 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
531 #define VMX_BASIC_MEM_TYPE_WB 6LLU
532 #define VMX_BASIC_INOUT 0x0040000000000000LLU
534 /* MSR_IA32_VMX_MISC bits */
535 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
538 #define MSR_VM_CR 0xc0010114
539 #define MSR_VM_IGNNE 0xc0010115
540 #define MSR_VM_HSAVE_PA 0xc0010117
542 #endif /* _ASM_X86_MSR_INDEX_H */