arch/x86/include/asm/sev-common.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * AMD SEV header common between the guest and the hypervisor.
   4  *
   5  * Author: Brijesh Singh <brijesh.singh@amd.com>
   6  */
   7
   8 #ifndef __ASM_X86_SEV_COMMON_H
   9 #define __ASM_X86_SEV_COMMON_H
  10
  11 #define GHCB_MSR_INFO_POS               0
  12 #define GHCB_DATA_LOW                   12
  13 #define GHCB_MSR_INFO_MASK              (BIT_ULL(GHCB_DATA_LOW) - 1)
  14
  15 #define GHCB_DATA(v)                    \
  16         (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
  17
  18 /* SEV Information Request/Response */
  19 #define GHCB_MSR_SEV_INFO_RESP          0x001
  20 #define GHCB_MSR_SEV_INFO_REQ           0x002
  21
  22 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit)    \
  23         /* GHCBData[63:48] */                   \
  24         ((((_max) & 0xffff) << 48) |            \
  25          /* GHCBData[47:32] */                  \
  26          (((_min) & 0xffff) << 32) |            \
  27          /* GHCBData[31:24] */                  \
  28          (((_cbit) & 0xff)  << 24) |            \
  29          GHCB_MSR_SEV_INFO_RESP)
  30
  31 #define GHCB_MSR_INFO(v)                ((v) & 0xfffUL)
  32 #define GHCB_MSR_PROTO_MAX(v)           (((v) >> 48) & 0xffff)
  33 #define GHCB_MSR_PROTO_MIN(v)           (((v) >> 32) & 0xffff)
  34
  35 /* CPUID Request/Response */
  36 #define GHCB_MSR_CPUID_REQ              0x004
  37 #define GHCB_MSR_CPUID_RESP             0x005
  38 #define GHCB_MSR_CPUID_FUNC_POS         32
  39 #define GHCB_MSR_CPUID_FUNC_MASK        0xffffffff
  40 #define GHCB_MSR_CPUID_VALUE_POS        32
  41 #define GHCB_MSR_CPUID_VALUE_MASK       0xffffffff
  42 #define GHCB_MSR_CPUID_REG_POS          30
  43 #define GHCB_MSR_CPUID_REG_MASK         0x3
  44 #define GHCB_CPUID_REQ_EAX              0
  45 #define GHCB_CPUID_REQ_EBX              1
  46 #define GHCB_CPUID_REQ_ECX              2
  47 #define GHCB_CPUID_REQ_EDX              3
  48 #define GHCB_CPUID_REQ(fn, reg)                         \
  49         /* GHCBData[11:0] */                            \
  50         (GHCB_MSR_CPUID_REQ |                           \
  51         /* GHCBData[31:12] */                           \
  52         (((unsigned long)(reg) & 0x3) << 30) |          \
  53         /* GHCBData[63:32] */                           \
  54         (((unsigned long)fn) << 32))
  55
  56 /* AP Reset Hold */
  57 #define GHCB_MSR_AP_RESET_HOLD_REQ      0x006
  58 #define GHCB_MSR_AP_RESET_HOLD_RESP     0x007
  59
  60 /* GHCB Hypervisor Feature Request/Response */
  61 #define GHCB_MSR_HV_FT_REQ              0x080
  62 #define GHCB_MSR_HV_FT_RESP             0x081
  63
  64 #define GHCB_MSR_TERM_REQ               0x100
  65 #define GHCB_MSR_TERM_REASON_SET_POS    12
  66 #define GHCB_MSR_TERM_REASON_SET_MASK   0xf
  67 #define GHCB_MSR_TERM_REASON_POS        16
  68 #define GHCB_MSR_TERM_REASON_MASK       0xff
  69
  70 #define GHCB_SEV_TERM_REASON(reason_set, reason_val)    \
  71         /* GHCBData[15:12] */                           \
  72         (((((u64)reason_set) &  0xf) << 12) |           \
  73          /* GHCBData[23:16] */                          \
  74         ((((u64)reason_val) & 0xff) << 16))
  75
  76 #define GHCB_SEV_ES_GEN_REQ             0
  77 #define GHCB_SEV_ES_PROT_UNSUPPORTED    1
  78
  79 #define GHCB_RESP_CODE(v)               ((v) & GHCB_MSR_INFO_MASK)
  80
  81 /*
  82  * Error codes related to GHCB input that can be communicated back to the guest
  83  * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2.
  84  */
  85 #define GHCB_ERR_NOT_REGISTERED         1
  86 #define GHCB_ERR_INVALID_USAGE          2
  87 #define GHCB_ERR_INVALID_SCRATCH_AREA   3
  88 #define GHCB_ERR_MISSING_INPUT          4
  89 #define GHCB_ERR_INVALID_INPUT          5
  90 #define GHCB_ERR_INVALID_EVENT          6
  91
  92 #endif