1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
5 #include <asm/processor-flags.h>
7 /* Forward declaration, a strange C thing */
12 #include <asm/math_emu.h>
13 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <uapi/asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeatures.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
22 #include <asm/desc_defs.h>
24 #include <asm/special_insns.h>
25 #include <asm/fpu/types.h>
26 #include <asm/unwind_hints.h>
28 #include <linux/personality.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/math64.h>
32 #include <linux/err.h>
33 #include <linux/irqflags.h>
34 #include <linux/mem_encrypt.h>
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
40 * Based on this we disable the IP header alignment in network drivers.
42 #define NET_IP_ALIGN 0
46 * Default implementation of macro that returns current
47 * instruction pointer ("program counter").
49 static inline void *current_text_addr(void)
53 asm volatile("mov $1f, %0; 1:":"=r" (pc));
59 * These alignment constraints are for performance in the vSMP case,
60 * but in the task_struct case we must also meet hardware imposed
61 * alignment requirements of the FPU state:
63 #ifdef CONFIG_X86_VSMP
64 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
65 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
67 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
68 # define ARCH_MIN_MMSTRUCT_ALIGN 0
76 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
77 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
78 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
80 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
81 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
82 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
85 * CPU type and hardware bug flags. Kept separately for each CPU.
86 * Members of this structure are referenced in head_32.S, so think twice
87 * before touching them. [mj]
91 __u8 x86; /* CPU family */
92 __u8 x86_vendor; /* CPU vendor */
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits;
104 /* Max extended CPUID function supported: */
105 __u32 extended_cpuid_level;
106 /* Maximum supported CPUID level, -1=no CPUID: */
108 __u32 x86_capability[NCAPINTS + NBUGINTS];
109 char x86_vendor_id[16];
110 char x86_model_id[64];
111 /* in KB - valid for CPUS which support this call: */
112 unsigned int x86_cache_size;
113 int x86_cache_alignment; /* In bytes */
114 /* Cache QoS architectural values: */
115 int x86_cache_max_rmid; /* max index */
116 int x86_cache_occ_scale; /* scale to bytes */
118 unsigned long loops_per_jiffy;
119 /* cpuid returned max cores value: */
123 u16 x86_clflush_size;
124 /* number of cores as seen by the OS: */
126 /* Physical processor id: */
128 /* Logical processor id: */
132 /* Index into per_cpu list: */
135 unsigned initialized : 1;
136 } __randomize_layout;
139 u32 eax, ebx, ecx, edx;
142 enum cpuid_regs_idx {
149 #define X86_VENDOR_INTEL 0
150 #define X86_VENDOR_CYRIX 1
151 #define X86_VENDOR_AMD 2
152 #define X86_VENDOR_UMC 3
153 #define X86_VENDOR_CENTAUR 5
154 #define X86_VENDOR_TRANSMETA 7
155 #define X86_VENDOR_NSC 8
156 #define X86_VENDOR_NUM 9
158 #define X86_VENDOR_UNKNOWN 0xff
161 * capabilities of CPUs
163 extern struct cpuinfo_x86 boot_cpu_data;
164 extern struct cpuinfo_x86 new_cpu_data;
166 extern struct x86_hw_tss doublefault_tss;
167 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
168 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
171 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
172 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
174 #define cpu_info boot_cpu_data
175 #define cpu_data(cpu) boot_cpu_data
178 extern const struct seq_operations cpuinfo_op;
180 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
182 extern void cpu_detect(struct cpuinfo_x86 *c);
184 extern void early_cpu_init(void);
185 extern void identify_boot_cpu(void);
186 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
187 extern void print_cpu_info(struct cpuinfo_x86 *);
188 void print_cpu_msr(struct cpuinfo_x86 *);
191 extern int have_cpuid_p(void);
193 static inline int have_cpuid_p(void)
198 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
199 unsigned int *ecx, unsigned int *edx)
201 /* ecx is often an input as well as an output. */
207 : "0" (*eax), "2" (*ecx)
211 #define native_cpuid_reg(reg) \
212 static inline unsigned int native_cpuid_##reg(unsigned int op) \
214 unsigned int eax = op, ebx, ecx = 0, edx; \
216 native_cpuid(&eax, &ebx, &ecx, &edx); \
222 * Native CPUID functions returning a single datum.
224 native_cpuid_reg(eax)
225 native_cpuid_reg(ebx)
226 native_cpuid_reg(ecx)
227 native_cpuid_reg(edx)
230 * Friendlier CR3 helpers.
232 static inline unsigned long read_cr3_pa(void)
234 return __read_cr3() & CR3_ADDR_MASK;
237 static inline unsigned long native_read_cr3_pa(void)
239 return __native_read_cr3() & CR3_ADDR_MASK;
242 static inline void load_cr3(pgd_t *pgdir)
244 write_cr3(__sme_pa(pgdir));
248 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
249 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
250 * unrelated to the task-switch mechanism:
253 /* This is the TSS defined by the hardware. */
255 unsigned short back_link, __blh;
257 unsigned short ss0, __ss0h;
261 * We don't use ring 1, so ss1 is a convenient scratch space in
262 * the same cacheline as sp0. We use ss1 to cache the value in
263 * MSR_IA32_SYSENTER_CS. When we context switch
264 * MSR_IA32_SYSENTER_CS, we first check if the new value being
265 * written matches ss1, and, if it's not, then we wrmsr the new
266 * value and update ss1.
268 * The only reason we context switch MSR_IA32_SYSENTER_CS is
269 * that we set it to zero in vm86 tasks to avoid corrupting the
270 * stack if we were to go through the sysenter path from vm86
273 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
275 unsigned short __ss1h;
277 unsigned short ss2, __ss2h;
289 unsigned short es, __esh;
290 unsigned short cs, __csh;
291 unsigned short ss, __ssh;
292 unsigned short ds, __dsh;
293 unsigned short fs, __fsh;
294 unsigned short gs, __gsh;
295 unsigned short ldt, __ldth;
296 unsigned short trace;
297 unsigned short io_bitmap_base;
299 } __attribute__((packed));
306 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
307 * Linux does not use ring 1, so sp1 is not otherwise needed.
319 } __attribute__((packed));
325 #define IO_BITMAP_BITS 65536
326 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
327 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
328 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
329 #define INVALID_IO_BITMAP_OFFSET 0x8000
332 unsigned long words[64];
335 struct entry_stack_page {
336 struct entry_stack stack;
337 } __aligned(PAGE_SIZE);
341 * The fixed hardware portion. This must not cross a page boundary
342 * at risk of violating the SDM's advice and potentially triggering
345 struct x86_hw_tss x86_tss;
348 * The extra 1 is there because the CPU will access an
349 * additional byte beyond the end of the IO permission
350 * bitmap. The extra byte must be all 1 bits, and must
351 * be within the limit.
353 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
354 } __aligned(PAGE_SIZE);
356 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
359 * sizeof(unsigned long) coming from an extra "long" at the end
362 * -1? seg base+limit should be pointing to the address of the
365 #define __KERNEL_TSS_LIMIT \
366 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
369 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
371 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
372 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
376 * Save the original ist values for checking stack pointers during debugging
379 unsigned long ist[7];
383 DECLARE_PER_CPU(struct orig_ist, orig_ist);
385 union irq_stack_union {
386 char irq_stack[IRQ_STACK_SIZE];
388 * GCC hardcodes the stack canary as %gs:40. Since the
389 * irq_stack is the object at %gs:0, we reserve the bottom
390 * 48 bytes of the irq stack for the canary.
394 unsigned long stack_canary;
398 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
399 DECLARE_INIT_PER_CPU(irq_stack_union);
401 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
403 return (unsigned long)per_cpu(irq_stack_union.gs_base, cpu);
406 DECLARE_PER_CPU(char *, irq_stack_ptr);
407 DECLARE_PER_CPU(unsigned int, irq_count);
408 extern asmlinkage void ignore_sysret(void);
410 #if IS_ENABLED(CONFIG_KVM)
411 /* Save actual FS/GS selectors and bases to current->thread */
412 void save_fsgs_for_kvm(void);
415 #ifdef CONFIG_STACKPROTECTOR
417 * Make sure stack canary segment base is cached-aligned:
418 * "For Intel Atom processors, avoid non zero segment base address
419 * that is not aligned to cache line boundary at all cost."
420 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
422 struct stack_canary {
423 char __pad[20]; /* canary at %gs:20 */
424 unsigned long canary;
426 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
429 * per-CPU IRQ handling stacks
432 u32 stack[THREAD_SIZE/sizeof(u32)];
433 } __aligned(THREAD_SIZE);
435 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
436 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
439 extern unsigned int fpu_kernel_xstate_size;
440 extern unsigned int fpu_user_xstate_size;
448 struct thread_struct {
449 /* Cached TLS descriptors: */
450 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
456 unsigned long sysenter_cs;
460 unsigned short fsindex;
461 unsigned short gsindex;
465 unsigned long fsbase;
466 unsigned long gsbase;
469 * XXX: this could presumably be unsigned short. Alternatively,
470 * 32-bit kernels could be taught to use fsindex instead.
476 /* Save middle states of ptrace breakpoints */
477 struct perf_event *ptrace_bps[HBP_NUM];
478 /* Debug status used for traps, single steps, etc... */
479 unsigned long debugreg6;
480 /* Keep track of the exact dr7 value set by the user */
481 unsigned long ptrace_dr7;
484 unsigned long trap_nr;
485 unsigned long error_code;
487 /* Virtual 86 mode info */
490 /* IO permissions: */
491 unsigned long *io_bitmap_ptr;
493 /* Max allowed port in the bitmap, in bytes: */
494 unsigned io_bitmap_max;
496 mm_segment_t addr_limit;
498 unsigned int sig_on_uaccess_err:1;
499 unsigned int uaccess_err:1; /* uaccess failed */
501 /* Floating point and extended processor state */
504 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
509 /* Whitelist the FPU state from the task_struct for hardened usercopy. */
510 static inline void arch_thread_struct_whitelist(unsigned long *offset,
513 *offset = offsetof(struct thread_struct, fpu.state);
514 *size = fpu_kernel_xstate_size;
518 * Thread-synchronous status.
520 * This is different from the flags in that nobody else
521 * ever touches our thread-synchronous status, so we don't
522 * have to worry about atomic accesses.
524 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
527 * Set IOPL bits in EFLAGS from given mask
529 static inline void native_set_iopl_mask(unsigned mask)
534 asm volatile ("pushfl;"
541 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
546 native_load_sp0(unsigned long sp0)
548 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
551 static inline void native_swapgs(void)
554 asm volatile("swapgs" ::: "memory");
558 static inline unsigned long current_top_of_stack(void)
561 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
562 * and around vm86 mode and sp0 on x86_64 is special because of the
565 return this_cpu_read_stable(cpu_current_top_of_stack);
568 static inline bool on_thread_stack(void)
570 return (unsigned long)(current_top_of_stack() -
571 current_stack_pointer) < THREAD_SIZE;
574 #ifdef CONFIG_PARAVIRT
575 #include <asm/paravirt.h>
577 #define __cpuid native_cpuid
579 static inline void load_sp0(unsigned long sp0)
581 native_load_sp0(sp0);
584 #define set_iopl_mask native_set_iopl_mask
585 #endif /* CONFIG_PARAVIRT */
587 /* Free all resources held by a thread. */
588 extern void release_thread(struct task_struct *);
590 unsigned long get_wchan(struct task_struct *p);
593 * Generic CPUID function
594 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
595 * resulting in stale register contents being returned.
597 static inline void cpuid(unsigned int op,
598 unsigned int *eax, unsigned int *ebx,
599 unsigned int *ecx, unsigned int *edx)
603 __cpuid(eax, ebx, ecx, edx);
606 /* Some CPUID calls want 'count' to be placed in ecx */
607 static inline void cpuid_count(unsigned int op, int count,
608 unsigned int *eax, unsigned int *ebx,
609 unsigned int *ecx, unsigned int *edx)
613 __cpuid(eax, ebx, ecx, edx);
617 * CPUID functions returning a single datum
619 static inline unsigned int cpuid_eax(unsigned int op)
621 unsigned int eax, ebx, ecx, edx;
623 cpuid(op, &eax, &ebx, &ecx, &edx);
628 static inline unsigned int cpuid_ebx(unsigned int op)
630 unsigned int eax, ebx, ecx, edx;
632 cpuid(op, &eax, &ebx, &ecx, &edx);
637 static inline unsigned int cpuid_ecx(unsigned int op)
639 unsigned int eax, ebx, ecx, edx;
641 cpuid(op, &eax, &ebx, &ecx, &edx);
646 static inline unsigned int cpuid_edx(unsigned int op)
648 unsigned int eax, ebx, ecx, edx;
650 cpuid(op, &eax, &ebx, &ecx, &edx);
655 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
656 static __always_inline void rep_nop(void)
658 asm volatile("rep; nop" ::: "memory");
661 static __always_inline void cpu_relax(void)
667 * This function forces the icache and prefetched instruction stream to
668 * catch up with reality in two very specific cases:
670 * a) Text was modified using one virtual address and is about to be executed
671 * from the same physical page at a different virtual address.
673 * b) Text was modified on a different CPU, may subsequently be
674 * executed on this CPU, and you want to make sure the new version
675 * gets executed. This generally means you're calling this in a IPI.
677 * If you're calling this for a different reason, you're probably doing
680 static inline void sync_core(void)
683 * There are quite a few ways to do this. IRET-to-self is nice
684 * because it works on every CPU, at any CPL (so it's compatible
685 * with paravirtualization), and it never exits to a hypervisor.
686 * The only down sides are that it's a bit slow (it seems to be
687 * a bit more than 2x slower than the fastest options) and that
688 * it unmasks NMIs. The "push %cs" is needed because, in
689 * paravirtual environments, __KERNEL_CS may not be a valid CS
690 * value when we do IRET directly.
692 * In case NMI unmasking or performance ever becomes a problem,
693 * the next best option appears to be MOV-to-CR2 and an
694 * unconditional jump. That sequence also works on all CPUs,
695 * but it will fault at CPL3 (i.e. Xen PV).
697 * CPUID is the conventional way, but it's nasty: it doesn't
698 * exist on some 486-like CPUs, and it usually exits to a
701 * Like all of Linux's memory ordering operations, this is a
702 * compiler barrier as well.
711 : ASM_CALL_CONSTRAINT : : "memory");
720 "addq $8, (%%rsp)\n\t"
728 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
732 extern void select_idle_routine(const struct cpuinfo_x86 *c);
733 extern void amd_e400_c1e_apic_setup(void);
735 extern unsigned long boot_option_idle_override;
737 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
740 extern void enable_sep_cpu(void);
741 extern int sysenter_setup(void);
743 void early_trap_pf_init(void);
745 /* Defined in head.S */
746 extern struct desc_ptr early_gdt_descr;
748 extern void switch_to_new_gdt(int);
749 extern void load_direct_gdt(int);
750 extern void load_fixmap_gdt(int);
751 extern void load_percpu_segment(int);
752 extern void cpu_init(void);
754 static inline unsigned long get_debugctlmsr(void)
756 unsigned long debugctlmsr = 0;
758 #ifndef CONFIG_X86_DEBUGCTLMSR
759 if (boot_cpu_data.x86 < 6)
762 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
767 static inline void update_debugctlmsr(unsigned long debugctlmsr)
769 #ifndef CONFIG_X86_DEBUGCTLMSR
770 if (boot_cpu_data.x86 < 6)
773 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
776 extern void set_task_blockstep(struct task_struct *task, bool on);
778 /* Boot loader type from the setup header: */
779 extern int bootloader_type;
780 extern int bootloader_version;
782 extern char ignore_fpu_irq;
784 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
785 #define ARCH_HAS_PREFETCHW
786 #define ARCH_HAS_SPINLOCK_PREFETCH
789 # define BASE_PREFETCH ""
790 # define ARCH_HAS_PREFETCH
792 # define BASE_PREFETCH "prefetcht0 %P1"
796 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
798 * It's not worth to care about 3dnow prefetches for the K6
799 * because they are microcoded there and very slow.
801 static inline void prefetch(const void *x)
803 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
805 "m" (*(const char *)x));
809 * 3dnow prefetch to get an exclusive cache line.
810 * Useful for spinlocks to avoid one state transition in the
811 * cache coherency protocol:
813 static inline void prefetchw(const void *x)
815 alternative_input(BASE_PREFETCH, "prefetchw %P1",
816 X86_FEATURE_3DNOWPREFETCH,
817 "m" (*(const char *)x));
820 static inline void spin_lock_prefetch(const void *x)
825 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
826 TOP_OF_KERNEL_STACK_PADDING)
828 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
830 #define task_pt_regs(task) \
832 unsigned long __ptr = (unsigned long)task_stack_page(task); \
833 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
834 ((struct pt_regs *)__ptr) - 1; \
839 * User space process size: 3GB (default).
841 #define IA32_PAGE_OFFSET PAGE_OFFSET
842 #define TASK_SIZE PAGE_OFFSET
843 #define TASK_SIZE_LOW TASK_SIZE
844 #define TASK_SIZE_MAX TASK_SIZE
845 #define DEFAULT_MAP_WINDOW TASK_SIZE
846 #define STACK_TOP TASK_SIZE
847 #define STACK_TOP_MAX STACK_TOP
849 #define INIT_THREAD { \
850 .sp0 = TOP_OF_INIT_STACK, \
851 .sysenter_cs = __KERNEL_CS, \
852 .io_bitmap_ptr = NULL, \
853 .addr_limit = KERNEL_DS, \
856 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
860 * User space process size. This is the first address outside the user range.
861 * There are a few constraints that determine this:
863 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
864 * address, then that syscall will enter the kernel with a
865 * non-canonical return address, and SYSRET will explode dangerously.
866 * We avoid this particular problem by preventing anything executable
867 * from being mapped at the maximum canonical address.
869 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
870 * CPUs malfunction if they execute code from the highest canonical page.
871 * They'll speculate right off the end of the canonical space, and
872 * bad things happen. This is worked around in the same way as the
875 * With page table isolation enabled, we map the LDT in ... [stay tuned]
877 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
879 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
881 /* This decides where the kernel will search for a free chunk of vm
882 * space during mmap's.
884 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
885 0xc0000000 : 0xFFFFe000)
887 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
888 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
889 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
890 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
891 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
892 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
894 #define STACK_TOP TASK_SIZE_LOW
895 #define STACK_TOP_MAX TASK_SIZE_MAX
897 #define INIT_THREAD { \
898 .addr_limit = KERNEL_DS, \
901 extern unsigned long KSTK_ESP(struct task_struct *task);
903 #endif /* CONFIG_X86_64 */
905 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
906 unsigned long new_sp);
909 * This decides where the kernel will search for a free chunk of vm
910 * space during mmap's.
912 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
913 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
915 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
917 /* Get/set a process' ability to use the timestamp counter instruction */
918 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
919 #define SET_TSC_CTL(val) set_tsc_mode((val))
921 extern int get_tsc_mode(unsigned long adr);
922 extern int set_tsc_mode(unsigned int val);
924 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
926 /* Register/unregister a process' MPX related resource */
927 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
928 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
930 #ifdef CONFIG_X86_INTEL_MPX
931 extern int mpx_enable_management(void);
932 extern int mpx_disable_management(void);
934 static inline int mpx_enable_management(void)
938 static inline int mpx_disable_management(void)
942 #endif /* CONFIG_X86_INTEL_MPX */
944 #ifdef CONFIG_CPU_SUP_AMD
945 extern u16 amd_get_nb_id(int cpu);
946 extern u32 amd_get_nodes_per_socket(void);
948 static inline u16 amd_get_nb_id(int cpu) { return 0; }
949 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
952 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
954 uint32_t base, eax, signature[3];
956 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
957 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
959 if (!memcmp(sig, signature, 12) &&
960 (leaves == 0 || ((eax - base) >= leaves)))
967 extern unsigned long arch_align_stack(unsigned long sp);
968 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
970 void default_idle(void);
972 bool xen_set_default_idle(void);
974 #define xen_set_default_idle 0
977 void stop_this_cpu(void *dummy);
978 void df_debug(struct pt_regs *regs, long error_code);
979 void microcode_check(void);
980 #endif /* _ASM_X86_PROCESSOR_H */