1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Low-Level PCI Access for i386 machines.
5 * (c) 1999 Martin Mares <mj@ucw.cz>
8 #include <linux/ioport.h>
13 #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
15 #define DBG(fmt, ...) \
18 printk(fmt, ##__VA_ARGS__); \
22 #define PCI_PROBE_BIOS 0x0001
23 #define PCI_PROBE_CONF1 0x0002
24 #define PCI_PROBE_CONF2 0x0004
25 #define PCI_PROBE_MMCONF 0x0008
26 #define PCI_PROBE_MASK 0x000f
27 #define PCI_PROBE_NOEARLY 0x0010
29 #define PCI_NO_CHECKS 0x0400
30 #define PCI_USE_PIRQ_MASK 0x0800
31 #define PCI_ASSIGN_ROMS 0x1000
32 #define PCI_BIOS_IRQ_SCAN 0x2000
33 #define PCI_ASSIGN_ALL_BUSSES 0x4000
34 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
35 #define PCI_USE__CRS 0x10000
36 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
37 #define PCI_HAS_IO_ECS 0x40000
38 #define PCI_NOASSIGN_ROMS 0x80000
39 #define PCI_ROOT_NO_CRS 0x100000
40 #define PCI_NOASSIGN_BARS 0x200000
42 extern unsigned int pci_probe;
43 extern unsigned long pirq_table_addr;
45 enum pci_bf_sort_state {
54 void pcibios_resource_survey(void);
55 void pcibios_set_cache_line_size(void);
59 extern int pcibios_last_bus;
60 extern struct pci_ops pci_root_ops;
62 void pcibios_scan_specific_bus(int busn);
67 u8 bus, devfn; /* Bus, device and function */
69 u8 link; /* IRQ line ID, chipset dependent,
71 u16 bitmap; /* Available IRQs */
72 } __attribute__((packed)) irq[4];
73 u8 slot; /* Slot number, 0=onboard */
75 } __attribute__((packed));
77 struct irq_routing_table {
78 u32 signature; /* PIRQ_SIGNATURE should be here */
79 u16 version; /* PIRQ_VERSION */
80 u16 size; /* Table size in bytes */
81 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
82 u16 exclusive_irqs; /* IRQs devoted exclusively to
84 u16 rtr_vendor, rtr_device; /* Vendor and device ID of
86 u32 miniport_data; /* Crap */
88 u8 checksum; /* Modulo 256 checksum must give 0 */
89 struct irq_info slots[0];
90 } __attribute__((packed));
92 extern unsigned int pcibios_irq_mask;
94 extern raw_spinlock_t pci_config_lock;
96 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
97 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
99 extern bool mp_should_keep_irq(struct device *dev);
102 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
103 int reg, int len, u32 *val);
104 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
105 int reg, int len, u32 val);
108 extern const struct pci_raw_ops *raw_pci_ops;
109 extern const struct pci_raw_ops *raw_pci_ext_ops;
111 extern const struct pci_raw_ops pci_mmcfg;
112 extern const struct pci_raw_ops pci_direct_conf1;
113 extern bool port_cf9_safe;
115 /* arch_initcall level */
116 extern int pci_direct_probe(void);
117 extern void pci_direct_init(int type);
118 extern void pci_pcbios_init(void);
119 extern void __init dmi_check_pciprobe(void);
120 extern void __init dmi_check_skip_isa_align(void);
122 /* some common used subsys_initcalls */
123 extern int __init pci_acpi_init(void);
124 extern void __init pcibios_irq_init(void);
125 extern int __init pcibios_init(void);
126 extern int pci_legacy_init(void);
127 extern void pcibios_fixup_irqs(void);
131 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
132 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
134 struct pci_mmcfg_region {
135 struct list_head list;
142 char name[PCI_MMCFG_RESOURCE_NAME_LEN];
145 extern int __init pci_mmcfg_arch_init(void);
146 extern void __init pci_mmcfg_arch_free(void);
147 extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
148 extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
149 extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
151 extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
152 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
154 extern struct list_head pci_mmcfg_list;
156 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
159 * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
160 * %eax. No other source or target registers may be used. The following
161 * mmio_config_* accessors enforce this. See "BIOS and Kernel Developer's
162 * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
163 * "MMIO Configuration Coding Requirements".
165 static inline unsigned char mmio_config_readb(void __iomem *pos)
168 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
172 static inline unsigned short mmio_config_readw(void __iomem *pos)
175 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
179 static inline unsigned int mmio_config_readl(void __iomem *pos)
182 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
186 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
188 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
191 static inline void mmio_config_writew(void __iomem *pos, u16 val)
193 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
196 static inline void mmio_config_writel(void __iomem *pos, u32 val)
198 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
203 # define x86_default_pci_init pci_acpi_init
205 # define x86_default_pci_init pci_legacy_init
207 # define x86_default_pci_init_irq pcibios_irq_init
208 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
210 # define x86_default_pci_init NULL
211 # define x86_default_pci_init_irq NULL
212 # define x86_default_pci_fixup_irqs NULL