1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5 * para-virtualization: those hooks are defined here. */
8 #include <asm/pgtable_types.h>
10 #include <asm/nospec-branch.h>
12 #include <asm/paravirt_types.h>
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
20 static inline void load_sp0(unsigned long sp0)
22 PVOP_VCALL1(pv_cpu_ops.load_sp0, sp0);
25 /* The paravirtualized CPUID instruction. */
26 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
27 unsigned int *ecx, unsigned int *edx)
29 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
33 * These special macros can be used to get or set a debugging register
35 static inline unsigned long paravirt_get_debugreg(int reg)
37 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
39 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
40 static inline void set_debugreg(unsigned long val, int reg)
42 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
45 static inline unsigned long read_cr0(void)
47 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
50 static inline void write_cr0(unsigned long x)
52 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
55 static inline unsigned long read_cr2(void)
57 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
60 static inline void write_cr2(unsigned long x)
62 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
65 static inline unsigned long __read_cr3(void)
67 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
70 static inline void write_cr3(unsigned long x)
72 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
75 static inline void __write_cr4(unsigned long x)
77 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
81 static inline unsigned long read_cr8(void)
83 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
86 static inline void write_cr8(unsigned long x)
88 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
92 static inline void arch_safe_halt(void)
94 PVOP_VCALL0(pv_irq_ops.safe_halt);
97 static inline void halt(void)
99 PVOP_VCALL0(pv_irq_ops.halt);
102 static inline void wbinvd(void)
104 PVOP_VCALL0(pv_cpu_ops.wbinvd);
107 #define get_kernel_rpl() (pv_info.kernel_rpl)
109 static inline u64 paravirt_read_msr(unsigned msr)
111 return PVOP_CALL1(u64, pv_cpu_ops.read_msr, msr);
114 static inline void paravirt_write_msr(unsigned msr,
115 unsigned low, unsigned high)
117 PVOP_VCALL3(pv_cpu_ops.write_msr, msr, low, high);
120 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
122 return PVOP_CALL2(u64, pv_cpu_ops.read_msr_safe, msr, err);
125 static inline int paravirt_write_msr_safe(unsigned msr,
126 unsigned low, unsigned high)
128 return PVOP_CALL3(int, pv_cpu_ops.write_msr_safe, msr, low, high);
131 #define rdmsr(msr, val1, val2) \
133 u64 _l = paravirt_read_msr(msr); \
138 #define wrmsr(msr, val1, val2) \
140 paravirt_write_msr(msr, val1, val2); \
143 #define rdmsrl(msr, val) \
145 val = paravirt_read_msr(msr); \
148 static inline void wrmsrl(unsigned msr, u64 val)
150 wrmsr(msr, (u32)val, (u32)(val>>32));
153 #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b)
155 /* rdmsr with exception handling */
156 #define rdmsr_safe(msr, a, b) \
159 u64 _l = paravirt_read_msr_safe(msr, &_err); \
165 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
169 *p = paravirt_read_msr_safe(msr, &err);
173 static inline unsigned long long paravirt_sched_clock(void)
175 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
179 extern struct static_key paravirt_steal_enabled;
180 extern struct static_key paravirt_steal_rq_enabled;
182 static inline u64 paravirt_steal_clock(int cpu)
184 return PVOP_CALL1(u64, pv_time_ops.steal_clock, cpu);
187 static inline unsigned long long paravirt_read_pmc(int counter)
189 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
192 #define rdpmc(counter, low, high) \
194 u64 _l = paravirt_read_pmc(counter); \
199 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
201 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
203 PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
206 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
208 PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
211 static inline void load_TR_desc(void)
213 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
215 static inline void load_gdt(const struct desc_ptr *dtr)
217 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
219 static inline void load_idt(const struct desc_ptr *dtr)
221 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
223 static inline void set_ldt(const void *addr, unsigned entries)
225 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
227 static inline unsigned long paravirt_store_tr(void)
229 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
231 #define store_tr(tr) ((tr) = paravirt_store_tr())
232 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
234 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
238 static inline void load_gs_index(unsigned int gs)
240 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
244 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
247 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
250 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
251 void *desc, int type)
253 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
256 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
258 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
260 static inline void set_iopl_mask(unsigned mask)
262 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
265 /* The paravirtualized I/O functions */
266 static inline void slow_down_io(void)
268 pv_cpu_ops.io_delay();
269 #ifdef REALLY_SLOW_IO
270 pv_cpu_ops.io_delay();
271 pv_cpu_ops.io_delay();
272 pv_cpu_ops.io_delay();
276 static inline void paravirt_activate_mm(struct mm_struct *prev,
277 struct mm_struct *next)
279 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
282 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
283 struct mm_struct *mm)
285 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
288 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
290 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
293 static inline void __flush_tlb(void)
295 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
297 static inline void __flush_tlb_global(void)
299 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
301 static inline void __flush_tlb_one_user(unsigned long addr)
303 PVOP_VCALL1(pv_mmu_ops.flush_tlb_one_user, addr);
306 static inline void flush_tlb_others(const struct cpumask *cpumask,
307 const struct flush_tlb_info *info)
309 PVOP_VCALL2(pv_mmu_ops.flush_tlb_others, cpumask, info);
312 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
314 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
317 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
319 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
322 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
324 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
326 static inline void paravirt_release_pte(unsigned long pfn)
328 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
331 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
333 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
336 static inline void paravirt_release_pmd(unsigned long pfn)
338 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
341 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
343 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
345 static inline void paravirt_release_pud(unsigned long pfn)
347 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
350 static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn)
352 PVOP_VCALL2(pv_mmu_ops.alloc_p4d, mm, pfn);
355 static inline void paravirt_release_p4d(unsigned long pfn)
357 PVOP_VCALL1(pv_mmu_ops.release_p4d, pfn);
360 static inline pte_t __pte(pteval_t val)
364 if (sizeof(pteval_t) > sizeof(long))
365 ret = PVOP_CALLEE2(pteval_t,
367 val, (u64)val >> 32);
369 ret = PVOP_CALLEE1(pteval_t,
373 return (pte_t) { .pte = ret };
376 static inline pteval_t pte_val(pte_t pte)
380 if (sizeof(pteval_t) > sizeof(long))
381 ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val,
382 pte.pte, (u64)pte.pte >> 32);
384 ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val,
390 static inline pgd_t __pgd(pgdval_t val)
394 if (sizeof(pgdval_t) > sizeof(long))
395 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd,
396 val, (u64)val >> 32);
398 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd,
401 return (pgd_t) { ret };
404 static inline pgdval_t pgd_val(pgd_t pgd)
408 if (sizeof(pgdval_t) > sizeof(long))
409 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val,
410 pgd.pgd, (u64)pgd.pgd >> 32);
412 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val,
418 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
419 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
424 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
427 return (pte_t) { .pte = ret };
430 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
431 pte_t *ptep, pte_t pte)
433 if (sizeof(pteval_t) > sizeof(long))
435 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
437 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
438 mm, addr, ptep, pte.pte);
441 static inline void set_pte(pte_t *ptep, pte_t pte)
443 if (sizeof(pteval_t) > sizeof(long))
444 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
445 pte.pte, (u64)pte.pte >> 32);
447 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
451 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
452 pte_t *ptep, pte_t pte)
454 if (sizeof(pteval_t) > sizeof(long))
456 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
458 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
461 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
463 pmdval_t val = native_pmd_val(pmd);
465 if (sizeof(pmdval_t) > sizeof(long))
466 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
468 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
471 #if CONFIG_PGTABLE_LEVELS >= 3
472 static inline pmd_t __pmd(pmdval_t val)
476 if (sizeof(pmdval_t) > sizeof(long))
477 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd,
478 val, (u64)val >> 32);
480 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd,
483 return (pmd_t) { ret };
486 static inline pmdval_t pmd_val(pmd_t pmd)
490 if (sizeof(pmdval_t) > sizeof(long))
491 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val,
492 pmd.pmd, (u64)pmd.pmd >> 32);
494 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val,
500 static inline void set_pud(pud_t *pudp, pud_t pud)
502 pudval_t val = native_pud_val(pud);
504 if (sizeof(pudval_t) > sizeof(long))
505 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
506 val, (u64)val >> 32);
508 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
511 #if CONFIG_PGTABLE_LEVELS >= 4
512 static inline pud_t __pud(pudval_t val)
516 if (sizeof(pudval_t) > sizeof(long))
517 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud,
518 val, (u64)val >> 32);
520 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud,
523 return (pud_t) { ret };
526 static inline pudval_t pud_val(pud_t pud)
530 if (sizeof(pudval_t) > sizeof(long))
531 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val,
532 pud.pud, (u64)pud.pud >> 32);
534 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val,
540 static inline void pud_clear(pud_t *pudp)
542 set_pud(pudp, __pud(0));
545 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
547 p4dval_t val = native_p4d_val(p4d);
549 if (sizeof(p4dval_t) > sizeof(long))
550 PVOP_VCALL3(pv_mmu_ops.set_p4d, p4dp,
551 val, (u64)val >> 32);
553 PVOP_VCALL2(pv_mmu_ops.set_p4d, p4dp,
557 #if CONFIG_PGTABLE_LEVELS >= 5
559 static inline p4d_t __p4d(p4dval_t val)
561 p4dval_t ret = PVOP_CALLEE1(p4dval_t, pv_mmu_ops.make_p4d, val);
563 return (p4d_t) { ret };
566 static inline p4dval_t p4d_val(p4d_t p4d)
568 return PVOP_CALLEE1(p4dval_t, pv_mmu_ops.p4d_val, p4d.p4d);
571 static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
573 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, native_pgd_val(pgd));
576 #define set_pgd(pgdp, pgdval) do { \
577 if (pgtable_l5_enabled()) \
578 __set_pgd(pgdp, pgdval); \
580 set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd }); \
583 #define pgd_clear(pgdp) do { \
584 if (pgtable_l5_enabled()) \
585 set_pgd(pgdp, __pgd(0)); \
588 #endif /* CONFIG_PGTABLE_LEVELS == 5 */
590 static inline void p4d_clear(p4d_t *p4dp)
592 set_p4d(p4dp, __p4d(0));
595 #endif /* CONFIG_PGTABLE_LEVELS == 4 */
597 #endif /* CONFIG_PGTABLE_LEVELS >= 3 */
599 #ifdef CONFIG_X86_PAE
600 /* Special-case pte-setting operations for PAE, which can't update a
601 64-bit pte atomically */
602 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
604 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
605 pte.pte, pte.pte >> 32);
608 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
611 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
614 static inline void pmd_clear(pmd_t *pmdp)
616 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
618 #else /* !CONFIG_X86_PAE */
619 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
624 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
627 set_pte_at(mm, addr, ptep, __pte(0));
630 static inline void pmd_clear(pmd_t *pmdp)
632 set_pmd(pmdp, __pmd(0));
634 #endif /* CONFIG_X86_PAE */
636 #define __HAVE_ARCH_START_CONTEXT_SWITCH
637 static inline void arch_start_context_switch(struct task_struct *prev)
639 PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev);
642 static inline void arch_end_context_switch(struct task_struct *next)
644 PVOP_VCALL1(pv_cpu_ops.end_context_switch, next);
647 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
648 static inline void arch_enter_lazy_mmu_mode(void)
650 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
653 static inline void arch_leave_lazy_mmu_mode(void)
655 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
658 static inline void arch_flush_lazy_mmu_mode(void)
660 PVOP_VCALL0(pv_mmu_ops.lazy_mode.flush);
663 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
664 phys_addr_t phys, pgprot_t flags)
666 pv_mmu_ops.set_fixmap(idx, phys, flags);
669 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
671 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
674 PVOP_VCALL2(pv_lock_ops.queued_spin_lock_slowpath, lock, val);
677 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
679 PVOP_VCALLEE1(pv_lock_ops.queued_spin_unlock, lock);
682 static __always_inline void pv_wait(u8 *ptr, u8 val)
684 PVOP_VCALL2(pv_lock_ops.wait, ptr, val);
687 static __always_inline void pv_kick(int cpu)
689 PVOP_VCALL1(pv_lock_ops.kick, cpu);
692 static __always_inline bool pv_vcpu_is_preempted(long cpu)
694 return PVOP_CALLEE1(bool, pv_lock_ops.vcpu_is_preempted, cpu);
697 #endif /* SMP && PARAVIRT_SPINLOCKS */
700 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
701 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
703 /* save and restore all caller-save registers, except return value */
704 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
705 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
707 #define PV_FLAGS_ARG "0"
708 #define PV_EXTRA_CLOBBERS
709 #define PV_VEXTRA_CLOBBERS
711 /* save and restore all caller-save registers, except return value */
712 #define PV_SAVE_ALL_CALLER_REGS \
721 #define PV_RESTORE_ALL_CALLER_REGS \
731 /* We save some registers, but all of them, that's too much. We clobber all
732 * caller saved registers but the argument parameter */
733 #define PV_SAVE_REGS "pushq %%rdi;"
734 #define PV_RESTORE_REGS "popq %%rdi;"
735 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
736 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
737 #define PV_FLAGS_ARG "D"
741 * Generate a thunk around a function which saves all caller-save
742 * registers except for the return value. This allows C functions to
743 * be called from assembler code where fewer than normal registers are
744 * available. It may also help code generation around calls from C
745 * code if the common case doesn't use many registers.
747 * When a callee is wrapped in a thunk, the caller can assume that all
748 * arg regs and all scratch registers are preserved across the
749 * call. The return value in rax/eax will not be saved, even for void
752 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
753 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
754 extern typeof(func) __raw_callee_save_##func; \
756 asm(".pushsection .text;" \
757 ".globl " PV_THUNK_NAME(func) ";" \
758 ".type " PV_THUNK_NAME(func) ", @function;" \
759 PV_THUNK_NAME(func) ":" \
761 PV_SAVE_ALL_CALLER_REGS \
763 PV_RESTORE_ALL_CALLER_REGS \
768 /* Get a reference to a callee-save function */
769 #define PV_CALLEE_SAVE(func) \
770 ((struct paravirt_callee_save) { __raw_callee_save_##func })
772 /* Promise that "func" already uses the right calling convention */
773 #define __PV_IS_CALLEE_SAVE(func) \
774 ((struct paravirt_callee_save) { func })
776 static inline notrace unsigned long arch_local_save_flags(void)
778 return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl);
781 static inline notrace void arch_local_irq_restore(unsigned long f)
783 PVOP_VCALLEE1(pv_irq_ops.restore_fl, f);
786 static inline notrace void arch_local_irq_disable(void)
788 PVOP_VCALLEE0(pv_irq_ops.irq_disable);
791 static inline notrace void arch_local_irq_enable(void)
793 PVOP_VCALLEE0(pv_irq_ops.irq_enable);
796 static inline notrace unsigned long arch_local_irq_save(void)
800 f = arch_local_save_flags();
801 arch_local_irq_disable();
806 /* Make sure as little as possible of this mess escapes. */
821 extern void default_banner(void);
823 #else /* __ASSEMBLY__ */
825 #define _PVSITE(ptype, clobbers, ops, word, algn) \
829 .pushsection .parainstructions,"a"; \
838 #define COND_PUSH(set, mask, reg) \
839 .if ((~(set)) & mask); push %reg; .endif
840 #define COND_POP(set, mask, reg) \
841 .if ((~(set)) & mask); pop %reg; .endif
845 #define PV_SAVE_REGS(set) \
846 COND_PUSH(set, CLBR_RAX, rax); \
847 COND_PUSH(set, CLBR_RCX, rcx); \
848 COND_PUSH(set, CLBR_RDX, rdx); \
849 COND_PUSH(set, CLBR_RSI, rsi); \
850 COND_PUSH(set, CLBR_RDI, rdi); \
851 COND_PUSH(set, CLBR_R8, r8); \
852 COND_PUSH(set, CLBR_R9, r9); \
853 COND_PUSH(set, CLBR_R10, r10); \
854 COND_PUSH(set, CLBR_R11, r11)
855 #define PV_RESTORE_REGS(set) \
856 COND_POP(set, CLBR_R11, r11); \
857 COND_POP(set, CLBR_R10, r10); \
858 COND_POP(set, CLBR_R9, r9); \
859 COND_POP(set, CLBR_R8, r8); \
860 COND_POP(set, CLBR_RDI, rdi); \
861 COND_POP(set, CLBR_RSI, rsi); \
862 COND_POP(set, CLBR_RDX, rdx); \
863 COND_POP(set, CLBR_RCX, rcx); \
864 COND_POP(set, CLBR_RAX, rax)
866 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
867 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
868 #define PARA_INDIRECT(addr) *addr(%rip)
870 #define PV_SAVE_REGS(set) \
871 COND_PUSH(set, CLBR_EAX, eax); \
872 COND_PUSH(set, CLBR_EDI, edi); \
873 COND_PUSH(set, CLBR_ECX, ecx); \
874 COND_PUSH(set, CLBR_EDX, edx)
875 #define PV_RESTORE_REGS(set) \
876 COND_POP(set, CLBR_EDX, edx); \
877 COND_POP(set, CLBR_ECX, ecx); \
878 COND_POP(set, CLBR_EDI, edi); \
879 COND_POP(set, CLBR_EAX, eax)
881 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
882 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
883 #define PARA_INDIRECT(addr) *%cs:addr
886 #define INTERRUPT_RETURN \
887 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
888 ANNOTATE_RETPOLINE_SAFE; \
889 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret);)
891 #define DISABLE_INTERRUPTS(clobbers) \
892 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
893 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
894 ANNOTATE_RETPOLINE_SAFE; \
895 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
896 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
898 #define ENABLE_INTERRUPTS(clobbers) \
899 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
900 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
901 ANNOTATE_RETPOLINE_SAFE; \
902 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
903 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
906 #define GET_CR0_INTO_EAX \
907 push %ecx; push %edx; \
908 ANNOTATE_RETPOLINE_SAFE; \
909 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
911 #else /* !CONFIG_X86_32 */
914 * If swapgs is used while the userspace stack is still current,
915 * there's no way to call a pvop. The PV replacement *must* be
916 * inlined, or the swapgs instruction must be trapped and emulated.
918 #define SWAPGS_UNSAFE_STACK \
919 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
923 * Note: swapgs is very special, and in practise is either going to be
924 * implemented with a single "swapgs" instruction or something very
925 * special. Either way, we don't need to save any registers for
929 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
930 ANNOTATE_RETPOLINE_SAFE; \
931 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \
934 #define GET_CR2_INTO_RAX \
935 ANNOTATE_RETPOLINE_SAFE; \
936 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2);
938 #define USERGS_SYSRET64 \
939 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
941 ANNOTATE_RETPOLINE_SAFE; \
942 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64);)
944 #ifdef CONFIG_DEBUG_ENTRY
945 #define SAVE_FLAGS(clobbers) \
946 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_save_fl), clobbers, \
947 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
948 ANNOTATE_RETPOLINE_SAFE; \
949 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_save_fl); \
950 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
953 #endif /* CONFIG_X86_32 */
955 #endif /* __ASSEMBLY__ */
956 #else /* CONFIG_PARAVIRT */
957 # define default_banner x86_init_noop
959 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
960 struct mm_struct *mm)
964 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
967 #endif /* __ASSEMBLY__ */
968 #endif /* !CONFIG_PARAVIRT */
969 #endif /* _ASM_X86_PARAVIRT_H */