1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PARAVIRT_H
3 #define _ASM_X86_PARAVIRT_H
4 /* Various instructions on x86 need to be replaced for
5 * para-virtualization: those hooks are defined here. */
8 #include <asm/pgtable_types.h>
10 #include <asm/nospec-branch.h>
12 #include <asm/paravirt_types.h>
15 #include <linux/bug.h>
16 #include <linux/types.h>
17 #include <linux/cpumask.h>
18 #include <asm/frame.h>
20 static inline unsigned long long paravirt_sched_clock(void)
22 return PVOP_CALL0(unsigned long long, time.sched_clock);
26 extern struct static_key paravirt_steal_enabled;
27 extern struct static_key paravirt_steal_rq_enabled;
29 __visible void __native_queued_spin_unlock(struct qspinlock *lock);
30 bool pv_is_native_spin_unlock(void);
31 __visible bool __native_vcpu_is_preempted(long cpu);
32 bool pv_is_native_vcpu_is_preempted(void);
34 static inline u64 paravirt_steal_clock(int cpu)
36 return PVOP_CALL1(u64, time.steal_clock, cpu);
39 /* The paravirtualized I/O functions */
40 static inline void slow_down_io(void)
42 pv_ops.cpu.io_delay();
44 pv_ops.cpu.io_delay();
45 pv_ops.cpu.io_delay();
46 pv_ops.cpu.io_delay();
50 static inline void __flush_tlb(void)
52 PVOP_VCALL0(mmu.flush_tlb_user);
55 static inline void __flush_tlb_global(void)
57 PVOP_VCALL0(mmu.flush_tlb_kernel);
60 static inline void __flush_tlb_one_user(unsigned long addr)
62 PVOP_VCALL1(mmu.flush_tlb_one_user, addr);
65 static inline void flush_tlb_others(const struct cpumask *cpumask,
66 const struct flush_tlb_info *info)
68 PVOP_VCALL2(mmu.flush_tlb_others, cpumask, info);
71 static inline void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
73 PVOP_VCALL2(mmu.tlb_remove_table, tlb, table);
76 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
78 PVOP_VCALL1(mmu.exit_mmap, mm);
81 #ifdef CONFIG_PARAVIRT_XXL
82 static inline void load_sp0(unsigned long sp0)
84 PVOP_VCALL1(cpu.load_sp0, sp0);
87 /* The paravirtualized CPUID instruction. */
88 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
89 unsigned int *ecx, unsigned int *edx)
91 PVOP_VCALL4(cpu.cpuid, eax, ebx, ecx, edx);
95 * These special macros can be used to get or set a debugging register
97 static inline unsigned long paravirt_get_debugreg(int reg)
99 return PVOP_CALL1(unsigned long, cpu.get_debugreg, reg);
101 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
102 static inline void set_debugreg(unsigned long val, int reg)
104 PVOP_VCALL2(cpu.set_debugreg, reg, val);
107 static inline unsigned long read_cr0(void)
109 return PVOP_CALL0(unsigned long, cpu.read_cr0);
112 static inline void write_cr0(unsigned long x)
114 PVOP_VCALL1(cpu.write_cr0, x);
117 static inline unsigned long read_cr2(void)
119 return PVOP_CALL0(unsigned long, mmu.read_cr2);
122 static inline void write_cr2(unsigned long x)
124 PVOP_VCALL1(mmu.write_cr2, x);
127 static inline unsigned long __read_cr3(void)
129 return PVOP_CALL0(unsigned long, mmu.read_cr3);
132 static inline void write_cr3(unsigned long x)
134 PVOP_VCALL1(mmu.write_cr3, x);
137 static inline void __write_cr4(unsigned long x)
139 PVOP_VCALL1(cpu.write_cr4, x);
143 static inline unsigned long read_cr8(void)
145 return PVOP_CALL0(unsigned long, cpu.read_cr8);
148 static inline void write_cr8(unsigned long x)
150 PVOP_VCALL1(cpu.write_cr8, x);
154 static inline void arch_safe_halt(void)
156 PVOP_VCALL0(irq.safe_halt);
159 static inline void halt(void)
161 PVOP_VCALL0(irq.halt);
164 static inline void wbinvd(void)
166 PVOP_VCALL0(cpu.wbinvd);
169 #define get_kernel_rpl() (pv_info.kernel_rpl)
171 static inline u64 paravirt_read_msr(unsigned msr)
173 return PVOP_CALL1(u64, cpu.read_msr, msr);
176 static inline void paravirt_write_msr(unsigned msr,
177 unsigned low, unsigned high)
179 PVOP_VCALL3(cpu.write_msr, msr, low, high);
182 static inline u64 paravirt_read_msr_safe(unsigned msr, int *err)
184 return PVOP_CALL2(u64, cpu.read_msr_safe, msr, err);
187 static inline int paravirt_write_msr_safe(unsigned msr,
188 unsigned low, unsigned high)
190 return PVOP_CALL3(int, cpu.write_msr_safe, msr, low, high);
193 #define rdmsr(msr, val1, val2) \
195 u64 _l = paravirt_read_msr(msr); \
200 #define wrmsr(msr, val1, val2) \
202 paravirt_write_msr(msr, val1, val2); \
205 #define rdmsrl(msr, val) \
207 val = paravirt_read_msr(msr); \
210 static inline void wrmsrl(unsigned msr, u64 val)
212 wrmsr(msr, (u32)val, (u32)(val>>32));
215 #define wrmsr_safe(msr, a, b) paravirt_write_msr_safe(msr, a, b)
217 /* rdmsr with exception handling */
218 #define rdmsr_safe(msr, a, b) \
221 u64 _l = paravirt_read_msr_safe(msr, &_err); \
227 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
231 *p = paravirt_read_msr_safe(msr, &err);
235 static inline unsigned long long paravirt_read_pmc(int counter)
237 return PVOP_CALL1(u64, cpu.read_pmc, counter);
240 #define rdpmc(counter, low, high) \
242 u64 _l = paravirt_read_pmc(counter); \
247 #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
249 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
251 PVOP_VCALL2(cpu.alloc_ldt, ldt, entries);
254 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
256 PVOP_VCALL2(cpu.free_ldt, ldt, entries);
259 static inline void load_TR_desc(void)
261 PVOP_VCALL0(cpu.load_tr_desc);
263 static inline void load_gdt(const struct desc_ptr *dtr)
265 PVOP_VCALL1(cpu.load_gdt, dtr);
267 static inline void load_idt(const struct desc_ptr *dtr)
269 PVOP_VCALL1(cpu.load_idt, dtr);
271 static inline void set_ldt(const void *addr, unsigned entries)
273 PVOP_VCALL2(cpu.set_ldt, addr, entries);
275 static inline unsigned long paravirt_store_tr(void)
277 return PVOP_CALL0(unsigned long, cpu.store_tr);
280 #define store_tr(tr) ((tr) = paravirt_store_tr())
281 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
283 PVOP_VCALL2(cpu.load_tls, t, cpu);
287 static inline void load_gs_index(unsigned int gs)
289 PVOP_VCALL1(cpu.load_gs_index, gs);
293 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
296 PVOP_VCALL3(cpu.write_ldt_entry, dt, entry, desc);
299 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
300 void *desc, int type)
302 PVOP_VCALL4(cpu.write_gdt_entry, dt, entry, desc, type);
305 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
307 PVOP_VCALL3(cpu.write_idt_entry, dt, entry, g);
309 static inline void set_iopl_mask(unsigned mask)
311 PVOP_VCALL1(cpu.set_iopl_mask, mask);
314 static inline void paravirt_activate_mm(struct mm_struct *prev,
315 struct mm_struct *next)
317 PVOP_VCALL2(mmu.activate_mm, prev, next);
320 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
321 struct mm_struct *mm)
323 PVOP_VCALL2(mmu.dup_mmap, oldmm, mm);
326 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
328 return PVOP_CALL1(int, mmu.pgd_alloc, mm);
331 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
333 PVOP_VCALL2(mmu.pgd_free, mm, pgd);
336 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
338 PVOP_VCALL2(mmu.alloc_pte, mm, pfn);
340 static inline void paravirt_release_pte(unsigned long pfn)
342 PVOP_VCALL1(mmu.release_pte, pfn);
345 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
347 PVOP_VCALL2(mmu.alloc_pmd, mm, pfn);
350 static inline void paravirt_release_pmd(unsigned long pfn)
352 PVOP_VCALL1(mmu.release_pmd, pfn);
355 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
357 PVOP_VCALL2(mmu.alloc_pud, mm, pfn);
359 static inline void paravirt_release_pud(unsigned long pfn)
361 PVOP_VCALL1(mmu.release_pud, pfn);
364 static inline void paravirt_alloc_p4d(struct mm_struct *mm, unsigned long pfn)
366 PVOP_VCALL2(mmu.alloc_p4d, mm, pfn);
369 static inline void paravirt_release_p4d(unsigned long pfn)
371 PVOP_VCALL1(mmu.release_p4d, pfn);
374 static inline pte_t __pte(pteval_t val)
378 if (sizeof(pteval_t) > sizeof(long))
379 ret = PVOP_CALLEE2(pteval_t, mmu.make_pte, val, (u64)val >> 32);
381 ret = PVOP_CALLEE1(pteval_t, mmu.make_pte, val);
383 return (pte_t) { .pte = ret };
386 static inline pteval_t pte_val(pte_t pte)
390 if (sizeof(pteval_t) > sizeof(long))
391 ret = PVOP_CALLEE2(pteval_t, mmu.pte_val,
392 pte.pte, (u64)pte.pte >> 32);
394 ret = PVOP_CALLEE1(pteval_t, mmu.pte_val, pte.pte);
399 static inline pgd_t __pgd(pgdval_t val)
403 if (sizeof(pgdval_t) > sizeof(long))
404 ret = PVOP_CALLEE2(pgdval_t, mmu.make_pgd, val, (u64)val >> 32);
406 ret = PVOP_CALLEE1(pgdval_t, mmu.make_pgd, val);
408 return (pgd_t) { ret };
411 static inline pgdval_t pgd_val(pgd_t pgd)
415 if (sizeof(pgdval_t) > sizeof(long))
416 ret = PVOP_CALLEE2(pgdval_t, mmu.pgd_val,
417 pgd.pgd, (u64)pgd.pgd >> 32);
419 ret = PVOP_CALLEE1(pgdval_t, mmu.pgd_val, pgd.pgd);
424 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
425 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
430 ret = PVOP_CALL3(pteval_t, mmu.ptep_modify_prot_start, mm, addr, ptep);
432 return (pte_t) { .pte = ret };
435 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
436 pte_t *ptep, pte_t pte)
438 if (sizeof(pteval_t) > sizeof(long))
440 pv_ops.mmu.ptep_modify_prot_commit(mm, addr, ptep, pte);
442 PVOP_VCALL4(mmu.ptep_modify_prot_commit,
443 mm, addr, ptep, pte.pte);
446 static inline void set_pte(pte_t *ptep, pte_t pte)
448 if (sizeof(pteval_t) > sizeof(long))
449 PVOP_VCALL3(mmu.set_pte, ptep, pte.pte, (u64)pte.pte >> 32);
451 PVOP_VCALL2(mmu.set_pte, ptep, pte.pte);
454 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
455 pte_t *ptep, pte_t pte)
457 if (sizeof(pteval_t) > sizeof(long))
459 pv_ops.mmu.set_pte_at(mm, addr, ptep, pte);
461 PVOP_VCALL4(mmu.set_pte_at, mm, addr, ptep, pte.pte);
464 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
466 pmdval_t val = native_pmd_val(pmd);
468 if (sizeof(pmdval_t) > sizeof(long))
469 PVOP_VCALL3(mmu.set_pmd, pmdp, val, (u64)val >> 32);
471 PVOP_VCALL2(mmu.set_pmd, pmdp, val);
474 #if CONFIG_PGTABLE_LEVELS >= 3
475 static inline pmd_t __pmd(pmdval_t val)
479 if (sizeof(pmdval_t) > sizeof(long))
480 ret = PVOP_CALLEE2(pmdval_t, mmu.make_pmd, val, (u64)val >> 32);
482 ret = PVOP_CALLEE1(pmdval_t, mmu.make_pmd, val);
484 return (pmd_t) { ret };
487 static inline pmdval_t pmd_val(pmd_t pmd)
491 if (sizeof(pmdval_t) > sizeof(long))
492 ret = PVOP_CALLEE2(pmdval_t, mmu.pmd_val,
493 pmd.pmd, (u64)pmd.pmd >> 32);
495 ret = PVOP_CALLEE1(pmdval_t, mmu.pmd_val, pmd.pmd);
500 static inline void set_pud(pud_t *pudp, pud_t pud)
502 pudval_t val = native_pud_val(pud);
504 if (sizeof(pudval_t) > sizeof(long))
505 PVOP_VCALL3(mmu.set_pud, pudp, val, (u64)val >> 32);
507 PVOP_VCALL2(mmu.set_pud, pudp, val);
509 #if CONFIG_PGTABLE_LEVELS >= 4
510 static inline pud_t __pud(pudval_t val)
514 ret = PVOP_CALLEE1(pudval_t, mmu.make_pud, val);
516 return (pud_t) { ret };
519 static inline pudval_t pud_val(pud_t pud)
521 return PVOP_CALLEE1(pudval_t, mmu.pud_val, pud.pud);
524 static inline void pud_clear(pud_t *pudp)
526 set_pud(pudp, __pud(0));
529 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
531 p4dval_t val = native_p4d_val(p4d);
533 PVOP_VCALL2(mmu.set_p4d, p4dp, val);
536 #if CONFIG_PGTABLE_LEVELS >= 5
538 static inline p4d_t __p4d(p4dval_t val)
540 p4dval_t ret = PVOP_CALLEE1(p4dval_t, mmu.make_p4d, val);
542 return (p4d_t) { ret };
545 static inline p4dval_t p4d_val(p4d_t p4d)
547 return PVOP_CALLEE1(p4dval_t, mmu.p4d_val, p4d.p4d);
550 static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
552 PVOP_VCALL2(mmu.set_pgd, pgdp, native_pgd_val(pgd));
555 #define set_pgd(pgdp, pgdval) do { \
556 if (pgtable_l5_enabled()) \
557 __set_pgd(pgdp, pgdval); \
559 set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd }); \
562 #define pgd_clear(pgdp) do { \
563 if (pgtable_l5_enabled()) \
564 set_pgd(pgdp, __pgd(0)); \
567 #endif /* CONFIG_PGTABLE_LEVELS == 5 */
569 static inline void p4d_clear(p4d_t *p4dp)
571 set_p4d(p4dp, __p4d(0));
574 #endif /* CONFIG_PGTABLE_LEVELS == 4 */
576 #endif /* CONFIG_PGTABLE_LEVELS >= 3 */
578 #ifdef CONFIG_X86_PAE
579 /* Special-case pte-setting operations for PAE, which can't update a
580 64-bit pte atomically */
581 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
583 PVOP_VCALL3(mmu.set_pte_atomic, ptep, pte.pte, pte.pte >> 32);
586 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
589 PVOP_VCALL3(mmu.pte_clear, mm, addr, ptep);
592 static inline void pmd_clear(pmd_t *pmdp)
594 PVOP_VCALL1(mmu.pmd_clear, pmdp);
596 #else /* !CONFIG_X86_PAE */
597 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
602 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
605 set_pte_at(mm, addr, ptep, __pte(0));
608 static inline void pmd_clear(pmd_t *pmdp)
610 set_pmd(pmdp, __pmd(0));
612 #endif /* CONFIG_X86_PAE */
614 #define __HAVE_ARCH_START_CONTEXT_SWITCH
615 static inline void arch_start_context_switch(struct task_struct *prev)
617 PVOP_VCALL1(cpu.start_context_switch, prev);
620 static inline void arch_end_context_switch(struct task_struct *next)
622 PVOP_VCALL1(cpu.end_context_switch, next);
625 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
626 static inline void arch_enter_lazy_mmu_mode(void)
628 PVOP_VCALL0(mmu.lazy_mode.enter);
631 static inline void arch_leave_lazy_mmu_mode(void)
633 PVOP_VCALL0(mmu.lazy_mode.leave);
636 static inline void arch_flush_lazy_mmu_mode(void)
638 PVOP_VCALL0(mmu.lazy_mode.flush);
641 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
642 phys_addr_t phys, pgprot_t flags)
644 pv_ops.mmu.set_fixmap(idx, phys, flags);
648 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
650 static __always_inline void pv_queued_spin_lock_slowpath(struct qspinlock *lock,
653 PVOP_VCALL2(lock.queued_spin_lock_slowpath, lock, val);
656 static __always_inline void pv_queued_spin_unlock(struct qspinlock *lock)
658 PVOP_VCALLEE1(lock.queued_spin_unlock, lock);
661 static __always_inline void pv_wait(u8 *ptr, u8 val)
663 PVOP_VCALL2(lock.wait, ptr, val);
666 static __always_inline void pv_kick(int cpu)
668 PVOP_VCALL1(lock.kick, cpu);
671 static __always_inline bool pv_vcpu_is_preempted(long cpu)
673 return PVOP_CALLEE1(bool, lock.vcpu_is_preempted, cpu);
676 void __raw_callee_save___native_queued_spin_unlock(struct qspinlock *lock);
677 bool __raw_callee_save___native_vcpu_is_preempted(long cpu);
679 #endif /* SMP && PARAVIRT_SPINLOCKS */
682 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
683 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
685 /* save and restore all caller-save registers, except return value */
686 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
687 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
689 #define PV_FLAGS_ARG "0"
690 #define PV_EXTRA_CLOBBERS
691 #define PV_VEXTRA_CLOBBERS
693 /* save and restore all caller-save registers, except return value */
694 #define PV_SAVE_ALL_CALLER_REGS \
703 #define PV_RESTORE_ALL_CALLER_REGS \
713 /* We save some registers, but all of them, that's too much. We clobber all
714 * caller saved registers but the argument parameter */
715 #define PV_SAVE_REGS "pushq %%rdi;"
716 #define PV_RESTORE_REGS "popq %%rdi;"
717 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
718 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
719 #define PV_FLAGS_ARG "D"
723 * Generate a thunk around a function which saves all caller-save
724 * registers except for the return value. This allows C functions to
725 * be called from assembler code where fewer than normal registers are
726 * available. It may also help code generation around calls from C
727 * code if the common case doesn't use many registers.
729 * When a callee is wrapped in a thunk, the caller can assume that all
730 * arg regs and all scratch registers are preserved across the
731 * call. The return value in rax/eax will not be saved, even for void
734 #define PV_THUNK_NAME(func) "__raw_callee_save_" #func
735 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
736 extern typeof(func) __raw_callee_save_##func; \
738 asm(".pushsection .text;" \
739 ".globl " PV_THUNK_NAME(func) ";" \
740 ".type " PV_THUNK_NAME(func) ", @function;" \
741 PV_THUNK_NAME(func) ":" \
743 PV_SAVE_ALL_CALLER_REGS \
745 PV_RESTORE_ALL_CALLER_REGS \
750 /* Get a reference to a callee-save function */
751 #define PV_CALLEE_SAVE(func) \
752 ((struct paravirt_callee_save) { __raw_callee_save_##func })
754 /* Promise that "func" already uses the right calling convention */
755 #define __PV_IS_CALLEE_SAVE(func) \
756 ((struct paravirt_callee_save) { func })
758 #ifdef CONFIG_PARAVIRT_XXL
759 static inline notrace unsigned long arch_local_save_flags(void)
761 return PVOP_CALLEE0(unsigned long, irq.save_fl);
764 static inline notrace void arch_local_irq_restore(unsigned long f)
766 PVOP_VCALLEE1(irq.restore_fl, f);
769 static inline notrace void arch_local_irq_disable(void)
771 PVOP_VCALLEE0(irq.irq_disable);
774 static inline notrace void arch_local_irq_enable(void)
776 PVOP_VCALLEE0(irq.irq_enable);
779 static inline notrace unsigned long arch_local_irq_save(void)
783 f = arch_local_save_flags();
784 arch_local_irq_disable();
790 /* Make sure as little as possible of this mess escapes. */
805 extern void default_banner(void);
807 #else /* __ASSEMBLY__ */
809 #define _PVSITE(ptype, ops, word, algn) \
813 .pushsection .parainstructions,"a"; \
821 #define COND_PUSH(set, mask, reg) \
822 .if ((~(set)) & mask); push %reg; .endif
823 #define COND_POP(set, mask, reg) \
824 .if ((~(set)) & mask); pop %reg; .endif
828 #define PV_SAVE_REGS(set) \
829 COND_PUSH(set, CLBR_RAX, rax); \
830 COND_PUSH(set, CLBR_RCX, rcx); \
831 COND_PUSH(set, CLBR_RDX, rdx); \
832 COND_PUSH(set, CLBR_RSI, rsi); \
833 COND_PUSH(set, CLBR_RDI, rdi); \
834 COND_PUSH(set, CLBR_R8, r8); \
835 COND_PUSH(set, CLBR_R9, r9); \
836 COND_PUSH(set, CLBR_R10, r10); \
837 COND_PUSH(set, CLBR_R11, r11)
838 #define PV_RESTORE_REGS(set) \
839 COND_POP(set, CLBR_R11, r11); \
840 COND_POP(set, CLBR_R10, r10); \
841 COND_POP(set, CLBR_R9, r9); \
842 COND_POP(set, CLBR_R8, r8); \
843 COND_POP(set, CLBR_RDI, rdi); \
844 COND_POP(set, CLBR_RSI, rsi); \
845 COND_POP(set, CLBR_RDX, rdx); \
846 COND_POP(set, CLBR_RCX, rcx); \
847 COND_POP(set, CLBR_RAX, rax)
849 #define PARA_PATCH(off) ((off) / 8)
850 #define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .quad, 8)
851 #define PARA_INDIRECT(addr) *addr(%rip)
853 #define PV_SAVE_REGS(set) \
854 COND_PUSH(set, CLBR_EAX, eax); \
855 COND_PUSH(set, CLBR_EDI, edi); \
856 COND_PUSH(set, CLBR_ECX, ecx); \
857 COND_PUSH(set, CLBR_EDX, edx)
858 #define PV_RESTORE_REGS(set) \
859 COND_POP(set, CLBR_EDX, edx); \
860 COND_POP(set, CLBR_ECX, ecx); \
861 COND_POP(set, CLBR_EDI, edi); \
862 COND_POP(set, CLBR_EAX, eax)
864 #define PARA_PATCH(off) ((off) / 4)
865 #define PARA_SITE(ptype, ops) _PVSITE(ptype, ops, .long, 4)
866 #define PARA_INDIRECT(addr) *%cs:addr
869 #ifdef CONFIG_PARAVIRT_XXL
870 #define INTERRUPT_RETURN \
871 PARA_SITE(PARA_PATCH(PV_CPU_iret), \
872 ANNOTATE_RETPOLINE_SAFE; \
873 jmp PARA_INDIRECT(pv_ops+PV_CPU_iret);)
875 #define DISABLE_INTERRUPTS(clobbers) \
876 PARA_SITE(PARA_PATCH(PV_IRQ_irq_disable), \
877 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
878 ANNOTATE_RETPOLINE_SAFE; \
879 call PARA_INDIRECT(pv_ops+PV_IRQ_irq_disable); \
880 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
882 #define ENABLE_INTERRUPTS(clobbers) \
883 PARA_SITE(PARA_PATCH(PV_IRQ_irq_enable), \
884 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
885 ANNOTATE_RETPOLINE_SAFE; \
886 call PARA_INDIRECT(pv_ops+PV_IRQ_irq_enable); \
887 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
891 #ifdef CONFIG_PARAVIRT_XXL
893 * If swapgs is used while the userspace stack is still current,
894 * there's no way to call a pvop. The PV replacement *must* be
895 * inlined, or the swapgs instruction must be trapped and emulated.
897 #define SWAPGS_UNSAFE_STACK \
898 PARA_SITE(PARA_PATCH(PV_CPU_swapgs), swapgs)
901 * Note: swapgs is very special, and in practise is either going to be
902 * implemented with a single "swapgs" instruction or something very
903 * special. Either way, we don't need to save any registers for
907 PARA_SITE(PARA_PATCH(PV_CPU_swapgs), \
908 ANNOTATE_RETPOLINE_SAFE; \
909 call PARA_INDIRECT(pv_ops+PV_CPU_swapgs); \
913 #define GET_CR2_INTO_RAX \
914 ANNOTATE_RETPOLINE_SAFE; \
915 call PARA_INDIRECT(pv_ops+PV_MMU_read_cr2);
917 #ifdef CONFIG_PARAVIRT_XXL
918 #define USERGS_SYSRET64 \
919 PARA_SITE(PARA_PATCH(PV_CPU_usergs_sysret64), \
920 ANNOTATE_RETPOLINE_SAFE; \
921 jmp PARA_INDIRECT(pv_ops+PV_CPU_usergs_sysret64);)
923 #ifdef CONFIG_DEBUG_ENTRY
924 #define SAVE_FLAGS(clobbers) \
925 PARA_SITE(PARA_PATCH(PV_IRQ_save_fl), \
926 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
927 ANNOTATE_RETPOLINE_SAFE; \
928 call PARA_INDIRECT(pv_ops+PV_IRQ_save_fl); \
929 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
933 #endif /* CONFIG_X86_32 */
935 #endif /* __ASSEMBLY__ */
936 #else /* CONFIG_PARAVIRT */
937 # define default_banner x86_init_noop
938 #endif /* !CONFIG_PARAVIRT */
941 #ifndef CONFIG_PARAVIRT_XXL
942 static inline void paravirt_arch_dup_mmap(struct mm_struct *oldmm,
943 struct mm_struct *mm)
948 #ifndef CONFIG_PARAVIRT
949 static inline void paravirt_arch_exit_mmap(struct mm_struct *mm)
953 #endif /* __ASSEMBLY__ */
954 #endif /* _ASM_X86_PARAVIRT_H */