1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
4 #define _ASM_X86_NOSPEC_BRANCH_H_
6 #include <linux/static_key.h>
7 #include <linux/objtool.h>
8 #include <linux/linkage.h>
10 #include <asm/alternative.h>
11 #include <asm/cpufeatures.h>
12 #include <asm/msr-index.h>
13 #include <asm/unwind_hints.h>
14 #include <asm/percpu.h>
15 #include <asm/current.h>
18 * Call depth tracking for Intel SKL CPUs to address the RSB underflow
21 * The tracking does not use a counter. It uses uses arithmetic shift
22 * right on call entry and logical shift left on return.
24 * The depth tracking variable is initialized to 0x8000.... when the call
25 * depth is zero. The arithmetic shift right sign extends the MSB and
26 * saturates after the 12th call. The shift count is 5 for both directions
27 * so the tracking covers 12 nested calls.
30 * 0: 0x8000000000000000 0x0000000000000000
31 * 1: 0xfc00000000000000 0xf000000000000000
33 * 11: 0xfffffffffffffff8 0xfffffffffffffc00
34 * 12: 0xffffffffffffffff 0xffffffffffffffe0
36 * After a return buffer fill the depth is credited 12 calls before the
37 * next stuffing has to take place.
39 * There is a inaccuracy for situations like this:
48 * The shift count might cause this to be off by one in either direction,
49 * but there is still a cushion vs. the RSB depth. The algorithm does not
50 * claim to be perfect and it can be speculated around by the CPU, but it
51 * is considered that it obfuscates the problem enough to make exploitation
52 * extremely difficult.
54 #define RET_DEPTH_SHIFT 5
55 #define RSB_RET_STUFF_LOOPS 16
56 #define RET_DEPTH_INIT 0x8000000000000000ULL
57 #define RET_DEPTH_INIT_FROM_CALL 0xfc00000000000000ULL
58 #define RET_DEPTH_CREDIT 0xffffffffffffffffULL
60 #ifdef CONFIG_CALL_THUNKS_DEBUG
61 # define CALL_THUNKS_DEBUG_INC_CALLS \
62 incq PER_CPU_VAR(__x86_call_count);
63 # define CALL_THUNKS_DEBUG_INC_RETS \
64 incq PER_CPU_VAR(__x86_ret_count);
65 # define CALL_THUNKS_DEBUG_INC_STUFFS \
66 incq PER_CPU_VAR(__x86_stuffs_count);
67 # define CALL_THUNKS_DEBUG_INC_CTXSW \
68 incq PER_CPU_VAR(__x86_ctxsw_count);
70 # define CALL_THUNKS_DEBUG_INC_CALLS
71 # define CALL_THUNKS_DEBUG_INC_RETS
72 # define CALL_THUNKS_DEBUG_INC_STUFFS
73 # define CALL_THUNKS_DEBUG_INC_CTXSW
76 #if defined(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && !defined(COMPILE_OFFSETS)
78 #include <asm/asm-offsets.h>
80 #define CREDIT_CALL_DEPTH \
81 movq $-1, PER_CPU_VAR(pcpu_hot + X86_call_depth);
83 #define RESET_CALL_DEPTH \
86 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth);
88 #define RESET_CALL_DEPTH_FROM_CALL \
91 movq %rax, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
92 CALL_THUNKS_DEBUG_INC_CALLS
94 #define INCREMENT_CALL_DEPTH \
95 sarq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth); \
96 CALL_THUNKS_DEBUG_INC_CALLS
99 #define CREDIT_CALL_DEPTH
100 #define RESET_CALL_DEPTH
101 #define RESET_CALL_DEPTH_FROM_CALL
102 #define INCREMENT_CALL_DEPTH
106 * Fill the CPU return stack buffer.
108 * Each entry in the RSB, if used for a speculative 'ret', contains an
109 * infinite 'pause; lfence; jmp' loop to capture speculative execution.
111 * This is required in various cases for retpoline and IBRS-based
112 * mitigations for the Spectre variant 2 vulnerability. Sometimes to
113 * eliminate potentially bogus entries from the RSB, and sometimes
114 * purely to ensure that it doesn't get empty, which on some CPUs would
115 * allow predictions from other (unwanted!) sources to be used.
117 * We define a CPP macro such that it can be used from both .S files and
118 * inline assembly. It's possible to do a .macro and then include that
119 * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
122 #define RETPOLINE_THUNK_SIZE 32
123 #define RSB_CLEAR_LOOPS 32 /* To forcibly overwrite all entries */
126 * Common helper for __FILL_RETURN_BUFFER and __FILL_ONE_RETURN.
128 #define __FILL_RETURN_SLOT \
129 ANNOTATE_INTRA_FUNCTION_CALL; \
135 * Stuff the entire RSB.
137 * Google experimented with loop-unrolling and this turned out to be
138 * the optimal version - two calls, each with their own speculation
139 * trap should their return address end up getting used, in a loop.
142 #define __FILL_RETURN_BUFFER(reg, nr) \
147 add $(BITS_PER_LONG/8) * 2, %_ASM_SP; \
150 /* barrier for jnz misprediction */ \
153 CALL_THUNKS_DEBUG_INC_CTXSW
156 * i386 doesn't unconditionally have LFENCE, as such it can't
159 #define __FILL_RETURN_BUFFER(reg, nr) \
161 __FILL_RETURN_SLOT; \
163 add $(BITS_PER_LONG/8) * nr, %_ASM_SP;
167 * Stuff a single RSB slot.
169 * To mitigate Post-Barrier RSB speculation, one CALL instruction must be
170 * forced to retire before letting a RET instruction execute.
172 * On PBRSB-vulnerable CPUs, it is not safe for a RET to be executed
175 #define __FILL_ONE_RETURN \
177 add $(BITS_PER_LONG/8), %_ASM_SP; \
183 * This should be used immediately before an indirect jump/call. It tells
184 * objtool the subsequent indirect jump/call is vouched safe for retpoline
187 .macro ANNOTATE_RETPOLINE_SAFE
189 .pushsection .discard.retpoline_safe
195 * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
196 * vs RETBleed validation.
198 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
201 * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
202 * eventually turn into its own annotation.
204 .macro VALIDATE_UNRET_END
205 #if defined(CONFIG_NOINSTR_VALIDATION) && \
206 (defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO))
207 ANNOTATE_RETPOLINE_SAFE
213 * Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call
214 * to the retpoline thunk with a CS prefix when the register requires
215 * a RAX prefix byte to encode. Also see apply_retpolines().
217 .macro __CS_PREFIX reg:req
218 .irp rs,r8,r9,r10,r11,r12,r13,r14,r15
226 * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
227 * indirect jmp/call which may be susceptible to the Spectre variant 2
230 * NOTE: these do not take kCFI into account and are thus not comparable to C
231 * indirect calls, take care when using. The target of these should be an ENDBR
232 * instruction irrespective of kCFI.
234 .macro JMP_NOSPEC reg:req
235 #ifdef CONFIG_MITIGATION_RETPOLINE
237 jmp __x86_indirect_thunk_\reg
244 .macro CALL_NOSPEC reg:req
245 #ifdef CONFIG_MITIGATION_RETPOLINE
247 call __x86_indirect_thunk_\reg
254 * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
255 * monstrosity above, manually.
257 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2=ALT_NOT(X86_FEATURE_ALWAYS)
258 ALTERNATIVE_2 "jmp .Lskip_rsb_\@", \
259 __stringify(__FILL_RETURN_BUFFER(\reg,\nr)), \ftr, \
260 __stringify(nop;nop;__FILL_ONE_RETURN), \ftr2
265 #if defined(CONFIG_MITIGATION_UNRET_ENTRY) || defined(CONFIG_MITIGATION_SRSO)
266 #define CALL_UNTRAIN_RET "call entry_untrain_ret"
268 #define CALL_UNTRAIN_RET ""
272 * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
273 * return thunk isn't mapped into the userspace tables (then again, AMD
274 * typically has NO_MELTDOWN).
276 * While retbleed_untrain_ret() doesn't clobber anything but requires stack,
277 * entry_ibpb() will clobber AX, CX, DX.
279 * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
280 * where we have a stack but before any RET instruction.
282 .macro __UNTRAIN_RET ibpb_feature, call_depth_insns
283 #if defined(CONFIG_MITIGATION_RETHUNK) || defined(CONFIG_MITIGATION_IBPB_ENTRY)
286 CALL_UNTRAIN_RET, X86_FEATURE_UNRET, \
287 "call entry_ibpb", \ibpb_feature, \
288 __stringify(\call_depth_insns), X86_FEATURE_CALL_DEPTH
292 #define UNTRAIN_RET \
293 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH)
295 #define UNTRAIN_RET_VM \
296 __UNTRAIN_RET X86_FEATURE_IBPB_ON_VMEXIT, __stringify(RESET_CALL_DEPTH)
298 #define UNTRAIN_RET_FROM_CALL \
299 __UNTRAIN_RET X86_FEATURE_ENTRY_IBPB, __stringify(RESET_CALL_DEPTH_FROM_CALL)
302 .macro CALL_DEPTH_ACCOUNT
303 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING
305 __stringify(INCREMENT_CALL_DEPTH), X86_FEATURE_CALL_DEPTH
310 * Macro to execute VERW instruction that mitigate transient data sampling
311 * attacks such as MDS. On affected systems a microcode update overloaded VERW
312 * instruction to also clear the CPU buffers. VERW clobbers CFLAGS.ZF.
314 * Note: Only the memory operand variant of VERW clears the CPU buffers.
316 .macro CLEAR_CPU_BUFFERS
317 ALTERNATIVE "", __stringify(verw _ASM_RIP(mds_verw_sel)), X86_FEATURE_CLEAR_CPU_BUF
320 #else /* __ASSEMBLY__ */
322 #define ANNOTATE_RETPOLINE_SAFE \
324 ".pushsection .discard.retpoline_safe\n\t" \
328 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
329 extern retpoline_thunk_t __x86_indirect_thunk_array[];
330 extern retpoline_thunk_t __x86_indirect_call_thunk_array[];
331 extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];
333 #ifdef CONFIG_MITIGATION_RETHUNK
334 extern void __x86_return_thunk(void);
336 static inline void __x86_return_thunk(void) {}
339 #ifdef CONFIG_MITIGATION_UNRET_ENTRY
340 extern void retbleed_return_thunk(void);
342 static inline void retbleed_return_thunk(void) {}
345 #ifdef CONFIG_MITIGATION_SRSO
346 extern void srso_return_thunk(void);
347 extern void srso_alias_return_thunk(void);
349 static inline void srso_return_thunk(void) {}
350 static inline void srso_alias_return_thunk(void) {}
353 extern void retbleed_return_thunk(void);
354 extern void srso_return_thunk(void);
355 extern void srso_alias_return_thunk(void);
357 extern void entry_untrain_ret(void);
358 extern void entry_ibpb(void);
360 extern void (*x86_return_thunk)(void);
362 extern void __warn_thunk(void);
364 #ifdef CONFIG_MITIGATION_CALL_DEPTH_TRACKING
365 extern void call_depth_return_thunk(void);
367 #define CALL_DEPTH_ACCOUNT \
369 __stringify(INCREMENT_CALL_DEPTH), \
370 X86_FEATURE_CALL_DEPTH)
372 #ifdef CONFIG_CALL_THUNKS_DEBUG
373 DECLARE_PER_CPU(u64, __x86_call_count);
374 DECLARE_PER_CPU(u64, __x86_ret_count);
375 DECLARE_PER_CPU(u64, __x86_stuffs_count);
376 DECLARE_PER_CPU(u64, __x86_ctxsw_count);
378 #else /* !CONFIG_MITIGATION_CALL_DEPTH_TRACKING */
380 static inline void call_depth_return_thunk(void) {}
381 #define CALL_DEPTH_ACCOUNT ""
383 #endif /* CONFIG_MITIGATION_CALL_DEPTH_TRACKING */
385 #ifdef CONFIG_MITIGATION_RETPOLINE
388 extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
389 #include <asm/GEN-for-each-reg.h>
393 extern retpoline_thunk_t __x86_indirect_call_thunk_ ## reg;
394 #include <asm/GEN-for-each-reg.h>
398 extern retpoline_thunk_t __x86_indirect_jump_thunk_ ## reg;
399 #include <asm/GEN-for-each-reg.h>
405 * Inline asm uses the %V modifier which is only in newer GCC
406 * which is ensured when CONFIG_MITIGATION_RETPOLINE is defined.
408 # define CALL_NOSPEC \
410 ANNOTATE_RETPOLINE_SAFE \
411 "call *%[thunk_target]\n", \
412 "call __x86_indirect_thunk_%V[thunk_target]\n", \
413 X86_FEATURE_RETPOLINE, \
415 ANNOTATE_RETPOLINE_SAFE \
416 "call *%[thunk_target]\n", \
417 X86_FEATURE_RETPOLINE_LFENCE)
419 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
421 #else /* CONFIG_X86_32 */
423 * For i386 we use the original ret-equivalent retpoline, because
424 * otherwise we'll run out of registers. We don't care about CET
427 # define CALL_NOSPEC \
429 ANNOTATE_RETPOLINE_SAFE \
430 "call *%[thunk_target]\n", \
433 "901: call 903f;\n" \
438 "903: lea 4(%%esp), %%esp;\n" \
439 " pushl %[thunk_target];\n" \
442 "904: call 901b;\n", \
443 X86_FEATURE_RETPOLINE, \
445 ANNOTATE_RETPOLINE_SAFE \
446 "call *%[thunk_target]\n", \
447 X86_FEATURE_RETPOLINE_LFENCE)
449 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
451 #else /* No retpoline for C / inline asm */
452 # define CALL_NOSPEC "call *%[thunk_target]\n"
453 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
456 /* The Spectre V2 mitigation variants */
457 enum spectre_v2_mitigation {
459 SPECTRE_V2_RETPOLINE,
462 SPECTRE_V2_EIBRS_RETPOLINE,
463 SPECTRE_V2_EIBRS_LFENCE,
467 /* The indirect branch speculation control variants */
468 enum spectre_v2_user_mitigation {
469 SPECTRE_V2_USER_NONE,
470 SPECTRE_V2_USER_STRICT,
471 SPECTRE_V2_USER_STRICT_PREFERRED,
472 SPECTRE_V2_USER_PRCTL,
473 SPECTRE_V2_USER_SECCOMP,
476 /* The Speculative Store Bypass disable variants */
477 enum ssb_mitigation {
478 SPEC_STORE_BYPASS_NONE,
479 SPEC_STORE_BYPASS_DISABLE,
480 SPEC_STORE_BYPASS_PRCTL,
481 SPEC_STORE_BYPASS_SECCOMP,
484 static __always_inline
485 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
487 asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
490 "d" ((u32)(val >> 32)),
491 [feature] "i" (feature)
495 extern u64 x86_pred_cmd;
497 static inline void indirect_branch_prediction_barrier(void)
499 alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
502 /* The Intel SPEC CTRL MSR base value cache */
503 extern u64 x86_spec_ctrl_base;
504 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
505 extern void update_spec_ctrl_cond(u64 val);
506 extern u64 spec_ctrl_current(void);
509 * With retpoline, we must use IBRS to restrict branch prediction
510 * before calling into firmware.
512 * (Implemented as CPP macros due to header hell.)
514 #define firmware_restrict_branch_speculation_start() \
517 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
518 spec_ctrl_current() | SPEC_CTRL_IBRS, \
519 X86_FEATURE_USE_IBRS_FW); \
520 alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, \
521 X86_FEATURE_USE_IBPB_FW); \
524 #define firmware_restrict_branch_speculation_end() \
526 alternative_msr_write(MSR_IA32_SPEC_CTRL, \
527 spec_ctrl_current(), \
528 X86_FEATURE_USE_IBRS_FW); \
532 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
533 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
534 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
536 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
538 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
540 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
542 extern u16 mds_verw_sel;
544 #include <asm/segment.h>
547 * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
549 * This uses the otherwise unused and obsolete VERW instruction in
550 * combination with microcode which triggers a CPU buffer flush when the
551 * instruction is executed.
553 static __always_inline void mds_clear_cpu_buffers(void)
555 static const u16 ds = __KERNEL_DS;
558 * Has to be the memory-operand variant because only that
559 * guarantees the CPU buffer flush functionality according to
560 * documentation. The register-operand variant does not.
561 * Works with any segment selector, but a valid writable
562 * data segment is the fastest variant.
564 * "cc" clobber is required because VERW modifies ZF.
566 asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
570 * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
572 * Clear CPU buffers if the corresponding static key is enabled
574 static __always_inline void mds_idle_clear_cpu_buffers(void)
576 if (static_branch_likely(&mds_idle_clear))
577 mds_clear_cpu_buffers();
580 #endif /* __ASSEMBLY__ */
582 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */