arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7 #include <linux/objtool.h>
   8 #include <linux/linkage.h>
   9
  10 #include <asm/alternative.h>
  11 #include <asm/cpufeatures.h>
  12 #include <asm/msr-index.h>
  13 #include <asm/unwind_hints.h>
  14 #include <asm/percpu.h>
  15
  16 #define RETPOLINE_THUNK_SIZE    32
  17
  18 /*
  19  * Fill the CPU return stack buffer.
  20  *
  21  * Each entry in the RSB, if used for a speculative 'ret', contains an
  22  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  23  *
  24  * This is required in various cases for retpoline and IBRS-based
  25  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  26  * eliminate potentially bogus entries from the RSB, and sometimes
  27  * purely to ensure that it doesn't get empty, which on some CPUs would
  28  * allow predictions from other (unwanted!) sources to be used.
  29  *
  30  * We define a CPP macro such that it can be used from both .S files and
  31  * inline assembly. It's possible to do a .macro and then include that
  32  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  33  */
  34
  35 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  36
  37 /*
  38  * Google experimented with loop-unrolling and this turned out to be
  39  * the optimal version - two calls, each with their own speculation
  40  * trap should their return address end up getting used, in a loop.
  41  */
  42 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  43         mov     $(nr/2), reg;                   \
  44 771:                                            \
  45         ANNOTATE_INTRA_FUNCTION_CALL;           \
  46         call    772f;                           \
  47 773:    /* speculation trap */                  \
  48         UNWIND_HINT_EMPTY;                      \
  49         pause;                                  \
  50         lfence;                                 \
  51         jmp     773b;                           \
  52 772:                                            \
  53         ANNOTATE_INTRA_FUNCTION_CALL;           \
  54         call    774f;                           \
  55 775:    /* speculation trap */                  \
  56         UNWIND_HINT_EMPTY;                      \
  57         pause;                                  \
  58         lfence;                                 \
  59         jmp     775b;                           \
  60 774:                                            \
  61         add     $(BITS_PER_LONG/8) * 2, sp;     \
  62         dec     reg;                            \
  63         jnz     771b;                           \
  64         /* barrier for jnz misprediction */     \
  65         lfence;
  66
  67 #ifdef __ASSEMBLY__
  68
  69 /*
  70  * This should be used immediately before an indirect jump/call. It tells
  71  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  72  * builds.
  73  */
  74 .macro ANNOTATE_RETPOLINE_SAFE
  75         .Lannotate_\@:
  76         .pushsection .discard.retpoline_safe
  77         _ASM_PTR .Lannotate_\@
  78         .popsection
  79 .endm
  80
  81 /*
  82  * (ab)use RETPOLINE_SAFE on RET to annotate away 'bare' RET instructions
  83  * vs RETBleed validation.
  84  */
  85 #define ANNOTATE_UNRET_SAFE ANNOTATE_RETPOLINE_SAFE
  86
  87 /*
  88  * Abuse ANNOTATE_RETPOLINE_SAFE on a NOP to indicate UNRET_END, should
  89  * eventually turn into it's own annotation.
  90  */
  91 .macro ANNOTATE_UNRET_END
  92 #ifdef CONFIG_DEBUG_ENTRY
  93         ANNOTATE_RETPOLINE_SAFE
  94         nop
  95 #endif
  96 .endm
  97
  98 /*
  99  * Equivalent to -mindirect-branch-cs-prefix; emit the 5 byte jmp/call
 100  * to the retpoline thunk with a CS prefix when the register requires
 101  * a RAX prefix byte to encode. Also see apply_retpolines().
 102  */
 103 .macro __CS_PREFIX reg:req
 104         .irp rs,r8,r9,r10,r11,r12,r13,r14,r15
 105         .ifc \reg,\rs
 106         .byte 0x2e
 107         .endif
 108         .endr
 109 .endm
 110
 111 /*
 112  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
 113  * indirect jmp/call which may be susceptible to the Spectre variant 2
 114  * attack.
 115  */
 116 .macro JMP_NOSPEC reg:req
 117 #ifdef CONFIG_RETPOLINE
 118         __CS_PREFIX \reg
 119         jmp     __x86_indirect_thunk_\reg
 120 #else
 121         jmp     *%\reg
 122         int3
 123 #endif
 124 .endm
 125
 126 .macro CALL_NOSPEC reg:req
 127 #ifdef CONFIG_RETPOLINE
 128         __CS_PREFIX \reg
 129         call    __x86_indirect_thunk_\reg
 130 #else
 131         call    *%\reg
 132 #endif
 133 .endm
 134
 135 .macro ISSUE_UNBALANCED_RET_GUARD
 136         ANNOTATE_INTRA_FUNCTION_CALL
 137         call .Lunbalanced_ret_guard_\@
 138         int3
 139 .Lunbalanced_ret_guard_\@:
 140         add $(BITS_PER_LONG/8), %_ASM_SP
 141         lfence
 142 .endm
 143
 144  /*
 145   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 146   * monstrosity above, manually.
 147   */
 148 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req ftr2
 149 .ifb \ftr2
 150         ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
 151 .else
 152         ALTERNATIVE_2 "jmp .Lskip_rsb_\@", "", \ftr, "jmp .Lunbalanced_\@", \ftr2
 153 .endif
 154         __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
 155 .Lunbalanced_\@:
 156         ISSUE_UNBALANCED_RET_GUARD
 157 .Lskip_rsb_\@:
 158 .endm
 159
 160 #ifdef CONFIG_CPU_UNRET_ENTRY
 161 #define CALL_ZEN_UNTRAIN_RET    "call zen_untrain_ret"
 162 #else
 163 #define CALL_ZEN_UNTRAIN_RET    ""
 164 #endif
 165
 166 /*
 167  * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
 168  * return thunk isn't mapped into the userspace tables (then again, AMD
 169  * typically has NO_MELTDOWN).
 170  *
 171  * While zen_untrain_ret() doesn't clobber anything but requires stack,
 172  * entry_ibpb() will clobber AX, CX, DX.
 173  *
 174  * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
 175  * where we have a stack but before any RET instruction.
 176  */
 177 .macro UNTRAIN_RET
 178 #if defined(CONFIG_CPU_UNRET_ENTRY) || defined(CONFIG_CPU_IBPB_ENTRY)
 179         ANNOTATE_UNRET_END
 180         ALTERNATIVE_2 "",                                               \
 181                       CALL_ZEN_UNTRAIN_RET, X86_FEATURE_UNRET,          \
 182                       "call entry_ibpb", X86_FEATURE_ENTRY_IBPB
 183 #endif
 184 .endm
 185
 186 #else /* __ASSEMBLY__ */
 187
 188 #define ANNOTATE_RETPOLINE_SAFE                                 \
 189         "999:\n\t"                                              \
 190         ".pushsection .discard.retpoline_safe\n\t"              \
 191         _ASM_PTR " 999b\n\t"                                    \
 192         ".popsection\n\t"
 193
 194 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
 195 extern retpoline_thunk_t __x86_indirect_thunk_array[];
 196
 197 extern void __x86_return_thunk(void);
 198 extern void zen_untrain_ret(void);
 199 extern void entry_ibpb(void);
 200
 201 #ifdef CONFIG_RETPOLINE
 202
 203 #define GEN(reg) \
 204         extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
 205 #include <asm/GEN-for-each-reg.h>
 206 #undef GEN
 207
 208 #ifdef CONFIG_X86_64
 209
 210 /*
 211  * Inline asm uses the %V modifier which is only in newer GCC
 212  * which is ensured when CONFIG_RETPOLINE is defined.
 213  */
 214 # define CALL_NOSPEC                                            \
 215         ALTERNATIVE_2(                                          \
 216         ANNOTATE_RETPOLINE_SAFE                                 \
 217         "call *%[thunk_target]\n",                              \
 218         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 219         X86_FEATURE_RETPOLINE,                                  \
 220         "lfence;\n"                                             \
 221         ANNOTATE_RETPOLINE_SAFE                                 \
 222         "call *%[thunk_target]\n",                              \
 223         X86_FEATURE_RETPOLINE_LFENCE)
 224
 225 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 226
 227 #else /* CONFIG_X86_32 */
 228 /*
 229  * For i386 we use the original ret-equivalent retpoline, because
 230  * otherwise we'll run out of registers. We don't care about CET
 231  * here, anyway.
 232  */
 233 # define CALL_NOSPEC                                            \
 234         ALTERNATIVE_2(                                          \
 235         ANNOTATE_RETPOLINE_SAFE                                 \
 236         "call *%[thunk_target]\n",                              \
 237         "       jmp    904f;\n"                                 \
 238         "       .align 16\n"                                    \
 239         "901:   call   903f;\n"                                 \
 240         "902:   pause;\n"                                       \
 241         "       lfence;\n"                                      \
 242         "       jmp    902b;\n"                                 \
 243         "       .align 16\n"                                    \
 244         "903:   lea    4(%%esp), %%esp;\n"                      \
 245         "       pushl  %[thunk_target];\n"                      \
 246         "       ret;\n"                                         \
 247         "       .align 16\n"                                    \
 248         "904:   call   901b;\n",                                \
 249         X86_FEATURE_RETPOLINE,                                  \
 250         "lfence;\n"                                             \
 251         ANNOTATE_RETPOLINE_SAFE                                 \
 252         "call *%[thunk_target]\n",                              \
 253         X86_FEATURE_RETPOLINE_LFENCE)
 254
 255 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 256 #endif
 257 #else /* No retpoline for C / inline asm */
 258 # define CALL_NOSPEC "call *%[thunk_target]\n"
 259 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 260 #endif
 261
 262 /* The Spectre V2 mitigation variants */
 263 enum spectre_v2_mitigation {
 264         SPECTRE_V2_NONE,
 265         SPECTRE_V2_RETPOLINE,
 266         SPECTRE_V2_LFENCE,
 267         SPECTRE_V2_EIBRS,
 268         SPECTRE_V2_EIBRS_RETPOLINE,
 269         SPECTRE_V2_EIBRS_LFENCE,
 270         SPECTRE_V2_IBRS,
 271 };
 272
 273 /* The indirect branch speculation control variants */
 274 enum spectre_v2_user_mitigation {
 275         SPECTRE_V2_USER_NONE,
 276         SPECTRE_V2_USER_STRICT,
 277         SPECTRE_V2_USER_STRICT_PREFERRED,
 278         SPECTRE_V2_USER_PRCTL,
 279         SPECTRE_V2_USER_SECCOMP,
 280 };
 281
 282 /* The Speculative Store Bypass disable variants */
 283 enum ssb_mitigation {
 284         SPEC_STORE_BYPASS_NONE,
 285         SPEC_STORE_BYPASS_DISABLE,
 286         SPEC_STORE_BYPASS_PRCTL,
 287         SPEC_STORE_BYPASS_SECCOMP,
 288 };
 289
 290 extern char __indirect_thunk_start[];
 291 extern char __indirect_thunk_end[];
 292
 293 static __always_inline
 294 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 295 {
 296         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 297                 : : "c" (msr),
 298                     "a" ((u32)val),
 299                     "d" ((u32)(val >> 32)),
 300                     [feature] "i" (feature)
 301                 : "memory");
 302 }
 303
 304 static inline void indirect_branch_prediction_barrier(void)
 305 {
 306         u64 val = PRED_CMD_IBPB;
 307
 308         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 309 }
 310
 311 /* The Intel SPEC CTRL MSR base value cache */
 312 extern u64 x86_spec_ctrl_base;
 313 DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
 314 extern void write_spec_ctrl_current(u64 val, bool force);
 315 extern u64 spec_ctrl_current(void);
 316
 317 /*
 318  * With retpoline, we must use IBRS to restrict branch prediction
 319  * before calling into firmware.
 320  *
 321  * (Implemented as CPP macros due to header hell.)
 322  */
 323 #define firmware_restrict_branch_speculation_start()                    \
 324 do {                                                                    \
 325         preempt_disable();                                              \
 326         alternative_msr_write(MSR_IA32_SPEC_CTRL,                       \
 327                               spec_ctrl_current() | SPEC_CTRL_IBRS,     \
 328                               X86_FEATURE_USE_IBRS_FW);                 \
 329         alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB,         \
 330                               X86_FEATURE_USE_IBPB_FW);                 \
 331 } while (0)
 332
 333 #define firmware_restrict_branch_speculation_end()                      \
 334 do {                                                                    \
 335         alternative_msr_write(MSR_IA32_SPEC_CTRL,                       \
 336                               spec_ctrl_current(),                      \
 337                               X86_FEATURE_USE_IBRS_FW);                 \
 338         preempt_enable();                                               \
 339 } while (0)
 340
 341 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 342 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 343 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 344
 345 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 346 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 347
 348 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 349
 350 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 351
 352 #include <asm/segment.h>
 353
 354 /**
 355  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 356  *
 357  * This uses the otherwise unused and obsolete VERW instruction in
 358  * combination with microcode which triggers a CPU buffer flush when the
 359  * instruction is executed.
 360  */
 361 static __always_inline void mds_clear_cpu_buffers(void)
 362 {
 363         static const u16 ds = __KERNEL_DS;
 364
 365         /*
 366          * Has to be the memory-operand variant because only that
 367          * guarantees the CPU buffer flush functionality according to
 368          * documentation. The register-operand variant does not.
 369          * Works with any segment selector, but a valid writable
 370          * data segment is the fastest variant.
 371          *
 372          * "cc" clobber is required because VERW modifies ZF.
 373          */
 374         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 375 }
 376
 377 /**
 378  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 379  *
 380  * Clear CPU buffers if the corresponding static key is enabled
 381  */
 382 static __always_inline void mds_user_clear_cpu_buffers(void)
 383 {
 384         if (static_branch_likely(&mds_user_clear))
 385                 mds_clear_cpu_buffers();
 386 }
 387
 388 /**
 389  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 390  *
 391  * Clear CPU buffers if the corresponding static key is enabled
 392  */
 393 static inline void mds_idle_clear_cpu_buffers(void)
 394 {
 395         if (static_branch_likely(&mds_idle_clear))
 396                 mds_clear_cpu_buffers();
 397 }
 398
 399 #endif /* __ASSEMBLY__ */
 400
 401 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */