arch/x86/include/asm/nospec-branch.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 #ifndef _ASM_X86_NOSPEC_BRANCH_H_
   4 #define _ASM_X86_NOSPEC_BRANCH_H_
   5
   6 #include <linux/static_key.h>
   7 #include <linux/objtool.h>
   8 #include <linux/linkage.h>
   9
  10 #include <asm/alternative.h>
  11 #include <asm/cpufeatures.h>
  12 #include <asm/msr-index.h>
  13 #include <asm/unwind_hints.h>
  14
  15 #define RETPOLINE_THUNK_SIZE    32
  16
  17 /*
  18  * Fill the CPU return stack buffer.
  19  *
  20  * Each entry in the RSB, if used for a speculative 'ret', contains an
  21  * infinite 'pause; lfence; jmp' loop to capture speculative execution.
  22  *
  23  * This is required in various cases for retpoline and IBRS-based
  24  * mitigations for the Spectre variant 2 vulnerability. Sometimes to
  25  * eliminate potentially bogus entries from the RSB, and sometimes
  26  * purely to ensure that it doesn't get empty, which on some CPUs would
  27  * allow predictions from other (unwanted!) sources to be used.
  28  *
  29  * We define a CPP macro such that it can be used from both .S files and
  30  * inline assembly. It's possible to do a .macro and then include that
  31  * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
  32  */
  33
  34 #define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
  35
  36 /*
  37  * Google experimented with loop-unrolling and this turned out to be
  38  * the optimal version - two calls, each with their own speculation
  39  * trap should their return address end up getting used, in a loop.
  40  */
  41 #define __FILL_RETURN_BUFFER(reg, nr, sp)       \
  42         mov     $(nr/2), reg;                   \
  43 771:                                            \
  44         ANNOTATE_INTRA_FUNCTION_CALL;           \
  45         call    772f;                           \
  46 773:    /* speculation trap */                  \
  47         UNWIND_HINT_EMPTY;                      \
  48         pause;                                  \
  49         lfence;                                 \
  50         jmp     773b;                           \
  51 772:                                            \
  52         ANNOTATE_INTRA_FUNCTION_CALL;           \
  53         call    774f;                           \
  54 775:    /* speculation trap */                  \
  55         UNWIND_HINT_EMPTY;                      \
  56         pause;                                  \
  57         lfence;                                 \
  58         jmp     775b;                           \
  59 774:                                            \
  60         add     $(BITS_PER_LONG/8) * 2, sp;     \
  61         dec     reg;                            \
  62         jnz     771b;
  63
  64 #ifdef __ASSEMBLY__
  65
  66 /*
  67  * This should be used immediately before an indirect jump/call. It tells
  68  * objtool the subsequent indirect jump/call is vouched safe for retpoline
  69  * builds.
  70  */
  71 .macro ANNOTATE_RETPOLINE_SAFE
  72         .Lannotate_\@:
  73         .pushsection .discard.retpoline_safe
  74         _ASM_PTR .Lannotate_\@
  75         .popsection
  76 .endm
  77
  78 /*
  79  * JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
  80  * indirect jmp/call which may be susceptible to the Spectre variant 2
  81  * attack.
  82  */
  83 .macro JMP_NOSPEC reg:req
  84 #ifdef CONFIG_RETPOLINE
  85         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), \
  86                       __stringify(jmp __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
  87                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), X86_FEATURE_RETPOLINE_LFENCE
  88 #else
  89         jmp     *%\reg
  90 #endif
  91 .endm
  92
  93 .macro CALL_NOSPEC reg:req
  94 #ifdef CONFIG_RETPOLINE
  95         ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *%\reg), \
  96                       __stringify(call __x86_indirect_thunk_\reg), X86_FEATURE_RETPOLINE, \
  97                       __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *%\reg), X86_FEATURE_RETPOLINE_LFENCE
  98 #else
  99         call    *%\reg
 100 #endif
 101 .endm
 102
 103  /*
 104   * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
 105   * monstrosity above, manually.
 106   */
 107 .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 108 #ifdef CONFIG_RETPOLINE
 109         ALTERNATIVE "jmp .Lskip_rsb_\@", "", \ftr
 110         __FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP)
 111 .Lskip_rsb_\@:
 112 #endif
 113 .endm
 114
 115 /*
 116  * Mitigate RETBleed for AMD/Hygon Zen uarch. Requires KERNEL CR3 because the
 117  * return thunk isn't mapped into the userspace tables (then again, AMD
 118  * typically has NO_MELTDOWN).
 119  *
 120  * Doesn't clobber any registers but does require a stable stack.
 121  *
 122  * As such, this must be placed after every *SWITCH_TO_KERNEL_CR3 at a point
 123  * where we have a stack but before any RET instruction.
 124  */
 125 .macro UNTRAIN_RET
 126 #ifdef CONFIG_RETPOLINE
 127         ALTERNATIVE "", "call zen_untrain_ret", X86_FEATURE_UNRET
 128 #endif
 129 .endm
 130
 131 #else /* __ASSEMBLY__ */
 132
 133 #define ANNOTATE_RETPOLINE_SAFE                                 \
 134         "999:\n\t"                                              \
 135         ".pushsection .discard.retpoline_safe\n\t"              \
 136         _ASM_PTR " 999b\n\t"                                    \
 137         ".popsection\n\t"
 138
 139 typedef u8 retpoline_thunk_t[RETPOLINE_THUNK_SIZE];
 140 extern retpoline_thunk_t __x86_indirect_thunk_array[];
 141
 142 extern void __x86_return_thunk(void);
 143 extern void zen_untrain_ret(void);
 144
 145 #ifdef CONFIG_RETPOLINE
 146
 147 #define GEN(reg) \
 148         extern retpoline_thunk_t __x86_indirect_thunk_ ## reg;
 149 #include <asm/GEN-for-each-reg.h>
 150 #undef GEN
 151
 152 #ifdef CONFIG_X86_64
 153
 154 /*
 155  * Inline asm uses the %V modifier which is only in newer GCC
 156  * which is ensured when CONFIG_RETPOLINE is defined.
 157  */
 158 # define CALL_NOSPEC                                            \
 159         ALTERNATIVE_2(                                          \
 160         ANNOTATE_RETPOLINE_SAFE                                 \
 161         "call *%[thunk_target]\n",                              \
 162         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
 163         X86_FEATURE_RETPOLINE,                                  \
 164         "lfence;\n"                                             \
 165         ANNOTATE_RETPOLINE_SAFE                                 \
 166         "call *%[thunk_target]\n",                              \
 167         X86_FEATURE_RETPOLINE_LFENCE)
 168
 169 # define THUNK_TARGET(addr) [thunk_target] "r" (addr)
 170
 171 #else /* CONFIG_X86_32 */
 172 /*
 173  * For i386 we use the original ret-equivalent retpoline, because
 174  * otherwise we'll run out of registers. We don't care about CET
 175  * here, anyway.
 176  */
 177 # define CALL_NOSPEC                                            \
 178         ALTERNATIVE_2(                                          \
 179         ANNOTATE_RETPOLINE_SAFE                                 \
 180         "call *%[thunk_target]\n",                              \
 181         "       jmp    904f;\n"                                 \
 182         "       .align 16\n"                                    \
 183         "901:   call   903f;\n"                                 \
 184         "902:   pause;\n"                                       \
 185         "       lfence;\n"                                      \
 186         "       jmp    902b;\n"                                 \
 187         "       .align 16\n"                                    \
 188         "903:   lea    4(%%esp), %%esp;\n"                      \
 189         "       pushl  %[thunk_target];\n"                      \
 190         "       ret;\n"                                         \
 191         "       .align 16\n"                                    \
 192         "904:   call   901b;\n",                                \
 193         X86_FEATURE_RETPOLINE,                                  \
 194         "lfence;\n"                                             \
 195         ANNOTATE_RETPOLINE_SAFE                                 \
 196         "call *%[thunk_target]\n",                              \
 197         X86_FEATURE_RETPOLINE_LFENCE)
 198
 199 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 200 #endif
 201 #else /* No retpoline for C / inline asm */
 202 # define CALL_NOSPEC "call *%[thunk_target]\n"
 203 # define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
 204 #endif
 205
 206 /* The Spectre V2 mitigation variants */
 207 enum spectre_v2_mitigation {
 208         SPECTRE_V2_NONE,
 209         SPECTRE_V2_RETPOLINE,
 210         SPECTRE_V2_LFENCE,
 211         SPECTRE_V2_EIBRS,
 212         SPECTRE_V2_EIBRS_RETPOLINE,
 213         SPECTRE_V2_EIBRS_LFENCE,
 214         SPECTRE_V2_IBRS,
 215 };
 216
 217 /* The indirect branch speculation control variants */
 218 enum spectre_v2_user_mitigation {
 219         SPECTRE_V2_USER_NONE,
 220         SPECTRE_V2_USER_STRICT,
 221         SPECTRE_V2_USER_STRICT_PREFERRED,
 222         SPECTRE_V2_USER_PRCTL,
 223         SPECTRE_V2_USER_SECCOMP,
 224 };
 225
 226 /* The Speculative Store Bypass disable variants */
 227 enum ssb_mitigation {
 228         SPEC_STORE_BYPASS_NONE,
 229         SPEC_STORE_BYPASS_DISABLE,
 230         SPEC_STORE_BYPASS_PRCTL,
 231         SPEC_STORE_BYPASS_SECCOMP,
 232 };
 233
 234 extern char __indirect_thunk_start[];
 235 extern char __indirect_thunk_end[];
 236
 237 static __always_inline
 238 void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
 239 {
 240         asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
 241                 : : "c" (msr),
 242                     "a" ((u32)val),
 243                     "d" ((u32)(val >> 32)),
 244                     [feature] "i" (feature)
 245                 : "memory");
 246 }
 247
 248 static inline void indirect_branch_prediction_barrier(void)
 249 {
 250         u64 val = PRED_CMD_IBPB;
 251
 252         alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
 253 }
 254
 255 /* The Intel SPEC CTRL MSR base value cache */
 256 extern u64 x86_spec_ctrl_base;
 257 extern void write_spec_ctrl_current(u64 val, bool force);
 258 extern u64 spec_ctrl_current(void);
 259
 260 /*
 261  * With retpoline, we must use IBRS to restrict branch prediction
 262  * before calling into firmware.
 263  *
 264  * (Implemented as CPP macros due to header hell.)
 265  */
 266 #define firmware_restrict_branch_speculation_start()                    \
 267 do {                                                                    \
 268         u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS;                  \
 269                                                                         \
 270         preempt_disable();                                              \
 271         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 272                               X86_FEATURE_USE_IBRS_FW);                 \
 273 } while (0)
 274
 275 #define firmware_restrict_branch_speculation_end()                      \
 276 do {                                                                    \
 277         u64 val = x86_spec_ctrl_base;                                   \
 278                                                                         \
 279         alternative_msr_write(MSR_IA32_SPEC_CTRL, val,                  \
 280                               X86_FEATURE_USE_IBRS_FW);                 \
 281         preempt_enable();                                               \
 282 } while (0)
 283
 284 DECLARE_STATIC_KEY_FALSE(switch_to_cond_stibp);
 285 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 286 DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 287
 288 DECLARE_STATIC_KEY_FALSE(mds_user_clear);
 289 DECLARE_STATIC_KEY_FALSE(mds_idle_clear);
 290
 291 DECLARE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush);
 292
 293 DECLARE_STATIC_KEY_FALSE(mmio_stale_data_clear);
 294
 295 #include <asm/segment.h>
 296
 297 /**
 298  * mds_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 299  *
 300  * This uses the otherwise unused and obsolete VERW instruction in
 301  * combination with microcode which triggers a CPU buffer flush when the
 302  * instruction is executed.
 303  */
 304 static __always_inline void mds_clear_cpu_buffers(void)
 305 {
 306         static const u16 ds = __KERNEL_DS;
 307
 308         /*
 309          * Has to be the memory-operand variant because only that
 310          * guarantees the CPU buffer flush functionality according to
 311          * documentation. The register-operand variant does not.
 312          * Works with any segment selector, but a valid writable
 313          * data segment is the fastest variant.
 314          *
 315          * "cc" clobber is required because VERW modifies ZF.
 316          */
 317         asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 318 }
 319
 320 /**
 321  * mds_user_clear_cpu_buffers - Mitigation for MDS and TAA vulnerability
 322  *
 323  * Clear CPU buffers if the corresponding static key is enabled
 324  */
 325 static __always_inline void mds_user_clear_cpu_buffers(void)
 326 {
 327         if (static_branch_likely(&mds_user_clear))
 328                 mds_clear_cpu_buffers();
 329 }
 330
 331 /**
 332  * mds_idle_clear_cpu_buffers - Mitigation for MDS vulnerability
 333  *
 334  * Clear CPU buffers if the corresponding static key is enabled
 335  */
 336 static inline void mds_idle_clear_cpu_buffers(void)
 337 {
 338         if (static_branch_likely(&mds_idle_clear))
 339                 mds_clear_cpu_buffers();
 340 }
 341
 342 #endif /* __ASSEMBLY__ */
 343
 344 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */