10 #include <asm/cpumask.h>
11 #include <uapi/asm/msr.h>
30 struct msr_regs_info {
42 struct saved_msr *array;
46 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
47 * constraint has different meanings. For i386, "A" means exactly
48 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
49 * it means rax *or* rdx.
52 /* Using 64-bit values saves one instruction clearing the high half of low */
53 #define DECLARE_ARGS(val, low, high) unsigned long low, high
54 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32)
55 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
57 #define DECLARE_ARGS(val, low, high) unsigned long long val
58 #define EAX_EDX_VAL(val, low, high) (val)
59 #define EAX_EDX_RET(val, low, high) "=A" (val)
62 #ifdef CONFIG_TRACEPOINTS
64 * Be very careful with includes. This header is prone to include loops.
66 #include <asm/atomic.h>
67 #include <linux/tracepoint-defs.h>
69 extern struct tracepoint __tracepoint_read_msr;
70 extern struct tracepoint __tracepoint_write_msr;
71 extern struct tracepoint __tracepoint_rdpmc;
72 #define msr_tracepoint_active(t) static_key_false(&(t).key)
73 extern void do_trace_write_msr(unsigned msr, u64 val, int failed);
74 extern void do_trace_read_msr(unsigned msr, u64 val, int failed);
75 extern void do_trace_rdpmc(unsigned msr, u64 val, int failed);
77 #define msr_tracepoint_active(t) false
78 static inline void do_trace_write_msr(unsigned msr, u64 val, int failed) {}
79 static inline void do_trace_read_msr(unsigned msr, u64 val, int failed) {}
80 static inline void do_trace_rdpmc(unsigned msr, u64 val, int failed) {}
83 static inline unsigned long long native_read_msr(unsigned int msr)
85 DECLARE_ARGS(val, low, high);
87 asm volatile("1: rdmsr\n"
89 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe)
90 : EAX_EDX_RET(val, low, high) : "c" (msr));
91 if (msr_tracepoint_active(__tracepoint_read_msr))
92 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), 0);
93 return EAX_EDX_VAL(val, low, high);
96 static inline unsigned long long native_read_msr_safe(unsigned int msr,
99 DECLARE_ARGS(val, low, high);
101 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
103 ".section .fixup,\"ax\"\n\t"
104 "3: mov %[fault],%[err]\n\t"
105 "xorl %%eax, %%eax\n\t"
106 "xorl %%edx, %%edx\n\t"
110 : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
111 : "c" (msr), [fault] "i" (-EIO));
112 if (msr_tracepoint_active(__tracepoint_read_msr))
113 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
114 return EAX_EDX_VAL(val, low, high);
117 /* Can be uninlined because referenced by paravirt */
118 static notrace inline void __native_write_msr_notrace(unsigned int msr,
119 unsigned low, unsigned high)
121 asm volatile("1: wrmsr\n"
123 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
124 : : "c" (msr), "a"(low), "d" (high) : "memory");
127 /* Can be uninlined because referenced by paravirt */
128 static notrace inline void native_write_msr(unsigned int msr,
129 unsigned low, unsigned high)
131 __native_write_msr_notrace(msr, low, high);
132 if (msr_tracepoint_active(__tracepoint_write_msr))
133 do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
136 static inline void wrmsr_notrace(unsigned msr, unsigned low, unsigned high)
138 __native_write_msr_notrace(msr, low, high);
141 /* Can be uninlined because referenced by paravirt */
142 notrace static inline int native_write_msr_safe(unsigned int msr,
143 unsigned low, unsigned high)
146 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
148 ".section .fixup,\"ax\"\n\t"
149 "3: mov %[fault],%[err] ; jmp 1b\n\t"
153 : "c" (msr), "0" (low), "d" (high),
156 if (msr_tracepoint_active(__tracepoint_write_msr))
157 do_trace_write_msr(msr, ((u64)high << 32 | low), err);
161 extern int rdmsr_safe_regs(u32 regs[8]);
162 extern int wrmsr_safe_regs(u32 regs[8]);
165 * rdtsc() - returns the current TSC without ordering constraints
167 * rdtsc() returns the result of RDTSC as a 64-bit integer. The
168 * only ordering constraint it supplies is the ordering implied by
169 * "asm volatile": it will put the RDTSC in the place you expect. The
170 * CPU can and will speculatively execute that RDTSC, though, so the
171 * results can be non-monotonic if compared on different CPUs.
173 static __always_inline unsigned long long rdtsc(void)
175 DECLARE_ARGS(val, low, high);
177 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
179 return EAX_EDX_VAL(val, low, high);
183 * rdtsc_ordered() - read the current TSC in program order
185 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
186 * It is ordered like a load to a global in-memory counter. It should
187 * be impossible to observe non-monotonic rdtsc_unordered() behavior
188 * across multiple CPUs as long as the TSC is synced.
190 static __always_inline unsigned long long rdtsc_ordered(void)
193 * The RDTSC instruction is not ordered relative to memory
194 * access. The Intel SDM and the AMD APM are both vague on this
195 * point, but empirically an RDTSC instruction can be
196 * speculatively executed before prior loads. An RDTSC
197 * immediately after an appropriate barrier appears to be
198 * ordered as a normal load, that is, it provides the same
199 * ordering guarantees as reading from a global memory location
200 * that some other imaginary CPU is updating continuously with a
203 alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
204 "lfence", X86_FEATURE_LFENCE_RDTSC);
208 /* Deprecated, keep it for a cycle for easier merging: */
209 #define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0)
211 static inline unsigned long long native_read_pmc(int counter)
213 DECLARE_ARGS(val, low, high);
215 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
216 if (msr_tracepoint_active(__tracepoint_rdpmc))
217 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
218 return EAX_EDX_VAL(val, low, high);
221 #ifdef CONFIG_PARAVIRT
222 #include <asm/paravirt.h>
224 #include <linux/errno.h>
226 * Access to machine-specific registers (available on 586 and better only)
227 * Note: the rd* operations modify the parameters directly (without using
228 * pointer indirection), this allows gcc to optimize better
231 #define rdmsr(msr, low, high) \
233 u64 __val = native_read_msr((msr)); \
234 (void)((low) = (u32)__val); \
235 (void)((high) = (u32)(__val >> 32)); \
238 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
240 native_write_msr(msr, low, high);
243 #define rdmsrl(msr, val) \
244 ((val) = native_read_msr((msr)))
246 static inline void wrmsrl(unsigned msr, u64 val)
248 native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
251 /* wrmsr with exception handling */
252 static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
254 return native_write_msr_safe(msr, low, high);
257 /* rdmsr with exception handling */
258 #define rdmsr_safe(msr, low, high) \
261 u64 __val = native_read_msr_safe((msr), &__err); \
262 (*low) = (u32)__val; \
263 (*high) = (u32)(__val >> 32); \
267 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
271 *p = native_read_msr_safe(msr, &err);
275 #define rdpmc(counter, low, high) \
277 u64 _l = native_read_pmc((counter)); \
279 (high) = (u32)(_l >> 32); \
282 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
284 #endif /* !CONFIG_PARAVIRT */
287 * 64-bit version of wrmsr_safe():
289 static inline int wrmsrl_safe(u32 msr, u64 val)
291 return wrmsr_safe(msr, (u32)val, (u32)(val >> 32));
294 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
296 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
298 struct msr *msrs_alloc(void);
299 void msrs_free(struct msr *msrs);
300 int msr_set_bit(u32 msr, u8 bit);
301 int msr_clear_bit(u32 msr, u8 bit);
304 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
305 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
306 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
307 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
308 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
309 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
310 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
311 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
312 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
313 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
314 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
315 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
316 #else /* CONFIG_SMP */
317 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
319 rdmsr(msr_no, *l, *h);
322 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
327 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
332 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
337 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
340 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
342 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
345 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
347 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
350 return rdmsr_safe(msr_no, l, h);
352 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
354 return wrmsr_safe(msr_no, l, h);
356 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
358 return rdmsrl_safe(msr_no, q);
360 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
362 return wrmsrl_safe(msr_no, q);
364 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
366 return rdmsr_safe_regs(regs);
368 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
370 return wrmsr_safe_regs(regs);
372 #endif /* CONFIG_SMP */
373 #endif /* __ASSEMBLY__ */
374 #endif /* _ASM_X86_MSR_H */