1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <asm/errno.h>
11 #include <asm/cpumask.h>
12 #include <uapi/asm/msr.h>
31 struct msr_regs_info {
43 struct saved_msr *array;
47 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
48 * constraint has different meanings. For i386, "A" means exactly
49 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
50 * it means rax *or* rdx.
53 /* Using 64-bit values saves one instruction clearing the high half of low */
54 #define DECLARE_ARGS(val, low, high) unsigned long low, high
55 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32)
56 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
58 #define DECLARE_ARGS(val, low, high) unsigned long long val
59 #define EAX_EDX_VAL(val, low, high) (val)
60 #define EAX_EDX_RET(val, low, high) "=A" (val)
63 #ifdef CONFIG_TRACEPOINTS
65 * Be very careful with includes. This header is prone to include loops.
67 #include <asm/atomic.h>
68 #include <linux/tracepoint-defs.h>
70 extern struct tracepoint __tracepoint_read_msr;
71 extern struct tracepoint __tracepoint_write_msr;
72 extern struct tracepoint __tracepoint_rdpmc;
73 #define msr_tracepoint_active(t) static_key_false(&(t).key)
74 extern void do_trace_write_msr(unsigned int msr, u64 val, int failed);
75 extern void do_trace_read_msr(unsigned int msr, u64 val, int failed);
76 extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed);
78 #define msr_tracepoint_active(t) false
79 static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {}
80 static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {}
81 static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {}
85 * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR
86 * accessors and should not have any tracing or other functionality piggybacking
87 * on them - those are *purely* for accessing MSRs and nothing more. So don't even
88 * think of extending them - you will be slapped with a stinking trout or a frozen
89 * shark will reach you, wherever you are! You've been warned.
91 static inline unsigned long long notrace __rdmsr(unsigned int msr)
93 DECLARE_ARGS(val, low, high);
95 asm volatile("1: rdmsr\n"
97 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe)
98 : EAX_EDX_RET(val, low, high) : "c" (msr));
100 return EAX_EDX_VAL(val, low, high);
103 static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high)
105 asm volatile("1: wrmsr\n"
107 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
108 : : "c" (msr), "a"(low), "d" (high) : "memory");
111 static inline unsigned long long native_read_msr(unsigned int msr)
113 unsigned long long val;
117 if (msr_tracepoint_active(__tracepoint_read_msr))
118 do_trace_read_msr(msr, val, 0);
123 static inline unsigned long long native_read_msr_safe(unsigned int msr,
126 DECLARE_ARGS(val, low, high);
128 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
130 ".section .fixup,\"ax\"\n\t"
131 "3: mov %[fault],%[err]\n\t"
132 "xorl %%eax, %%eax\n\t"
133 "xorl %%edx, %%edx\n\t"
137 : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
138 : "c" (msr), [fault] "i" (-EIO));
139 if (msr_tracepoint_active(__tracepoint_read_msr))
140 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
141 return EAX_EDX_VAL(val, low, high);
144 /* Can be uninlined because referenced by paravirt */
145 static inline void notrace
146 native_write_msr(unsigned int msr, u32 low, u32 high)
148 __wrmsr(msr, low, high);
150 if (msr_tracepoint_active(__tracepoint_write_msr))
151 do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
154 /* Can be uninlined because referenced by paravirt */
155 static inline int notrace
156 native_write_msr_safe(unsigned int msr, u32 low, u32 high)
160 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
162 ".section .fixup,\"ax\"\n\t"
163 "3: mov %[fault],%[err] ; jmp 1b\n\t"
167 : "c" (msr), "0" (low), "d" (high),
170 if (msr_tracepoint_active(__tracepoint_write_msr))
171 do_trace_write_msr(msr, ((u64)high << 32 | low), err);
175 extern int rdmsr_safe_regs(u32 regs[8]);
176 extern int wrmsr_safe_regs(u32 regs[8]);
179 * rdtsc() - returns the current TSC without ordering constraints
181 * rdtsc() returns the result of RDTSC as a 64-bit integer. The
182 * only ordering constraint it supplies is the ordering implied by
183 * "asm volatile": it will put the RDTSC in the place you expect. The
184 * CPU can and will speculatively execute that RDTSC, though, so the
185 * results can be non-monotonic if compared on different CPUs.
187 static __always_inline unsigned long long rdtsc(void)
189 DECLARE_ARGS(val, low, high);
191 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
193 return EAX_EDX_VAL(val, low, high);
197 * rdtsc_ordered() - read the current TSC in program order
199 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
200 * It is ordered like a load to a global in-memory counter. It should
201 * be impossible to observe non-monotonic rdtsc_unordered() behavior
202 * across multiple CPUs as long as the TSC is synced.
204 static __always_inline unsigned long long rdtsc_ordered(void)
207 * The RDTSC instruction is not ordered relative to memory
208 * access. The Intel SDM and the AMD APM are both vague on this
209 * point, but empirically an RDTSC instruction can be
210 * speculatively executed before prior loads. An RDTSC
211 * immediately after an appropriate barrier appears to be
212 * ordered as a normal load, that is, it provides the same
213 * ordering guarantees as reading from a global memory location
214 * that some other imaginary CPU is updating continuously with a
217 alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
218 "lfence", X86_FEATURE_LFENCE_RDTSC);
222 /* Deprecated, keep it for a cycle for easier merging: */
223 #define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0)
225 static inline unsigned long long native_read_pmc(int counter)
227 DECLARE_ARGS(val, low, high);
229 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
230 if (msr_tracepoint_active(__tracepoint_rdpmc))
231 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
232 return EAX_EDX_VAL(val, low, high);
235 #ifdef CONFIG_PARAVIRT
236 #include <asm/paravirt.h>
238 #include <linux/errno.h>
240 * Access to machine-specific registers (available on 586 and better only)
241 * Note: the rd* operations modify the parameters directly (without using
242 * pointer indirection), this allows gcc to optimize better
245 #define rdmsr(msr, low, high) \
247 u64 __val = native_read_msr((msr)); \
248 (void)((low) = (u32)__val); \
249 (void)((high) = (u32)(__val >> 32)); \
252 static inline void wrmsr(unsigned int msr, u32 low, u32 high)
254 native_write_msr(msr, low, high);
257 #define rdmsrl(msr, val) \
258 ((val) = native_read_msr((msr)))
260 static inline void wrmsrl(unsigned int msr, u64 val)
262 native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
265 /* wrmsr with exception handling */
266 static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high)
268 return native_write_msr_safe(msr, low, high);
271 /* rdmsr with exception handling */
272 #define rdmsr_safe(msr, low, high) \
275 u64 __val = native_read_msr_safe((msr), &__err); \
276 (*low) = (u32)__val; \
277 (*high) = (u32)(__val >> 32); \
281 static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p)
285 *p = native_read_msr_safe(msr, &err);
289 #define rdpmc(counter, low, high) \
291 u64 _l = native_read_pmc((counter)); \
293 (high) = (u32)(_l >> 32); \
296 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
298 #endif /* !CONFIG_PARAVIRT */
301 * 64-bit version of wrmsr_safe():
303 static inline int wrmsrl_safe(u32 msr, u64 val)
305 return wrmsr_safe(msr, (u32)val, (u32)(val >> 32));
308 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
310 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
312 struct msr *msrs_alloc(void);
313 void msrs_free(struct msr *msrs);
314 int msr_set_bit(u32 msr, u8 bit);
315 int msr_clear_bit(u32 msr, u8 bit);
318 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
319 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
320 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
321 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
322 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
323 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
324 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
325 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
326 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
327 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
328 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
329 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
330 #else /* CONFIG_SMP */
331 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
333 rdmsr(msr_no, *l, *h);
336 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
341 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
346 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
351 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
354 rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
356 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
359 wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
361 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
364 return rdmsr_safe(msr_no, l, h);
366 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
368 return wrmsr_safe(msr_no, l, h);
370 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
372 return rdmsrl_safe(msr_no, q);
374 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
376 return wrmsrl_safe(msr_no, q);
378 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
380 return rdmsr_safe_regs(regs);
382 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
384 return wrmsr_safe_regs(regs);
386 #endif /* CONFIG_SMP */
387 #endif /* __ASSEMBLY__ */
388 #endif /* _ASM_X86_MSR_H */