1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MPSPEC_DEF_H
3 #define _ASM_X86_MPSPEC_DEF_H
6 * Structure definitions for SMP machines following the
7 * Intel Multiprocessing Specification 1.1 and 1.4.
11 * This tag identifies where the SMP configuration
15 #define SMP_MAGIC_IDENT (('_'<<24) | ('P'<<16) | ('M'<<8) | '_')
18 # define MAX_MPC_ENTRY 1024
21 /* Intel MP Floating Pointer Structure */
23 char signature[4]; /* "_MP_" */
24 unsigned int physptr; /* Configuration table address */
25 unsigned char length; /* Our length (paragraphs) */
26 unsigned char specification; /* Specification version */
27 unsigned char checksum; /* Checksum (makes sum 0) */
28 unsigned char feature1; /* Standard or configuration ? */
29 unsigned char feature2; /* Bit7 set for IMCR|PIC */
30 unsigned char feature3; /* Unused (0) */
31 unsigned char feature4; /* Unused (0) */
32 unsigned char feature5; /* Unused (0) */
35 #define MPC_SIGNATURE "PCMP"
39 unsigned short length; /* Size of table */
44 unsigned int oemptr; /* 0 if not present */
45 unsigned short oemsize; /* 0 if not present */
46 unsigned short oemcount;
47 unsigned int lapic; /* APIC address */
48 unsigned int reserved;
51 /* Followed by entries */
53 #define MP_PROCESSOR 0
58 /* Used by IBM NUMA-Q to describe node locality */
59 #define MP_TRANSLATION 192
61 #define CPU_ENABLED 1 /* Processor is available */
62 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
64 #define CPU_STEPPING_MASK 0x000F
65 #define CPU_MODEL_MASK 0x00F0
66 #define CPU_FAMILY_MASK 0x0F00
70 unsigned char apicid; /* Local APIC number */
71 unsigned char apicver; /* Its versions */
72 unsigned char cpuflag;
73 unsigned int cpufeature;
74 unsigned int featureflag; /* CPUID feature value */
75 unsigned int reserved[2];
81 unsigned char bustype[6];
84 /* List of Bus Type string values, Intel MP Spec. */
85 #define BUSTYPE_EISA "EISA"
86 #define BUSTYPE_ISA "ISA"
87 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
88 #define BUSTYPE_MCA "MCA" /* Obsolete */
89 #define BUSTYPE_VL "VL" /* Local bus */
90 #define BUSTYPE_PCI "PCI"
91 #define BUSTYPE_PCMCIA "PCMCIA"
92 #define BUSTYPE_CBUS "CBUS"
93 #define BUSTYPE_CBUSII "CBUSII"
94 #define BUSTYPE_FUTURE "FUTURE"
95 #define BUSTYPE_MBI "MBI"
96 #define BUSTYPE_MBII "MBII"
97 #define BUSTYPE_MPI "MPI"
98 #define BUSTYPE_MPSA "MPSA"
99 #define BUSTYPE_NUBUS "NUBUS"
100 #define BUSTYPE_TC "TC"
101 #define BUSTYPE_VME "VME"
102 #define BUSTYPE_XPRESS "XPRESS"
104 #define MPC_APIC_USABLE 0x01
108 unsigned char apicid;
109 unsigned char apicver;
111 unsigned int apicaddr;
116 unsigned char irqtype;
117 unsigned short irqflag;
118 unsigned char srcbus;
119 unsigned char srcbusirq;
120 unsigned char dstapic;
121 unsigned char dstirq;
124 enum mp_irq_source_types {
131 #define MP_IRQDIR_DEFAULT 0
132 #define MP_IRQDIR_HIGH 1
133 #define MP_IRQDIR_LOW 3
135 #define MP_APIC_ALL 0xFF
139 unsigned char irqtype;
140 unsigned short irqflag;
141 unsigned char srcbusid;
142 unsigned char srcbusirq;
143 unsigned char destapic;
144 unsigned char destapiclint;
147 #define MPC_OEM_SIGNATURE "_OEM"
149 struct mpc_oemtable {
151 unsigned short length; /* Size of table */
158 * Default configurations
160 * 1 2 CPU ISA 82489DX
161 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
162 * 3 2 CPU EISA 82489DX
163 * 4 2 CPU MCA 82489DX
174 #endif /* _ASM_X86_MPSPEC_DEF_H */