1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_MICROCODE_H
3 #define _ASM_X86_MICROCODE_H
11 struct ucode_cpu_info {
12 struct cpu_signature cpu_sig;
16 #ifdef CONFIG_MICROCODE
17 void load_ucode_bsp(void);
18 void load_ucode_ap(void);
19 void microcode_bsp_resume(void);
21 static inline void load_ucode_bsp(void) { }
22 static inline void load_ucode_ap(void) { }
23 static inline void microcode_bsp_resume(void) { }
26 extern unsigned long initrd_start_early;
28 #ifdef CONFIG_CPU_SUP_INTEL
29 /* Intel specific microcode defines. Public for IFS */
30 struct microcode_header_intel {
38 unsigned int datasize;
39 unsigned int totalsize;
40 unsigned int metasize;
41 unsigned int min_req_ver;
42 unsigned int reserved;
45 struct microcode_intel {
46 struct microcode_header_intel hdr;
50 #define DEFAULT_UCODE_DATASIZE (2000)
51 #define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
52 #define MC_HEADER_TYPE_MICROCODE 1
53 #define MC_HEADER_TYPE_IFS 2
55 static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr)
57 return hdr->datasize ? : DEFAULT_UCODE_DATASIZE;
60 static inline u32 intel_get_microcode_revision(void)
64 native_wrmsrl(MSR_IA32_UCODE_REV, 0);
66 /* As documented in the SDM: Do a CPUID 1 here */
69 /* get the current revision from MSR 0x8B */
70 native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
74 #endif /* !CONFIG_CPU_SUP_INTEL */
76 bool microcode_nmi_handler(void);
77 void microcode_offline_nmi_handler(void);
79 #ifdef CONFIG_MICROCODE_LATE_LOADING
80 DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable);
81 static __always_inline bool microcode_nmi_handler_enabled(void)
83 return static_branch_unlikely(µcode_nmi_handler_enable);
86 static __always_inline bool microcode_nmi_handler_enabled(void) { return false; }
89 #endif /* _ASM_X86_MICROCODE_H */