1 #ifndef _ASM_X86_INTEL_RDT_H
2 #define _ASM_X86_INTEL_RDT_H
4 #define IA32_L3_CBM_BASE 0xc90
5 #define IA32_L2_CBM_BASE 0xd10
8 * struct rdt_resource - attributes of an RDT resource
9 * @enabled: Is this feature enabled on this machine
10 * @capable: Is this feature available on this machine
11 * @name: Name to use in "schemata" file
12 * @num_closid: Number of CLOSIDs available
13 * @max_cbm: Largest Cache Bit Mask allowed
14 * @min_cbm_bits: Minimum number of consecutive bits to be set
16 * @domains: All domains for this resource
17 * @num_domains: Number of domains active
18 * @msr_base: Base MSR address for CBMs
19 * @tmp_cbms: Scratch space when updating schemata
20 * @cache_level: Which cache level defines scope of this domain
21 * @cbm_idx_multi: Multiplier of CBM index
22 * @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
23 * closid * cbm_idx_multi + cbm_idx_offset
33 struct list_head domains;
43 * struct rdt_domain - group of cpus sharing an RDT resource
44 * @list: all instances of this resource
45 * @id: unique id for this instance
46 * @cpu_mask: which cpus share this resource
47 * @cbm: array of cache bit masks (indexed by CLOSID)
50 struct list_head list;
52 struct cpumask cpu_mask;
57 * struct msr_param - set a range of MSRs from a domain
58 * @res: The resource to use
59 * @low: Beginning index from base MSR
63 struct rdt_resource *res;
68 extern struct mutex rdtgroup_mutex;
70 extern struct rdt_resource rdt_resources_all[];
78 /* Must be the last */
82 #define for_each_capable_rdt_resource(r) \
83 for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
87 #define for_each_enabled_rdt_resource(r) \
88 for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
92 /* CPUID.(EAX=10H, ECX=ResID=1).EAX */
93 union cpuid_0x10_1_eax {
95 unsigned int cbm_len:5;
100 /* CPUID.(EAX=10H, ECX=ResID=1).EDX */
101 union cpuid_0x10_1_edx {
103 unsigned int cos_max:16;
108 void rdt_cbm_update(void *arg);
109 #endif /* _ASM_X86_INTEL_RDT_H */