1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * intel-mid.h: Intel MID specific setup code
5 * (C) Copyright 2009 Intel Corporation
7 #ifndef _ASM_X86_INTEL_MID_H
8 #define _ASM_X86_INTEL_MID_H
10 #include <linux/sfi.h>
11 #include <linux/pci.h>
12 #include <linux/platform_device.h>
14 extern int intel_mid_pci_init(void);
15 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
16 extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev);
18 extern void intel_mid_pwr_power_off(void);
20 #define INTEL_MID_PWR_LSS_OFFSET 4
21 #define INTEL_MID_PWR_LSS_TYPE (1 << 7)
23 extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
25 extern int get_gpio_by_name(const char *name);
26 extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
27 extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
28 extern int sfi_mrtc_num;
29 extern struct sfi_rtc_table_entry sfi_mrtc_array[];
32 * Here defines the array of devices platform data that IAFW would export
33 * through SFI "DEVS" table, we use name and type to match the device and
37 char name[SFI_NAME_LEN + 1];
41 void *(*get_platform_data)(void *info);
44 #define sfi_device(i) \
45 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
46 __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
49 * struct mid_sd_board_info - template for SD device creation
50 * @name: identifies the driver
51 * @bus_num: board-specific identifier for a given SD controller
52 * @max_clk: the maximum frequency device supports
53 * @platform_data: the particular data stored there is driver-specific
55 struct mid_sd_board_info {
56 char name[SFI_NAME_LEN];
64 * Medfield is the follow-up of Moorestown, it combines two chip solution into
65 * one. Other than that it also added always-on and constant tsc and lapic
66 * timers. Medfield is the platform name, and the chip name is called Penwell
67 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
68 * identified via MSRs.
70 enum intel_mid_cpu_type {
71 /* 1 was Moorestown */
72 INTEL_MID_CPU_CHIP_PENWELL = 2,
73 INTEL_MID_CPU_CHIP_CLOVERVIEW,
74 INTEL_MID_CPU_CHIP_TANGIER,
77 extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
79 #ifdef CONFIG_X86_INTEL_MID
81 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
83 return __intel_mid_cpu_chip;
86 static inline bool intel_mid_has_msic(void)
88 return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
91 extern void intel_scu_devices_create(void);
92 extern void intel_scu_devices_destroy(void);
94 #else /* !CONFIG_X86_INTEL_MID */
96 #define intel_mid_identify_cpu() 0
97 #define intel_mid_has_msic() 0
99 static inline void intel_scu_devices_create(void) { }
100 static inline void intel_scu_devices_destroy(void) { }
102 #endif /* !CONFIG_X86_INTEL_MID */
104 enum intel_mid_timer_options {
105 INTEL_MID_TIMER_DEFAULT,
106 INTEL_MID_TIMER_APBT_ONLY,
107 INTEL_MID_TIMER_LAPIC_APBT,
110 extern enum intel_mid_timer_options intel_mid_timer_options;
112 /* Bus Select SoC Fuse value */
113 #define BSEL_SOC_FUSE_MASK 0x7
115 #define BSEL_SOC_FUSE_001 0x1
117 #define BSEL_SOC_FUSE_101 0x5
119 #define BSEL_SOC_FUSE_111 0x7
121 #define SFI_MTMR_MAX_NUM 8
122 #define SFI_MRTC_MAX 8
125 #define MRST_VRTC_MAP_SZ 1024
126 /* #define MRST_VRTC_PGOFFSET 0xc00 */
128 extern void intel_mid_rtc_init(void);
130 /* The offset for the mapping of global gpio pin to irq */
131 #define INTEL_MID_IRQ_OFFSET 0x100
133 #endif /* _ASM_X86_INTEL_MID_H */