1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Generate .byte code for some instructions not supported by old
11 #define REG_NUM_INVALID 100
13 #define REG_TYPE_R32 0
14 #define REG_TYPE_R64 1
15 #define REG_TYPE_XMM 2
16 #define REG_TYPE_INVALID 100
18 .macro R32_NUM opd r32
19 \opd = REG_NUM_INVALID
72 .macro R64_NUM opd r64
73 \opd = REG_NUM_INVALID
126 .macro XMM_NUM opd xmm
127 \opd = REG_NUM_INVALID
178 .macro REG_TYPE type reg
179 R32_NUM reg_type_r32 \reg
180 R64_NUM reg_type_r64 \reg
181 XMM_NUM reg_type_xmm \reg
182 .if reg_type_r64 <> REG_NUM_INVALID
184 .elseif reg_type_r32 <> REG_NUM_INVALID
186 .elseif reg_type_xmm <> REG_NUM_INVALID
189 \type = REG_TYPE_INVALID
197 .macro PFX_REX opd1 opd2 W=0
198 .if ((\opd1 | \opd2) & 8) || \W
199 .byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3)
203 .macro MODRM mod opd1 opd2
204 .byte \mod | (\opd1 & 7) | ((\opd2 & 7) << 3)
207 .macro PSHUFB_XMM xmm1 xmm2
208 XMM_NUM pshufb_opd1 \xmm1
209 XMM_NUM pshufb_opd2 \xmm2
211 PFX_REX pshufb_opd1 pshufb_opd2
212 .byte 0x0f, 0x38, 0x00
213 MODRM 0xc0 pshufb_opd1 pshufb_opd2
216 .macro PCLMULQDQ imm8 xmm1 xmm2
217 XMM_NUM clmul_opd1 \xmm1
218 XMM_NUM clmul_opd2 \xmm2
220 PFX_REX clmul_opd1 clmul_opd2
221 .byte 0x0f, 0x3a, 0x44
222 MODRM 0xc0 clmul_opd1 clmul_opd2
226 .macro PEXTRD imm8 xmm gpr
227 R32_NUM extrd_opd1 \gpr
228 XMM_NUM extrd_opd2 \xmm
230 PFX_REX extrd_opd1 extrd_opd2
231 .byte 0x0f, 0x3a, 0x16
232 MODRM 0xc0 extrd_opd1 extrd_opd2
236 .macro AESKEYGENASSIST rcon xmm1 xmm2
237 XMM_NUM aeskeygen_opd1 \xmm1
238 XMM_NUM aeskeygen_opd2 \xmm2
240 PFX_REX aeskeygen_opd1 aeskeygen_opd2
241 .byte 0x0f, 0x3a, 0xdf
242 MODRM 0xc0 aeskeygen_opd1 aeskeygen_opd2
246 .macro AESIMC xmm1 xmm2
247 XMM_NUM aesimc_opd1 \xmm1
248 XMM_NUM aesimc_opd2 \xmm2
250 PFX_REX aesimc_opd1 aesimc_opd2
251 .byte 0x0f, 0x38, 0xdb
252 MODRM 0xc0 aesimc_opd1 aesimc_opd2
255 .macro AESENC xmm1 xmm2
256 XMM_NUM aesenc_opd1 \xmm1
257 XMM_NUM aesenc_opd2 \xmm2
259 PFX_REX aesenc_opd1 aesenc_opd2
260 .byte 0x0f, 0x38, 0xdc
261 MODRM 0xc0 aesenc_opd1 aesenc_opd2
264 .macro AESENCLAST xmm1 xmm2
265 XMM_NUM aesenclast_opd1 \xmm1
266 XMM_NUM aesenclast_opd2 \xmm2
268 PFX_REX aesenclast_opd1 aesenclast_opd2
269 .byte 0x0f, 0x38, 0xdd
270 MODRM 0xc0 aesenclast_opd1 aesenclast_opd2
273 .macro AESDEC xmm1 xmm2
274 XMM_NUM aesdec_opd1 \xmm1
275 XMM_NUM aesdec_opd2 \xmm2
277 PFX_REX aesdec_opd1 aesdec_opd2
278 .byte 0x0f, 0x38, 0xde
279 MODRM 0xc0 aesdec_opd1 aesdec_opd2
282 .macro AESDECLAST xmm1 xmm2
283 XMM_NUM aesdeclast_opd1 \xmm1
284 XMM_NUM aesdeclast_opd2 \xmm2
286 PFX_REX aesdeclast_opd1 aesdeclast_opd2
287 .byte 0x0f, 0x38, 0xdf
288 MODRM 0xc0 aesdeclast_opd1 aesdeclast_opd2
291 .macro MOVQ_R64_XMM opd1 opd2
292 REG_TYPE movq_r64_xmm_opd1_type \opd1
293 .if movq_r64_xmm_opd1_type == REG_TYPE_XMM
294 XMM_NUM movq_r64_xmm_opd1 \opd1
295 R64_NUM movq_r64_xmm_opd2 \opd2
297 R64_NUM movq_r64_xmm_opd1 \opd1
298 XMM_NUM movq_r64_xmm_opd2 \opd2
301 PFX_REX movq_r64_xmm_opd1 movq_r64_xmm_opd2 1
302 .if movq_r64_xmm_opd1_type == REG_TYPE_XMM
307 MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2