1 /* SPDX-License-Identifier: GPL-2.0 */
9 * The legacy x87 FPU state format, as saved by FSAVE and
10 * restored by the FRSTOR instructions:
13 u32 cwd; /* FPU Control Word */
14 u32 swd; /* FPU Status Word */
15 u32 twd; /* FPU Tag Word */
16 u32 fip; /* FPU IP Offset */
17 u32 fcs; /* FPU IP Selector */
18 u32 foo; /* FPU Operand Pointer Offset */
19 u32 fos; /* FPU Operand Pointer Selector */
21 /* 8*10 bytes for each FP-reg = 80 bytes: */
24 /* Software status information [not touched by FSAVE]: */
29 * The legacy fx SSE/MMX FPU state format, as saved by FXSAVE and
30 * restored by the FXRSTOR instructions. It's similar to the FSAVE
31 * format, but differs in some areas, plus has extensions at
32 * the end for the XMM registers.
35 u16 cwd; /* Control Word */
36 u16 swd; /* Status Word */
37 u16 twd; /* Tag Word */
38 u16 fop; /* Last Instruction Opcode */
41 u64 rip; /* Instruction Pointer */
42 u64 rdp; /* Data Pointer */
45 u32 fip; /* FPU IP Offset */
46 u32 fcs; /* FPU IP Selector */
47 u32 foo; /* FPU Operand Offset */
48 u32 fos; /* FPU Operand Selector */
51 u32 mxcsr; /* MXCSR Register State */
52 u32 mxcsr_mask; /* MXCSR Mask */
54 /* 8*16 bytes for each FP-reg = 128 bytes: */
57 /* 16*16 bytes for each XMM-reg = 256 bytes: */
67 } __attribute__((aligned(16)));
69 /* Default value for fxregs_state.mxcsr: */
70 #define MXCSR_DEFAULT 0x1f80
72 /* Copy both mxcsr & mxcsr_flags with a single u64 memcpy: */
73 #define MXCSR_AND_FLAGS_SIZE sizeof(u64)
76 * Software based FPU emulation state. This is arbitrary really,
77 * it matches the x87 format to make it easier to understand:
87 /* 8*10 bytes for each FP-reg = 80 bytes: */
95 struct math_emu_info *info;
100 * List of XSAVE features Linux knows about:
106 * Values above here are "legacy states".
107 * Those below are "extended states".
115 XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
118 XFEATURE_RSRVD_COMP_11,
119 XFEATURE_RSRVD_COMP_12,
120 XFEATURE_RSRVD_COMP_13,
121 XFEATURE_RSRVD_COMP_14,
127 #define XFEATURE_MASK_FP (1 << XFEATURE_FP)
128 #define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
129 #define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
130 #define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
131 #define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
132 #define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
133 #define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
134 #define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
135 #define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
136 #define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
137 #define XFEATURE_MASK_PASID (1 << XFEATURE_PASID)
138 #define XFEATURE_MASK_LBR (1 << XFEATURE_LBR)
140 #define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
141 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \
142 | XFEATURE_MASK_ZMM_Hi256 \
143 | XFEATURE_MASK_Hi16_ZMM)
145 #define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
160 * There are 16x 256-bit AVX registers named YMM0-YMM15.
161 * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
162 * and are stored in 'struct fxregs_state::xmm_space[]' in the
165 * The high 128 bits are stored here.
168 struct reg_128_bit hi_ymm[16];
171 /* Intel MPX support: */
178 * State component 3 is used for the 4 128-bit bounds registers
180 struct mpx_bndreg_state {
181 struct mpx_bndreg bndreg[4];
185 * State component 4 is used for the 64-bit user-mode MPX
186 * configuration register BNDCFGU and the 64-bit MPX status
187 * register BNDSTATUS. We call the pair "BNDCSR".
195 * The BNDCSR state is padded out to be 64-bytes in size.
197 struct mpx_bndcsr_state {
199 struct mpx_bndcsr bndcsr;
200 u8 pad_to_64_bytes[64];
204 /* AVX-512 Components: */
207 * State component 5 is used for the 8 64-bit opmask registers
208 * k0-k7 (opmask state).
210 struct avx_512_opmask_state {
215 * State component 6 is used for the upper 256 bits of the
216 * registers ZMM0-ZMM15. These 16 256-bit values are denoted
217 * ZMM0_H-ZMM15_H (ZMM_Hi256 state).
219 struct avx_512_zmm_uppers_state {
220 struct reg_256_bit zmm_upper[16];
224 * State component 7 is used for the 16 512-bit registers
225 * ZMM16-ZMM31 (Hi16_ZMM state).
227 struct avx_512_hi16_state {
228 struct reg_512_bit hi16_zmm[16];
232 * State component 9: 32-bit PKRU register. The state is
233 * 8 bytes long but only 4 bytes is used currently.
241 * State component 15: Architectural LBR configuration state.
242 * The size of Arch LBR state depends on the number of LBRs (lbr_depth).
251 struct arch_lbr_state {
257 struct lbr_entry entries[];
261 * State component 10 is supervisor state used for context-switching the
264 struct ia32_pasid_state {
268 struct xstate_header {
272 } __attribute__((packed));
275 * xstate_header.xcomp_bv[63] indicates that the extended_state_area
276 * is in compacted format.
278 #define XCOMP_BV_COMPACTED_FORMAT ((u64)1 << 63)
281 * This is our most modern FPU state format, as saved by the XSAVE
282 * and restored by the XRSTOR instructions.
284 * It consists of a legacy fxregs portion, an xstate header and
285 * subsequent areas as defined by the xstate header. Not all CPUs
286 * support all the extensions, so the size of the extended area
287 * can vary quite a bit between CPUs.
290 struct fxregs_state i387;
291 struct xstate_header header;
292 u8 extended_state_area[0];
293 } __attribute__ ((packed, aligned (64)));
296 * This is a union of all the possible FPU state formats
297 * put together, so that we can pick the right one runtime.
299 * The size of the structure is determined by the largest
300 * member - which is the xsave area. The padding is there
301 * to ensure that statically-allocated task_structs (just
302 * the init_task today) have enough space.
305 struct fregs_state fsave;
306 struct fxregs_state fxsave;
307 struct swregs_state soft;
308 struct xregs_state xsave;
309 u8 __padding[PAGE_SIZE];
313 * Highest level per task FPU state data structure that
314 * contains the FPU register state plus various FPU
321 * Records the last CPU on which this context was loaded into
322 * FPU registers. (In the lazy-restore case we might be
323 * able to reuse FPU registers across multiple context switches
324 * this way, if no intermediate task used the FPU.)
326 * A value of -1 is used to indicate that the FPU state in context
327 * memory is newer than the FPU state in registers, and that the
328 * FPU state should be reloaded next time the task is run.
330 unsigned int last_cpu;
335 * Records the timestamp of AVX512 use during last context switch.
337 unsigned long avx512_timestamp;
342 * In-memory copy of all FPU registers that we save/restore
343 * over context switches. If the task is using the FPU then
344 * the registers in the FPU are more recent than this state
345 * copy. If the task context-switches away then they get
346 * saved here and represent the FPU state.
348 union fpregs_state state;
350 * WARNING: 'state' is dynamically-sized. Do not put
351 * anything after it here.
355 #endif /* _ASM_X86_FPU_H */