1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 * x86-64 work by Andi Kleen 2002
11 #ifndef _ASM_X86_FPU_INTERNAL_H
12 #define _ASM_X86_FPU_INTERNAL_H
14 #include <linux/compat.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
20 #include <asm/fpu/api.h>
21 #include <asm/fpu/xstate.h>
22 #include <asm/fpu/xcr.h>
23 #include <asm/cpufeature.h>
24 #include <asm/trace/fpu.h>
27 * High level FPU state handling functions:
29 extern void fpu__save(struct fpu *fpu);
30 extern int fpu__restore_sig(void __user *buf, int ia32_frame);
31 extern void fpu__drop(struct fpu *fpu);
32 extern int fpu__copy(struct task_struct *dst, struct task_struct *src);
33 extern void fpu__clear_user_states(struct fpu *fpu);
34 extern void fpu__clear_all(struct fpu *fpu);
35 extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
38 * Boot time FPU initialization functions:
40 extern void fpu__init_cpu(void);
41 extern void fpu__init_system_xstate(void);
42 extern void fpu__init_cpu_xstate(void);
43 extern void fpu__init_system(struct cpuinfo_x86 *c);
44 extern void fpu__init_check_bugs(void);
45 extern void fpu__resume_cpu(void);
50 #ifdef CONFIG_X86_DEBUG_FPU
51 # define WARN_ON_FPU(x) WARN_ON_ONCE(x)
53 # define WARN_ON_FPU(x) ({ (void)(x); 0; })
57 * FPU related CPU feature flag helper routines:
59 static __always_inline __pure bool use_xsaveopt(void)
61 return static_cpu_has(X86_FEATURE_XSAVEOPT);
64 static __always_inline __pure bool use_xsave(void)
66 return static_cpu_has(X86_FEATURE_XSAVE);
69 static __always_inline __pure bool use_fxsr(void)
71 return static_cpu_has(X86_FEATURE_FXSR);
75 * fpstate handling functions:
78 extern union fpregs_state init_fpstate;
80 extern void fpstate_init(union fpregs_state *state);
81 #ifdef CONFIG_MATH_EMULATION
82 extern void fpstate_init_soft(struct swregs_state *soft);
84 static inline void fpstate_init_soft(struct swregs_state *soft) {}
87 #define user_insn(insn, output, input...) \
93 asm volatile(ASM_STAC "\n" \
96 ".section .fixup,\"ax\"\n" \
97 "3: movl $-1,%[err]\n" \
100 _ASM_EXTABLE(1b, 3b) \
101 : [err] "=r" (err), output \
106 #define kernel_insn_err(insn, output, input...) \
109 asm volatile("1:" #insn "\n\t" \
111 ".section .fixup,\"ax\"\n" \
112 "3: movl $-1,%[err]\n" \
115 _ASM_EXTABLE(1b, 3b) \
116 : [err] "=r" (err), output \
121 #define kernel_insn(insn, output, input...) \
122 asm volatile("1:" #insn "\n\t" \
124 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore) \
127 static inline int copy_fregs_to_user(struct fregs_state __user *fx)
129 return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
132 static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
134 if (IS_ENABLED(CONFIG_X86_32))
135 return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
137 return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
141 static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
143 if (IS_ENABLED(CONFIG_X86_32))
144 kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
146 kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
149 static inline int copy_kernel_to_fxregs_err(struct fxregs_state *fx)
151 if (IS_ENABLED(CONFIG_X86_32))
152 return kernel_insn_err(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
154 return kernel_insn_err(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
157 static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
159 if (IS_ENABLED(CONFIG_X86_32))
160 return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
162 return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
165 static inline void copy_kernel_to_fregs(struct fregs_state *fx)
167 kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
170 static inline int copy_kernel_to_fregs_err(struct fregs_state *fx)
172 return kernel_insn_err(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
175 static inline int copy_user_to_fregs(struct fregs_state __user *fx)
177 return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
180 static inline void copy_fxregs_to_kernel(struct fpu *fpu)
182 if (IS_ENABLED(CONFIG_X86_32))
183 asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
185 asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
188 static inline void fxsave(struct fxregs_state *fx)
190 if (IS_ENABLED(CONFIG_X86_32))
191 asm volatile( "fxsave %[fx]" : [fx] "=m" (*fx));
193 asm volatile("fxsaveq %[fx]" : [fx] "=m" (*fx));
196 /* These macros all use (%edi)/(%rdi) as the single memory argument. */
197 #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
198 #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
199 #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
200 #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
201 #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
203 #define XSTATE_OP(op, st, lmask, hmask, err) \
204 asm volatile("1:" op "\n\t" \
205 "xor %[err], %[err]\n" \
207 ".pushsection .fixup,\"ax\"\n\t" \
208 "3: movl $-2,%[err]\n\t" \
211 _ASM_EXTABLE(1b, 3b) \
213 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
217 * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
218 * format and supervisor states in addition to modified optimization in
221 * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
222 * supports modified optimization which is not supported by XSAVE.
224 * We use XSAVE as a fallback.
226 * The 661 label is defined in the ALTERNATIVE* macros as the address of the
227 * original instruction which gets replaced. We need to use it here as the
228 * address of the instruction where we might get an exception at.
230 #define XSTATE_XSAVE(st, lmask, hmask, err) \
231 asm volatile(ALTERNATIVE_2(XSAVE, \
232 XSAVEOPT, X86_FEATURE_XSAVEOPT, \
233 XSAVES, X86_FEATURE_XSAVES) \
235 "xor %[err], %[err]\n" \
237 ".pushsection .fixup,\"ax\"\n" \
238 "4: movl $-2, %[err]\n" \
241 _ASM_EXTABLE(661b, 4b) \
243 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
247 * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
250 #define XSTATE_XRESTORE(st, lmask, hmask) \
251 asm volatile(ALTERNATIVE(XRSTOR, \
252 XRSTORS, X86_FEATURE_XSAVES) \
255 _ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\
257 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
261 * This function is called only during boot time when x86 caps are not set
262 * up and alternative can not be used yet.
264 static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate)
268 u32 hmask = mask >> 32;
271 WARN_ON(system_state != SYSTEM_BOOTING);
273 if (boot_cpu_has(X86_FEATURE_XSAVES))
274 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
276 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
279 * We should never fault when copying from a kernel buffer, and the FPU
280 * state we set at boot time should be valid.
286 * Save processor xstate to xsave area.
288 static inline void copy_xregs_to_kernel(struct xregs_state *xstate)
290 u64 mask = xfeatures_mask_all;
292 u32 hmask = mask >> 32;
295 WARN_ON_FPU(!alternatives_patched);
297 XSTATE_XSAVE(xstate, lmask, hmask, err);
299 /* We should never fault when copying to a kernel buffer: */
304 * Restore processor xstate from xsave area.
306 static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask)
309 u32 hmask = mask >> 32;
311 XSTATE_XRESTORE(xstate, lmask, hmask);
315 * Save xstate to user space xsave area.
317 * We don't use modified optimization because xrstor/xrstors might track
318 * a different application.
320 * We don't use compacted format xsave area for
321 * backward compatibility for old applications which don't understand
322 * compacted format of xsave area.
324 static inline int copy_xregs_to_user(struct xregs_state __user *buf)
326 u64 mask = xfeatures_mask_user();
328 u32 hmask = mask >> 32;
332 * Clear the xsave header first, so that reserved fields are
333 * initialized to zero.
335 err = __clear_user(&buf->header, sizeof(buf->header));
340 XSTATE_OP(XSAVE, buf, lmask, hmask, err);
347 * Restore xstate from user space xsave area.
349 static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask)
351 struct xregs_state *xstate = ((__force struct xregs_state *)buf);
353 u32 hmask = mask >> 32;
357 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
364 * Restore xstate from kernel space xsave area, return an error code instead of
367 static inline int copy_kernel_to_xregs_err(struct xregs_state *xstate, u64 mask)
370 u32 hmask = mask >> 32;
373 if (static_cpu_has(X86_FEATURE_XSAVES))
374 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
376 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
381 extern int copy_fpregs_to_fpstate(struct fpu *fpu);
383 static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask)
386 copy_kernel_to_xregs(&fpstate->xsave, mask);
389 copy_kernel_to_fxregs(&fpstate->fxsave);
391 copy_kernel_to_fregs(&fpstate->fsave);
395 static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
398 * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
399 * pending. Clear the x87 state here by setting it to fixed values.
400 * "m" is a random variable that should be in L1.
402 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
406 "fildl %P[addr]" /* set F?P to defined value */
407 : : [addr] "m" (fpstate));
410 __copy_kernel_to_fpregs(fpstate, -1);
413 extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
416 * FPU context switch related helper methods:
419 DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
422 * The in-register FPU state for an FPU context on a CPU is assumed to be
423 * valid if the fpu->last_cpu matches the CPU, and the fpu_fpregs_owner_ctx
426 * If the FPU register state is valid, the kernel can skip restoring the
427 * FPU state from memory.
429 * Any code that clobbers the FPU registers or updates the in-memory
430 * FPU state for a task MUST let the rest of the kernel know that the
431 * FPU registers are no longer valid for this task.
433 * Either one of these invalidation functions is enough. Invalidate
434 * a resource you control: CPU if using the CPU for something else
435 * (with preemption disabled), FPU for the current task, or a task that
436 * is prevented from running by the current task.
438 static inline void __cpu_invalidate_fpregs_state(void)
440 __this_cpu_write(fpu_fpregs_owner_ctx, NULL);
443 static inline void __fpu_invalidate_fpregs_state(struct fpu *fpu)
448 static inline int fpregs_state_valid(struct fpu *fpu, unsigned int cpu)
450 return fpu == this_cpu_read(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
454 * These generally need preemption protection to work,
455 * do try to avoid using these on their own:
457 static inline void fpregs_deactivate(struct fpu *fpu)
459 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
460 trace_x86_fpu_regs_deactivated(fpu);
463 static inline void fpregs_activate(struct fpu *fpu)
465 this_cpu_write(fpu_fpregs_owner_ctx, fpu);
466 trace_x86_fpu_regs_activated(fpu);
470 * Internal helper, do not use directly. Use switch_fpu_return() instead.
472 static inline void __fpregs_load_activate(void)
474 struct fpu *fpu = ¤t->thread.fpu;
475 int cpu = smp_processor_id();
477 if (WARN_ON_ONCE(current->flags & PF_KTHREAD))
480 if (!fpregs_state_valid(fpu, cpu)) {
481 copy_kernel_to_fpregs(&fpu->state);
482 fpregs_activate(fpu);
485 clear_thread_flag(TIF_NEED_FPU_LOAD);
489 * FPU state switching for scheduling.
491 * This is a two-stage process:
493 * - switch_fpu_prepare() saves the old state.
494 * This is done within the context of the old process.
496 * - switch_fpu_finish() sets TIF_NEED_FPU_LOAD; the floating point state
497 * will get loaded on return to userspace, or when the kernel needs it.
499 * If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers
500 * are saved in the current thread's FPU register state.
502 * If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not
503 * hold current()'s FPU registers. It is required to load the
504 * registers before returning to userland or using the content
507 * The FPU context is only stored/restored for a user task and
508 * PF_KTHREAD is used to distinguish between kernel and user threads.
510 static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu)
512 if (static_cpu_has(X86_FEATURE_FPU) && !(current->flags & PF_KTHREAD)) {
513 if (!copy_fpregs_to_fpstate(old_fpu))
514 old_fpu->last_cpu = -1;
516 old_fpu->last_cpu = cpu;
518 /* But leave fpu_fpregs_owner_ctx! */
519 trace_x86_fpu_regs_deactivated(old_fpu);
524 * Misc helper functions:
528 * Load PKRU from the FPU context if available. Delay loading of the
529 * complete FPU state until the return to userland.
531 static inline void switch_fpu_finish(struct fpu *new_fpu)
533 u32 pkru_val = init_pkru_value;
534 struct pkru_state *pk;
536 if (!static_cpu_has(X86_FEATURE_FPU))
539 set_thread_flag(TIF_NEED_FPU_LOAD);
541 if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
545 * PKRU state is switched eagerly because it needs to be valid before we
546 * return to userland e.g. for a copy_to_user() operation.
548 if (!(current->flags & PF_KTHREAD)) {
550 * If the PKRU bit in xsave.header.xfeatures is not set,
551 * then the PKRU component was in init state, which means
552 * XRSTOR will set PKRU to 0. If the bit is not set then
553 * get_xsave_addr() will return NULL because the PKRU value
554 * in memory is not valid. This means pkru_val has to be
555 * set to 0 and not to init_pkru_value.
557 pk = get_xsave_addr(&new_fpu->state.xsave, XFEATURE_PKRU);
558 pkru_val = pk ? pk->pkru : 0;
560 __write_pkru(pkru_val);
563 #endif /* _ASM_X86_FPU_INTERNAL_H */