1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1994 Linus Torvalds
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 * x86-64 work by Andi Kleen 2002
11 #ifndef _ASM_X86_FPU_INTERNAL_H
12 #define _ASM_X86_FPU_INTERNAL_H
14 #include <linux/compat.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
20 #include <asm/fpu/api.h>
21 #include <asm/fpu/xstate.h>
22 #include <asm/cpufeature.h>
23 #include <asm/trace/fpu.h>
26 * High level FPU state handling functions:
28 extern void fpu__prepare_read(struct fpu *fpu);
29 extern void fpu__prepare_write(struct fpu *fpu);
30 extern void fpu__save(struct fpu *fpu);
31 extern int fpu__restore_sig(void __user *buf, int ia32_frame);
32 extern void fpu__drop(struct fpu *fpu);
33 extern int fpu__copy(struct task_struct *dst, struct task_struct *src);
34 extern void fpu__clear_user_states(struct fpu *fpu);
35 extern void fpu__clear_all(struct fpu *fpu);
36 extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
37 extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate);
40 * Boot time FPU initialization functions:
42 extern void fpu__init_cpu(void);
43 extern void fpu__init_system_xstate(void);
44 extern void fpu__init_cpu_xstate(void);
45 extern void fpu__init_system(struct cpuinfo_x86 *c);
46 extern void fpu__init_check_bugs(void);
47 extern void fpu__resume_cpu(void);
48 extern u64 fpu__get_supported_xfeatures_mask(void);
53 #ifdef CONFIG_X86_DEBUG_FPU
54 # define WARN_ON_FPU(x) WARN_ON_ONCE(x)
56 # define WARN_ON_FPU(x) ({ (void)(x); 0; })
60 * FPU related CPU feature flag helper routines:
62 static __always_inline __pure bool use_xsaveopt(void)
64 return static_cpu_has(X86_FEATURE_XSAVEOPT);
67 static __always_inline __pure bool use_xsave(void)
69 return static_cpu_has(X86_FEATURE_XSAVE);
72 static __always_inline __pure bool use_fxsr(void)
74 return static_cpu_has(X86_FEATURE_FXSR);
78 * fpstate handling functions:
81 extern union fpregs_state init_fpstate;
83 extern void fpstate_init(union fpregs_state *state);
84 #ifdef CONFIG_MATH_EMULATION
85 extern void fpstate_init_soft(struct swregs_state *soft);
87 static inline void fpstate_init_soft(struct swregs_state *soft) {}
90 static inline void fpstate_init_xstate(struct xregs_state *xsave)
93 * XRSTORS requires these bits set in xcomp_bv, or it will
96 xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask_all;
99 static inline void fpstate_init_fxstate(struct fxregs_state *fx)
102 fx->mxcsr = MXCSR_DEFAULT;
104 extern void fpstate_sanitize_xstate(struct fpu *fpu);
106 #define user_insn(insn, output, input...) \
112 asm volatile(ASM_STAC "\n" \
114 "2: " ASM_CLAC "\n" \
115 ".section .fixup,\"ax\"\n" \
116 "3: movl $-1,%[err]\n" \
119 _ASM_EXTABLE(1b, 3b) \
120 : [err] "=r" (err), output \
125 #define kernel_insn_err(insn, output, input...) \
128 asm volatile("1:" #insn "\n\t" \
130 ".section .fixup,\"ax\"\n" \
131 "3: movl $-1,%[err]\n" \
134 _ASM_EXTABLE(1b, 3b) \
135 : [err] "=r" (err), output \
140 #define kernel_insn(insn, output, input...) \
141 asm volatile("1:" #insn "\n\t" \
143 _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore) \
146 static inline int copy_fregs_to_user(struct fregs_state __user *fx)
148 return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
151 static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
153 if (IS_ENABLED(CONFIG_X86_32))
154 return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
156 return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
160 static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
162 if (IS_ENABLED(CONFIG_X86_32))
163 kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
165 kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
168 static inline int copy_kernel_to_fxregs_err(struct fxregs_state *fx)
170 if (IS_ENABLED(CONFIG_X86_32))
171 return kernel_insn_err(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
173 return kernel_insn_err(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
176 static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
178 if (IS_ENABLED(CONFIG_X86_32))
179 return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
181 return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
184 static inline void copy_kernel_to_fregs(struct fregs_state *fx)
186 kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
189 static inline int copy_kernel_to_fregs_err(struct fregs_state *fx)
191 return kernel_insn_err(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
194 static inline int copy_user_to_fregs(struct fregs_state __user *fx)
196 return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
199 static inline void copy_fxregs_to_kernel(struct fpu *fpu)
201 if (IS_ENABLED(CONFIG_X86_32))
202 asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
204 asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
207 /* These macros all use (%edi)/(%rdi) as the single memory argument. */
208 #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
209 #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
210 #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
211 #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
212 #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
214 #define XSTATE_OP(op, st, lmask, hmask, err) \
215 asm volatile("1:" op "\n\t" \
216 "xor %[err], %[err]\n" \
218 ".pushsection .fixup,\"ax\"\n\t" \
219 "3: movl $-2,%[err]\n\t" \
222 _ASM_EXTABLE(1b, 3b) \
224 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
228 * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
229 * format and supervisor states in addition to modified optimization in
232 * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
233 * supports modified optimization which is not supported by XSAVE.
235 * We use XSAVE as a fallback.
237 * The 661 label is defined in the ALTERNATIVE* macros as the address of the
238 * original instruction which gets replaced. We need to use it here as the
239 * address of the instruction where we might get an exception at.
241 #define XSTATE_XSAVE(st, lmask, hmask, err) \
242 asm volatile(ALTERNATIVE_2(XSAVE, \
243 XSAVEOPT, X86_FEATURE_XSAVEOPT, \
244 XSAVES, X86_FEATURE_XSAVES) \
246 "xor %[err], %[err]\n" \
248 ".pushsection .fixup,\"ax\"\n" \
249 "4: movl $-2, %[err]\n" \
252 _ASM_EXTABLE(661b, 4b) \
254 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
258 * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
261 #define XSTATE_XRESTORE(st, lmask, hmask) \
262 asm volatile(ALTERNATIVE(XRSTOR, \
263 XRSTORS, X86_FEATURE_XSAVES) \
266 _ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\
268 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
272 * This function is called only during boot time when x86 caps are not set
273 * up and alternative can not be used yet.
275 static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate)
279 u32 hmask = mask >> 32;
282 WARN_ON(system_state != SYSTEM_BOOTING);
284 if (boot_cpu_has(X86_FEATURE_XSAVES))
285 XSTATE_OP(XSAVES, xstate, lmask, hmask, err);
287 XSTATE_OP(XSAVE, xstate, lmask, hmask, err);
289 /* We should never fault when copying to a kernel buffer: */
294 * This function is called only during boot time when x86 caps are not set
295 * up and alternative can not be used yet.
297 static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate)
301 u32 hmask = mask >> 32;
304 WARN_ON(system_state != SYSTEM_BOOTING);
306 if (boot_cpu_has(X86_FEATURE_XSAVES))
307 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
309 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
312 * We should never fault when copying from a kernel buffer, and the FPU
313 * state we set at boot time should be valid.
319 * Save processor xstate to xsave area.
321 static inline void copy_xregs_to_kernel(struct xregs_state *xstate)
325 u32 hmask = mask >> 32;
328 WARN_ON_FPU(!alternatives_patched);
330 XSTATE_XSAVE(xstate, lmask, hmask, err);
332 /* We should never fault when copying to a kernel buffer: */
337 * Restore processor xstate from xsave area.
339 static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask)
342 u32 hmask = mask >> 32;
344 XSTATE_XRESTORE(xstate, lmask, hmask);
348 * Save xstate to user space xsave area.
350 * We don't use modified optimization because xrstor/xrstors might track
351 * a different application.
353 * We don't use compacted format xsave area for
354 * backward compatibility for old applications which don't understand
355 * compacted format of xsave area.
357 static inline int copy_xregs_to_user(struct xregs_state __user *buf)
362 * Clear the xsave header first, so that reserved fields are
363 * initialized to zero.
365 err = __clear_user(&buf->header, sizeof(buf->header));
370 XSTATE_OP(XSAVE, buf, -1, -1, err);
377 * Restore xstate from user space xsave area.
379 static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask)
381 struct xregs_state *xstate = ((__force struct xregs_state *)buf);
383 u32 hmask = mask >> 32;
387 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
394 * Restore xstate from kernel space xsave area, return an error code instead of
397 static inline int copy_kernel_to_xregs_err(struct xregs_state *xstate, u64 mask)
400 u32 hmask = mask >> 32;
403 if (static_cpu_has(X86_FEATURE_XSAVES))
404 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
406 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
412 * These must be called with preempt disabled. Returns
413 * 'true' if the FPU state is still intact and we can
414 * keep registers active.
416 * The legacy FNSAVE instruction cleared all FPU state
417 * unconditionally, so registers are essentially destroyed.
418 * Modern FPU state can be kept in registers, if there are
419 * no pending FP exceptions.
421 static inline int copy_fpregs_to_fpstate(struct fpu *fpu)
423 if (likely(use_xsave())) {
424 copy_xregs_to_kernel(&fpu->state.xsave);
427 * AVX512 state is tracked here because its use is
428 * known to slow the max clock speed of the core.
430 if (fpu->state.xsave.header.xfeatures & XFEATURE_MASK_AVX512)
431 fpu->avx512_timestamp = jiffies;
435 if (likely(use_fxsr())) {
436 copy_fxregs_to_kernel(fpu);
441 * Legacy FPU register saving, FNSAVE always clears FPU registers,
442 * so we have to mark them inactive:
444 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave));
449 static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask)
452 copy_kernel_to_xregs(&fpstate->xsave, mask);
455 copy_kernel_to_fxregs(&fpstate->fxsave);
457 copy_kernel_to_fregs(&fpstate->fsave);
461 static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
464 * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
465 * pending. Clear the x87 state here by setting it to fixed values.
466 * "m" is a random variable that should be in L1.
468 if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
472 "fildl %P[addr]" /* set F?P to defined value */
473 : : [addr] "m" (fpstate));
476 __copy_kernel_to_fpregs(fpstate, -1);
479 extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
482 * FPU context switch related helper methods:
485 DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
488 * The in-register FPU state for an FPU context on a CPU is assumed to be
489 * valid if the fpu->last_cpu matches the CPU, and the fpu_fpregs_owner_ctx
492 * If the FPU register state is valid, the kernel can skip restoring the
493 * FPU state from memory.
495 * Any code that clobbers the FPU registers or updates the in-memory
496 * FPU state for a task MUST let the rest of the kernel know that the
497 * FPU registers are no longer valid for this task.
499 * Either one of these invalidation functions is enough. Invalidate
500 * a resource you control: CPU if using the CPU for something else
501 * (with preemption disabled), FPU for the current task, or a task that
502 * is prevented from running by the current task.
504 static inline void __cpu_invalidate_fpregs_state(void)
506 __this_cpu_write(fpu_fpregs_owner_ctx, NULL);
509 static inline void __fpu_invalidate_fpregs_state(struct fpu *fpu)
514 static inline int fpregs_state_valid(struct fpu *fpu, unsigned int cpu)
516 return fpu == this_cpu_read(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
520 * These generally need preemption protection to work,
521 * do try to avoid using these on their own:
523 static inline void fpregs_deactivate(struct fpu *fpu)
525 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
526 trace_x86_fpu_regs_deactivated(fpu);
529 static inline void fpregs_activate(struct fpu *fpu)
531 this_cpu_write(fpu_fpregs_owner_ctx, fpu);
532 trace_x86_fpu_regs_activated(fpu);
536 * Internal helper, do not use directly. Use switch_fpu_return() instead.
538 static inline void __fpregs_load_activate(void)
540 struct fpu *fpu = ¤t->thread.fpu;
541 int cpu = smp_processor_id();
543 if (WARN_ON_ONCE(current->flags & PF_KTHREAD))
546 if (!fpregs_state_valid(fpu, cpu)) {
547 copy_kernel_to_fpregs(&fpu->state);
548 fpregs_activate(fpu);
551 clear_thread_flag(TIF_NEED_FPU_LOAD);
555 * FPU state switching for scheduling.
557 * This is a two-stage process:
559 * - switch_fpu_prepare() saves the old state.
560 * This is done within the context of the old process.
562 * - switch_fpu_finish() sets TIF_NEED_FPU_LOAD; the floating point state
563 * will get loaded on return to userspace, or when the kernel needs it.
565 * If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers
566 * are saved in the current thread's FPU register state.
568 * If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not
569 * hold current()'s FPU registers. It is required to load the
570 * registers before returning to userland or using the content
573 * The FPU context is only stored/restored for a user task and
574 * PF_KTHREAD is used to distinguish between kernel and user threads.
576 static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu)
578 if (static_cpu_has(X86_FEATURE_FPU) && !(current->flags & PF_KTHREAD)) {
579 if (!copy_fpregs_to_fpstate(old_fpu))
580 old_fpu->last_cpu = -1;
582 old_fpu->last_cpu = cpu;
584 /* But leave fpu_fpregs_owner_ctx! */
585 trace_x86_fpu_regs_deactivated(old_fpu);
590 * Misc helper functions:
594 * Load PKRU from the FPU context if available. Delay loading of the
595 * complete FPU state until the return to userland.
597 static inline void switch_fpu_finish(struct fpu *new_fpu)
599 u32 pkru_val = init_pkru_value;
600 struct pkru_state *pk;
602 if (!static_cpu_has(X86_FEATURE_FPU))
605 set_thread_flag(TIF_NEED_FPU_LOAD);
607 if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
611 * PKRU state is switched eagerly because it needs to be valid before we
612 * return to userland e.g. for a copy_to_user() operation.
615 pk = get_xsave_addr(&new_fpu->state.xsave, XFEATURE_PKRU);
619 __write_pkru(pkru_val);
623 * MXCSR and XCR definitions:
626 extern unsigned int mxcsr_feature_mask;
628 #define XCR_XFEATURE_ENABLED_MASK 0x00000000
630 static inline u64 xgetbv(u32 index)
634 asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
635 : "=a" (eax), "=d" (edx)
637 return eax + ((u64)edx << 32);
640 static inline void xsetbv(u32 index, u64 value)
643 u32 edx = value >> 32;
645 asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
646 : : "a" (eax), "d" (edx), "c" (index));
649 #endif /* _ASM_X86_FPU_INTERNAL_H */