arch/x86/include/asm/fpu/internal.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 1994 Linus Torvalds
   4  *
   5  * Pentium III FXSR, SSE support
   6  * General FPU state handling cleanups
   7  *      Gareth Hughes <gareth@valinux.com>, May 2000
   8  * x86-64 work by Andi Kleen 2002
   9  */
  10
  11 #ifndef _ASM_X86_FPU_INTERNAL_H
  12 #define _ASM_X86_FPU_INTERNAL_H
  13
  14 #include <linux/compat.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/mm.h>
  18
  19 #include <asm/user.h>
  20 #include <asm/fpu/api.h>
  21 #include <asm/fpu/xstate.h>
  22 #include <asm/fpu/xcr.h>
  23 #include <asm/cpufeature.h>
  24 #include <asm/trace/fpu.h>
  25
  26 /*
  27  * High level FPU state handling functions:
  28  */
  29 extern void fpu__prepare_read(struct fpu *fpu);
  30 extern void fpu__prepare_write(struct fpu *fpu);
  31 extern void fpu__save(struct fpu *fpu);
  32 extern int  fpu__restore_sig(void __user *buf, int ia32_frame);
  33 extern void fpu__drop(struct fpu *fpu);
  34 extern int  fpu__copy(struct task_struct *dst, struct task_struct *src);
  35 extern void fpu__clear_user_states(struct fpu *fpu);
  36 extern void fpu__clear_all(struct fpu *fpu);
  37 extern int  fpu__exception_code(struct fpu *fpu, int trap_nr);
  38
  39 /*
  40  * Boot time FPU initialization functions:
  41  */
  42 extern void fpu__init_cpu(void);
  43 extern void fpu__init_system_xstate(void);
  44 extern void fpu__init_cpu_xstate(void);
  45 extern void fpu__init_system(struct cpuinfo_x86 *c);
  46 extern void fpu__init_check_bugs(void);
  47 extern void fpu__resume_cpu(void);
  48 extern u64 fpu__get_supported_xfeatures_mask(void);
  49
  50 /*
  51  * Debugging facility:
  52  */
  53 #ifdef CONFIG_X86_DEBUG_FPU
  54 # define WARN_ON_FPU(x) WARN_ON_ONCE(x)
  55 #else
  56 # define WARN_ON_FPU(x) ({ (void)(x); 0; })
  57 #endif
  58
  59 /*
  60  * FPU related CPU feature flag helper routines:
  61  */
  62 static __always_inline __pure bool use_xsaveopt(void)
  63 {
  64         return static_cpu_has(X86_FEATURE_XSAVEOPT);
  65 }
  66
  67 static __always_inline __pure bool use_xsave(void)
  68 {
  69         return static_cpu_has(X86_FEATURE_XSAVE);
  70 }
  71
  72 static __always_inline __pure bool use_fxsr(void)
  73 {
  74         return static_cpu_has(X86_FEATURE_FXSR);
  75 }
  76
  77 /*
  78  * fpstate handling functions:
  79  */
  80
  81 extern union fpregs_state init_fpstate;
  82
  83 extern void fpstate_init(union fpregs_state *state);
  84 #ifdef CONFIG_MATH_EMULATION
  85 extern void fpstate_init_soft(struct swregs_state *soft);
  86 #else
  87 static inline void fpstate_init_soft(struct swregs_state *soft) {}
  88 #endif
  89
  90 static inline void fpstate_init_xstate(struct xregs_state *xsave)
  91 {
  92         /*
  93          * XRSTORS requires these bits set in xcomp_bv, or it will
  94          * trigger #GP:
  95          */
  96         xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask_all;
  97 }
  98
  99 static inline void fpstate_init_fxstate(struct fxregs_state *fx)
 100 {
 101         fx->cwd = 0x37f;
 102         fx->mxcsr = MXCSR_DEFAULT;
 103 }
 104 extern void fpstate_sanitize_xstate(struct fpu *fpu);
 105
 106 #define user_insn(insn, output, input...)                               \
 107 ({                                                                      \
 108         int err;                                                        \
 109                                                                         \
 110         might_fault();                                                  \
 111                                                                         \
 112         asm volatile(ASM_STAC "\n"                                      \
 113                      "1:" #insn "\n\t"                                  \
 114                      "2: " ASM_CLAC "\n"                                \
 115                      ".section .fixup,\"ax\"\n"                         \
 116                      "3:  movl $-1,%[err]\n"                            \
 117                      "    jmp  2b\n"                                    \
 118                      ".previous\n"                                      \
 119                      _ASM_EXTABLE(1b, 3b)                               \
 120                      : [err] "=r" (err), output                         \
 121                      : "0"(0), input);                                  \
 122         err;                                                            \
 123 })
 124
 125 #define kernel_insn_err(insn, output, input...)                         \
 126 ({                                                                      \
 127         int err;                                                        \
 128         asm volatile("1:" #insn "\n\t"                                  \
 129                      "2:\n"                                             \
 130                      ".section .fixup,\"ax\"\n"                         \
 131                      "3:  movl $-1,%[err]\n"                            \
 132                      "    jmp  2b\n"                                    \
 133                      ".previous\n"                                      \
 134                      _ASM_EXTABLE(1b, 3b)                               \
 135                      : [err] "=r" (err), output                         \
 136                      : "0"(0), input);                                  \
 137         err;                                                            \
 138 })
 139
 140 #define kernel_insn(insn, output, input...)                             \
 141         asm volatile("1:" #insn "\n\t"                                  \
 142                      "2:\n"                                             \
 143                      _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore)  \
 144                      : output : input)
 145
 146 static inline int copy_fregs_to_user(struct fregs_state __user *fx)
 147 {
 148         return user_insn(fnsave %[fx]; fwait,  [fx] "=m" (*fx), "m" (*fx));
 149 }
 150
 151 static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
 152 {
 153         if (IS_ENABLED(CONFIG_X86_32))
 154                 return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
 155         else
 156                 return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
 157
 158 }
 159
 160 static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
 161 {
 162         if (IS_ENABLED(CONFIG_X86_32))
 163                 kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 164         else
 165                 kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
 166 }
 167
 168 static inline int copy_kernel_to_fxregs_err(struct fxregs_state *fx)
 169 {
 170         if (IS_ENABLED(CONFIG_X86_32))
 171                 return kernel_insn_err(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 172         else
 173                 return kernel_insn_err(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
 174 }
 175
 176 static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
 177 {
 178         if (IS_ENABLED(CONFIG_X86_32))
 179                 return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 180         else
 181                 return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
 182 }
 183
 184 static inline void copy_kernel_to_fregs(struct fregs_state *fx)
 185 {
 186         kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 187 }
 188
 189 static inline int copy_kernel_to_fregs_err(struct fregs_state *fx)
 190 {
 191         return kernel_insn_err(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 192 }
 193
 194 static inline int copy_user_to_fregs(struct fregs_state __user *fx)
 195 {
 196         return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
 197 }
 198
 199 static inline void copy_fxregs_to_kernel(struct fpu *fpu)
 200 {
 201         if (IS_ENABLED(CONFIG_X86_32))
 202                 asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
 203         else
 204                 asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
 205 }
 206
 207 static inline void fxsave(struct fxregs_state *fx)
 208 {
 209         if (IS_ENABLED(CONFIG_X86_32))
 210                 asm volatile( "fxsave %[fx]" : [fx] "=m" (*fx));
 211         else
 212                 asm volatile("fxsaveq %[fx]" : [fx] "=m" (*fx));
 213 }
 214
 215 /* These macros all use (%edi)/(%rdi) as the single memory argument. */
 216 #define XSAVE           ".byte " REX_PREFIX "0x0f,0xae,0x27"
 217 #define XSAVEOPT        ".byte " REX_PREFIX "0x0f,0xae,0x37"
 218 #define XSAVES          ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
 219 #define XRSTOR          ".byte " REX_PREFIX "0x0f,0xae,0x2f"
 220 #define XRSTORS         ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
 221
 222 #define XSTATE_OP(op, st, lmask, hmask, err)                            \
 223         asm volatile("1:" op "\n\t"                                     \
 224                      "xor %[err], %[err]\n"                             \
 225                      "2:\n\t"                                           \
 226                      ".pushsection .fixup,\"ax\"\n\t"                   \
 227                      "3: movl $-2,%[err]\n\t"                           \
 228                      "jmp 2b\n\t"                                       \
 229                      ".popsection\n\t"                                  \
 230                      _ASM_EXTABLE(1b, 3b)                               \
 231                      : [err] "=r" (err)                                 \
 232                      : "D" (st), "m" (*st), "a" (lmask), "d" (hmask)    \
 233                      : "memory")
 234
 235 /*
 236  * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
 237  * format and supervisor states in addition to modified optimization in
 238  * XSAVEOPT.
 239  *
 240  * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
 241  * supports modified optimization which is not supported by XSAVE.
 242  *
 243  * We use XSAVE as a fallback.
 244  *
 245  * The 661 label is defined in the ALTERNATIVE* macros as the address of the
 246  * original instruction which gets replaced. We need to use it here as the
 247  * address of the instruction where we might get an exception at.
 248  */
 249 #define XSTATE_XSAVE(st, lmask, hmask, err)                             \
 250         asm volatile(ALTERNATIVE_2(XSAVE,                               \
 251                                    XSAVEOPT, X86_FEATURE_XSAVEOPT,      \
 252                                    XSAVES,   X86_FEATURE_XSAVES)        \
 253                      "\n"                                               \
 254                      "xor %[err], %[err]\n"                             \
 255                      "3:\n"                                             \
 256                      ".pushsection .fixup,\"ax\"\n"                     \
 257                      "4: movl $-2, %[err]\n"                            \
 258                      "jmp 3b\n"                                         \
 259                      ".popsection\n"                                    \
 260                      _ASM_EXTABLE(661b, 4b)                             \
 261                      : [err] "=r" (err)                                 \
 262                      : "D" (st), "m" (*st), "a" (lmask), "d" (hmask)    \
 263                      : "memory")
 264
 265 /*
 266  * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
 267  * XSAVE area format.
 268  */
 269 #define XSTATE_XRESTORE(st, lmask, hmask)                               \
 270         asm volatile(ALTERNATIVE(XRSTOR,                                \
 271                                  XRSTORS, X86_FEATURE_XSAVES)           \
 272                      "\n"                                               \
 273                      "3:\n"                                             \
 274                      _ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\
 275                      :                                                  \
 276                      : "D" (st), "m" (*st), "a" (lmask), "d" (hmask)    \
 277                      : "memory")
 278
 279 /*
 280  * This function is called only during boot time when x86 caps are not set
 281  * up and alternative can not be used yet.
 282  */
 283 static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate)
 284 {
 285         u64 mask = -1;
 286         u32 lmask = mask;
 287         u32 hmask = mask >> 32;
 288         int err;
 289
 290         WARN_ON(system_state != SYSTEM_BOOTING);
 291
 292         if (boot_cpu_has(X86_FEATURE_XSAVES))
 293                 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
 294         else
 295                 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
 296
 297         /*
 298          * We should never fault when copying from a kernel buffer, and the FPU
 299          * state we set at boot time should be valid.
 300          */
 301         WARN_ON_FPU(err);
 302 }
 303
 304 /*
 305  * Save processor xstate to xsave area.
 306  */
 307 static inline void copy_xregs_to_kernel(struct xregs_state *xstate)
 308 {
 309         u64 mask = xfeatures_mask_all;
 310         u32 lmask = mask;
 311         u32 hmask = mask >> 32;
 312         int err;
 313
 314         WARN_ON_FPU(!alternatives_patched);
 315
 316         XSTATE_XSAVE(xstate, lmask, hmask, err);
 317
 318         /* We should never fault when copying to a kernel buffer: */
 319         WARN_ON_FPU(err);
 320 }
 321
 322 /*
 323  * Restore processor xstate from xsave area.
 324  */
 325 static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask)
 326 {
 327         u32 lmask = mask;
 328         u32 hmask = mask >> 32;
 329
 330         XSTATE_XRESTORE(xstate, lmask, hmask);
 331 }
 332
 333 /*
 334  * Save xstate to user space xsave area.
 335  *
 336  * We don't use modified optimization because xrstor/xrstors might track
 337  * a different application.
 338  *
 339  * We don't use compacted format xsave area for
 340  * backward compatibility for old applications which don't understand
 341  * compacted format of xsave area.
 342  */
 343 static inline int copy_xregs_to_user(struct xregs_state __user *buf)
 344 {
 345         u64 mask = xfeatures_mask_user();
 346         u32 lmask = mask;
 347         u32 hmask = mask >> 32;
 348         int err;
 349
 350         /*
 351          * Clear the xsave header first, so that reserved fields are
 352          * initialized to zero.
 353          */
 354         err = __clear_user(&buf->header, sizeof(buf->header));
 355         if (unlikely(err))
 356                 return -EFAULT;
 357
 358         stac();
 359         XSTATE_OP(XSAVE, buf, lmask, hmask, err);
 360         clac();
 361
 362         return err;
 363 }
 364
 365 /*
 366  * Restore xstate from user space xsave area.
 367  */
 368 static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask)
 369 {
 370         struct xregs_state *xstate = ((__force struct xregs_state *)buf);
 371         u32 lmask = mask;
 372         u32 hmask = mask >> 32;
 373         int err;
 374
 375         stac();
 376         XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
 377         clac();
 378
 379         return err;
 380 }
 381
 382 /*
 383  * Restore xstate from kernel space xsave area, return an error code instead of
 384  * an exception.
 385  */
 386 static inline int copy_kernel_to_xregs_err(struct xregs_state *xstate, u64 mask)
 387 {
 388         u32 lmask = mask;
 389         u32 hmask = mask >> 32;
 390         int err;
 391
 392         if (static_cpu_has(X86_FEATURE_XSAVES))
 393                 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
 394         else
 395                 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
 396
 397         return err;
 398 }
 399
 400 extern int copy_fpregs_to_fpstate(struct fpu *fpu);
 401
 402 static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask)
 403 {
 404         if (use_xsave()) {
 405                 copy_kernel_to_xregs(&fpstate->xsave, mask);
 406         } else {
 407                 if (use_fxsr())
 408                         copy_kernel_to_fxregs(&fpstate->fxsave);
 409                 else
 410                         copy_kernel_to_fregs(&fpstate->fsave);
 411         }
 412 }
 413
 414 static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
 415 {
 416         /*
 417          * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
 418          * pending. Clear the x87 state here by setting it to fixed values.
 419          * "m" is a random variable that should be in L1.
 420          */
 421         if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
 422                 asm volatile(
 423                         "fnclex\n\t"
 424                         "emms\n\t"
 425                         "fildl %P[addr]"        /* set F?P to defined value */
 426                         : : [addr] "m" (fpstate));
 427         }
 428
 429         __copy_kernel_to_fpregs(fpstate, -1);
 430 }
 431
 432 extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
 433
 434 /*
 435  * FPU context switch related helper methods:
 436  */
 437
 438 DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
 439
 440 /*
 441  * The in-register FPU state for an FPU context on a CPU is assumed to be
 442  * valid if the fpu->last_cpu matches the CPU, and the fpu_fpregs_owner_ctx
 443  * matches the FPU.
 444  *
 445  * If the FPU register state is valid, the kernel can skip restoring the
 446  * FPU state from memory.
 447  *
 448  * Any code that clobbers the FPU registers or updates the in-memory
 449  * FPU state for a task MUST let the rest of the kernel know that the
 450  * FPU registers are no longer valid for this task.
 451  *
 452  * Either one of these invalidation functions is enough. Invalidate
 453  * a resource you control: CPU if using the CPU for something else
 454  * (with preemption disabled), FPU for the current task, or a task that
 455  * is prevented from running by the current task.
 456  */
 457 static inline void __cpu_invalidate_fpregs_state(void)
 458 {
 459         __this_cpu_write(fpu_fpregs_owner_ctx, NULL);
 460 }
 461
 462 static inline void __fpu_invalidate_fpregs_state(struct fpu *fpu)
 463 {
 464         fpu->last_cpu = -1;
 465 }
 466
 467 static inline int fpregs_state_valid(struct fpu *fpu, unsigned int cpu)
 468 {
 469         return fpu == this_cpu_read(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
 470 }
 471
 472 /*
 473  * These generally need preemption protection to work,
 474  * do try to avoid using these on their own:
 475  */
 476 static inline void fpregs_deactivate(struct fpu *fpu)
 477 {
 478         this_cpu_write(fpu_fpregs_owner_ctx, NULL);
 479         trace_x86_fpu_regs_deactivated(fpu);
 480 }
 481
 482 static inline void fpregs_activate(struct fpu *fpu)
 483 {
 484         this_cpu_write(fpu_fpregs_owner_ctx, fpu);
 485         trace_x86_fpu_regs_activated(fpu);
 486 }
 487
 488 /*
 489  * Internal helper, do not use directly. Use switch_fpu_return() instead.
 490  */
 491 static inline void __fpregs_load_activate(void)
 492 {
 493         struct fpu *fpu = &current->thread.fpu;
 494         int cpu = smp_processor_id();
 495
 496         if (WARN_ON_ONCE(current->flags & PF_KTHREAD))
 497                 return;
 498
 499         if (!fpregs_state_valid(fpu, cpu)) {
 500                 copy_kernel_to_fpregs(&fpu->state);
 501                 fpregs_activate(fpu);
 502                 fpu->last_cpu = cpu;
 503         }
 504         clear_thread_flag(TIF_NEED_FPU_LOAD);
 505 }
 506
 507 /*
 508  * FPU state switching for scheduling.
 509  *
 510  * This is a two-stage process:
 511  *
 512  *  - switch_fpu_prepare() saves the old state.
 513  *    This is done within the context of the old process.
 514  *
 515  *  - switch_fpu_finish() sets TIF_NEED_FPU_LOAD; the floating point state
 516  *    will get loaded on return to userspace, or when the kernel needs it.
 517  *
 518  * If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers
 519  * are saved in the current thread's FPU register state.
 520  *
 521  * If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not
 522  * hold current()'s FPU registers. It is required to load the
 523  * registers before returning to userland or using the content
 524  * otherwise.
 525  *
 526  * The FPU context is only stored/restored for a user task and
 527  * PF_KTHREAD is used to distinguish between kernel and user threads.
 528  */
 529 static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu)
 530 {
 531         if (static_cpu_has(X86_FEATURE_FPU) && !(current->flags & PF_KTHREAD)) {
 532                 if (!copy_fpregs_to_fpstate(old_fpu))
 533                         old_fpu->last_cpu = -1;
 534                 else
 535                         old_fpu->last_cpu = cpu;
 536
 537                 /* But leave fpu_fpregs_owner_ctx! */
 538                 trace_x86_fpu_regs_deactivated(old_fpu);
 539         }
 540 }
 541
 542 /*
 543  * Misc helper functions:
 544  */
 545
 546 /*
 547  * Load PKRU from the FPU context if available. Delay loading of the
 548  * complete FPU state until the return to userland.
 549  */
 550 static inline void switch_fpu_finish(struct fpu *new_fpu)
 551 {
 552         u32 pkru_val = init_pkru_value;
 553         struct pkru_state *pk;
 554
 555         if (!static_cpu_has(X86_FEATURE_FPU))
 556                 return;
 557
 558         set_thread_flag(TIF_NEED_FPU_LOAD);
 559
 560         if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
 561                 return;
 562
 563         /*
 564          * PKRU state is switched eagerly because it needs to be valid before we
 565          * return to userland e.g. for a copy_to_user() operation.
 566          */
 567         if (!(current->flags & PF_KTHREAD)) {
 568                 /*
 569                  * If the PKRU bit in xsave.header.xfeatures is not set,
 570                  * then the PKRU component was in init state, which means
 571                  * XRSTOR will set PKRU to 0. If the bit is not set then
 572                  * get_xsave_addr() will return NULL because the PKRU value
 573                  * in memory is not valid. This means pkru_val has to be
 574                  * set to 0 and not to init_pkru_value.
 575                  */
 576                 pk = get_xsave_addr(&new_fpu->state.xsave, XFEATURE_PKRU);
 577                 pkru_val = pk ? pk->pkru : 0;
 578         }
 579         __write_pkru(pkru_val);
 580 }
 581
 582 #endif /* _ASM_X86_FPU_INTERNAL_H */