1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_BITOPS_H
3 #define _ASM_X86_BITOPS_H
6 * Copyright 1992, Linus Torvalds.
8 * Note: inlines with more than a single statement should be marked
9 * __always_inline to avoid problems with older gcc's inlining heuristics.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
16 #include <linux/compiler.h>
17 #include <asm/alternative.h>
18 #include <asm/rmwcc.h>
19 #include <asm/barrier.h>
21 #if BITS_PER_LONG == 32
22 # define _BITOPS_LONG_SHIFT 5
23 #elif BITS_PER_LONG == 64
24 # define _BITOPS_LONG_SHIFT 6
26 # error "Unexpected BITS_PER_LONG"
29 #define BIT_64(n) (U64_C(1) << (n))
32 * These have to be done with inline assembly: that way the bit-setting
33 * is guaranteed to be atomic. All bit operations return 0 if the bit
34 * was cleared before the operation and != 0 if it was not.
36 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
39 #define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
41 #define ADDR BITOP_ADDR(addr)
44 * We do the locked ops that don't return the old value as
45 * a mask operation on a byte.
47 #define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
48 #define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3))
49 #define CONST_MASK(nr) (1 << ((nr) & 7))
52 * set_bit - Atomically set a bit in memory
54 * @addr: the address to start counting from
56 * This function is atomic and may not be reordered. See __set_bit()
57 * if you do not require the atomic guarantees.
59 * Note: there are no guarantees that this function will not be reordered
60 * on non x86 architectures, so if you are writing portable code,
61 * make sure not to rely on its reordering guarantees.
63 * Note that @nr may be almost arbitrarily large; this function is not
64 * restricted to acting on a single-word quantity.
66 static __always_inline void
67 set_bit(long nr, volatile unsigned long *addr)
69 if (IS_IMMEDIATE(nr)) {
70 asm volatile(LOCK_PREFIX "orb %1,%0"
71 : CONST_MASK_ADDR(nr, addr)
72 : "iq" ((u8)CONST_MASK(nr))
75 asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
76 : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
81 * __set_bit - Set a bit in memory
83 * @addr: the address to start counting from
85 * Unlike set_bit(), this function is non-atomic and may be reordered.
86 * If it's called on the same region of memory simultaneously, the effect
87 * may be that only one operation succeeds.
89 static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
91 asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
95 * clear_bit - Clears a bit in memory
97 * @addr: Address to start counting from
99 * clear_bit() is atomic and may not be reordered. However, it does
100 * not contain a memory barrier, so if it is used for locking purposes,
101 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
102 * in order to ensure changes are visible on other processors.
104 static __always_inline void
105 clear_bit(long nr, volatile unsigned long *addr)
107 if (IS_IMMEDIATE(nr)) {
108 asm volatile(LOCK_PREFIX "andb %1,%0"
109 : CONST_MASK_ADDR(nr, addr)
110 : "iq" ((u8)~CONST_MASK(nr)));
112 asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
119 * clear_bit_unlock - Clears a bit in memory
121 * @addr: Address to start counting from
123 * clear_bit() is atomic and implies release semantics before the memory
124 * operation. It can be used for an unlock.
126 static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
132 static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
134 asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
137 static __always_inline bool clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
140 asm volatile(LOCK_PREFIX "andb %2,%1"
142 : CC_OUT(s) (negative), ADDR
143 : "ir" ((char) ~(1 << nr)) : "memory");
147 // Let everybody know we have it
148 #define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte
151 * __clear_bit_unlock - Clears a bit in memory
153 * @addr: Address to start counting from
155 * __clear_bit() is non-atomic and implies release semantics before the memory
156 * operation. It can be used for an unlock if no other CPUs can concurrently
157 * modify other bits in the word.
159 * No memory barrier is required here, because x86 cannot reorder stores past
160 * older loads. Same principle as spin_unlock.
162 static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
165 __clear_bit(nr, addr);
169 * __change_bit - Toggle a bit in memory
170 * @nr: the bit to change
171 * @addr: the address to start counting from
173 * Unlike change_bit(), this function is non-atomic and may be reordered.
174 * If it's called on the same region of memory simultaneously, the effect
175 * may be that only one operation succeeds.
177 static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
179 asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
183 * change_bit - Toggle a bit in memory
185 * @addr: Address to start counting from
187 * change_bit() is atomic and may not be reordered.
188 * Note that @nr may be almost arbitrarily large; this function is not
189 * restricted to acting on a single-word quantity.
191 static __always_inline void change_bit(long nr, volatile unsigned long *addr)
193 if (IS_IMMEDIATE(nr)) {
194 asm volatile(LOCK_PREFIX "xorb %1,%0"
195 : CONST_MASK_ADDR(nr, addr)
196 : "iq" ((u8)CONST_MASK(nr)));
198 asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
205 * test_and_set_bit - Set a bit and return its old value
207 * @addr: Address to count from
209 * This operation is atomic and cannot be reordered.
210 * It also implies a memory barrier.
212 static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
214 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr);
218 * test_and_set_bit_lock - Set a bit and return its old value for lock
220 * @addr: Address to count from
222 * This is the same as test_and_set_bit on x86.
224 static __always_inline bool
225 test_and_set_bit_lock(long nr, volatile unsigned long *addr)
227 return test_and_set_bit(nr, addr);
231 * __test_and_set_bit - Set a bit and return its old value
233 * @addr: Address to count from
235 * This operation is non-atomic and can be reordered.
236 * If two examples of this operation race, one can appear to succeed
237 * but actually fail. You must protect multiple accesses with a lock.
239 static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
243 asm(__ASM_SIZE(bts) " %2,%1"
245 : CC_OUT(c) (oldbit), ADDR
251 * test_and_clear_bit - Clear a bit and return its old value
253 * @addr: Address to count from
255 * This operation is atomic and cannot be reordered.
256 * It also implies a memory barrier.
258 static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
260 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr);
264 * __test_and_clear_bit - Clear a bit and return its old value
266 * @addr: Address to count from
268 * This operation is non-atomic and can be reordered.
269 * If two examples of this operation race, one can appear to succeed
270 * but actually fail. You must protect multiple accesses with a lock.
272 * Note: the operation is performed atomically with respect to
273 * the local CPU, but not other CPUs. Portable code should not
274 * rely on this behaviour.
275 * KVM relies on this behaviour on x86 for modifying memory that is also
276 * accessed from a hypervisor on the same CPU if running in a VM: don't change
277 * this without also updating arch/x86/kernel/kvm.c
279 static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
283 asm volatile(__ASM_SIZE(btr) " %2,%1"
285 : CC_OUT(c) (oldbit), ADDR
290 /* WARNING: non atomic and it can be reordered! */
291 static __always_inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
295 asm volatile(__ASM_SIZE(btc) " %2,%1"
297 : CC_OUT(c) (oldbit), ADDR
298 : "Ir" (nr) : "memory");
304 * test_and_change_bit - Change a bit and return its old value
306 * @addr: Address to count from
308 * This operation is atomic and cannot be reordered.
309 * It also implies a memory barrier.
311 static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
313 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr);
316 static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
318 return ((1UL << (nr & (BITS_PER_LONG-1))) &
319 (addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
322 static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr)
326 asm volatile(__ASM_SIZE(bt) " %2,%1"
329 : "m" (*(unsigned long *)addr), "Ir" (nr));
334 #if 0 /* Fool kernel-doc since it doesn't do macros yet */
336 * test_bit - Determine whether a bit is set
337 * @nr: bit number to test
338 * @addr: Address to start counting from
340 static bool test_bit(int nr, const volatile unsigned long *addr);
343 #define test_bit(nr, addr) \
344 (__builtin_constant_p((nr)) \
345 ? constant_test_bit((nr), (addr)) \
346 : variable_test_bit((nr), (addr)))
349 * __ffs - find first set bit in word
350 * @word: The word to search
352 * Undefined if no bit exists, so code should check against 0 first.
354 static __always_inline unsigned long __ffs(unsigned long word)
363 * ffz - find first zero bit in word
364 * @word: The word to search
366 * Undefined if no zero exists, so code should check against ~0UL first.
368 static __always_inline unsigned long ffz(unsigned long word)
377 * __fls: find last set bit in word
378 * @word: The word to search
380 * Undefined if no set bit exists, so code should check against 0 first.
382 static __always_inline unsigned long __fls(unsigned long word)
394 * ffs - find first set bit in word
395 * @x: the word to search
397 * This is defined the same way as the libc and compiler builtin ffs
398 * routines, therefore differs in spirit from the other bitops.
400 * ffs(value) returns 0 if value is 0 or the position of the first
401 * set bit if value is nonzero. The first (least significant) bit
404 static __always_inline int ffs(int x)
410 * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
411 * dest reg is undefined if x==0, but their CPU architect says its
412 * value is written to set it to the same as before, except that the
413 * top 32 bits will be cleared.
415 * We cannot do this on 32 bits because at the very least some
416 * 486 CPUs did not behave this way.
420 : "rm" (x), "0" (-1));
421 #elif defined(CONFIG_X86_CMOV)
424 : "=&r" (r) : "rm" (x), "r" (-1));
429 "1:" : "=r" (r) : "rm" (x));
435 * fls - find last set bit in word
436 * @x: the word to search
438 * This is defined in a similar way as the libc and compiler builtin
439 * ffs, but returns the position of the most significant set bit.
441 * fls(value) returns 0 if value is 0 or the position of the last
442 * set bit if value is nonzero. The last (most significant) bit is
445 static __always_inline int fls(unsigned int x)
451 * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
452 * dest reg is undefined if x==0, but their CPU architect says its
453 * value is written to set it to the same as before, except that the
454 * top 32 bits will be cleared.
456 * We cannot do this on 32 bits because at the very least some
457 * 486 CPUs did not behave this way.
461 : "rm" (x), "0" (-1));
462 #elif defined(CONFIG_X86_CMOV)
465 : "=&r" (r) : "rm" (x), "rm" (-1));
470 "1:" : "=r" (r) : "rm" (x));
476 * fls64 - find last set bit in a 64-bit word
477 * @x: the word to search
479 * This is defined in a similar way as the libc and compiler builtin
480 * ffsll, but returns the position of the most significant set bit.
482 * fls64(value) returns 0 if value is 0 or the position of the last
483 * set bit if value is nonzero. The last (most significant) bit is
487 static __always_inline int fls64(__u64 x)
491 * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
492 * dest reg is undefined if x==0, but their CPU architect says its
493 * value is written to set it to the same as before.
501 #include <asm-generic/bitops/fls64.h>
504 #include <asm-generic/bitops/find.h>
506 #include <asm-generic/bitops/sched.h>
508 #include <asm/arch_hweight.h>
510 #include <asm-generic/bitops/const_hweight.h>
512 #include <asm-generic/bitops/le.h>
514 #include <asm-generic/bitops/ext2-atomic-setbit.h>
516 #endif /* __KERNEL__ */
517 #endif /* _ASM_X86_BITOPS_H */