1 /* SPDX-License-Identifier: GPL-2.0 */
3 * From PPR Vol 1 for AMD Family 19h Model 01h B1
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include <asm/msr-index.h>
13 /* MSR 0xc0011030: IBS Fetch Control */
17 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
18 fetch_cnt:16, /* 16-31: instruction fetch count */
19 fetch_lat:16, /* 32-47: instruction fetch latency */
20 fetch_en:1, /* 48: instruction fetch enable */
21 fetch_val:1, /* 49: instruction fetch valid */
22 fetch_comp:1, /* 50: instruction fetch complete */
23 ic_miss:1, /* 51: i-cache miss */
24 phy_addr_valid:1,/* 52: physical address valid */
25 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
26 * (needs IbsPhyAddrValid) */
27 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
28 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
29 rand_en:1, /* 57: random tagging enable */
30 fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
31 * (needs IbsFetchComp) */
32 reserved:5; /* 59-63: reserved */
36 /* MSR 0xc0011033: IBS Execution Control */
40 __u64 opmaxcnt:16, /* 0-15: periodic op max. count */
41 reserved0:1, /* 16: reserved */
42 op_en:1, /* 17: op sampling enable */
43 op_val:1, /* 18: op sample valid */
44 cnt_ctl:1, /* 19: periodic op counter control */
45 opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
46 reserved1:5, /* 27-31: reserved */
47 opcurcnt:27, /* 32-58: periodic op counter current count */
48 reserved2:5; /* 59-63: reserved */
52 /* MSR 0xc0011035: IBS Op Data 2 */
56 __u64 comp_to_ret_ctr:16, /* 0-15: op completion to retire count */
57 tag_to_ret_ctr:16, /* 15-31: op tag to retire count */
58 reserved1:2, /* 32-33: reserved */
59 op_return:1, /* 34: return op */
60 op_brn_taken:1, /* 35: taken branch op */
61 op_brn_misp:1, /* 36: mispredicted branch op */
62 op_brn_ret:1, /* 37: branch op retired */
63 op_rip_invalid:1, /* 38: RIP is invalid */
64 op_brn_fuse:1, /* 39: fused branch op */
65 op_microcode:1, /* 40: microcode op */
66 reserved2:23; /* 41-63: reserved */
70 /* MSR 0xc0011036: IBS Op Data 2 */
74 __u64 data_src:3, /* 0-2: data source */
75 reserved0:1, /* 3: reserved */
76 rmt_node:1, /* 4: destination node */
77 cache_hit_st:1, /* 5: cache hit state */
78 reserved1:57; /* 5-63: reserved */
82 /* MSR 0xc0011037: IBS Op Data 3 */
86 __u64 ld_op:1, /* 0: load op */
87 st_op:1, /* 1: store op */
88 dc_l1tlb_miss:1, /* 2: data cache L1TLB miss */
89 dc_l2tlb_miss:1, /* 3: data cache L2TLB hit in 2M page */
90 dc_l1tlb_hit_2m:1, /* 4: data cache L1TLB hit in 2M page */
91 dc_l1tlb_hit_1g:1, /* 5: data cache L1TLB hit in 1G page */
92 dc_l2tlb_hit_2m:1, /* 6: data cache L2TLB hit in 2M page */
93 dc_miss:1, /* 7: data cache miss */
94 dc_mis_acc:1, /* 8: misaligned access */
95 reserved:4, /* 9-12: reserved */
96 dc_wc_mem_acc:1, /* 13: write combining memory access */
97 dc_uc_mem_acc:1, /* 14: uncacheable memory access */
98 dc_locked_op:1, /* 15: locked operation */
99 dc_miss_no_mab_alloc:1, /* 16: DC miss with no MAB allocated */
100 dc_lin_addr_valid:1, /* 17: data cache linear address valid */
101 dc_phy_addr_valid:1, /* 18: data cache physical address valid */
102 dc_l2_tlb_hit_1g:1, /* 19: data cache L2 hit in 1GB page */
103 l2_miss:1, /* 20: L2 cache miss */
104 sw_pf:1, /* 21: software prefetch */
105 op_mem_width:4, /* 22-25: load/store size in bytes */
106 op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */
107 dc_miss_lat:16, /* 32-47: data cache miss latency */
108 tlb_refill_lat:16; /* 48-63: L1 TLB refill latency */
112 /* MSR 0xc001103c: IBS Fetch Control Extended */
113 union ic_ibs_extd_ctl {
116 __u64 itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */
117 reserved:48; /* 16-63: reserved */
125 struct perf_ibs_data {
128 u32 data[0]; /* data buffer starts here */
131 u64 regs[MSR_AMD64_IBS_REG_COUNT_MAX];