arch/x86/hyperv/hv_apic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /*
   4  * Hyper-V specific APIC code.
   5  *
   6  * Copyright (C) 2018, Microsoft, Inc.
   7  *
   8  * Author : K. Y. Srinivasan <kys@microsoft.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  17  * NON INFRINGEMENT.  See the GNU General Public License for more
  18  * details.
  19  *
  20  */
  21
  22 #include <linux/types.h>
  23 #include <linux/vmalloc.h>
  24 #include <linux/mm.h>
  25 #include <linux/clockchips.h>
  26 #include <linux/hyperv.h>
  27 #include <linux/slab.h>
  28 #include <linux/cpuhotplug.h>
  29 #include <asm/hypervisor.h>
  30 #include <asm/mshyperv.h>
  31 #include <asm/apic.h>
  32
  33 #include <asm/trace/hyperv.h>
  34
  35 static struct apic orig_apic;
  36
  37 static u64 hv_apic_icr_read(void)
  38 {
  39         u64 reg_val;
  40
  41         rdmsrl(HV_X64_MSR_ICR, reg_val);
  42         return reg_val;
  43 }
  44
  45 static void hv_apic_icr_write(u32 low, u32 id)
  46 {
  47         u64 reg_val;
  48
  49         reg_val = SET_APIC_DEST_FIELD(id);
  50         reg_val = reg_val << 32;
  51         reg_val |= low;
  52
  53         wrmsrl(HV_X64_MSR_ICR, reg_val);
  54 }
  55
  56 static u32 hv_apic_read(u32 reg)
  57 {
  58         u32 reg_val, hi;
  59
  60         switch (reg) {
  61         case APIC_EOI:
  62                 rdmsr(HV_X64_MSR_EOI, reg_val, hi);
  63                 (void)hi;
  64                 return reg_val;
  65         case APIC_TASKPRI:
  66                 rdmsr(HV_X64_MSR_TPR, reg_val, hi);
  67                 (void)hi;
  68                 return reg_val;
  69
  70         default:
  71                 return native_apic_mem_read(reg);
  72         }
  73 }
  74
  75 static void hv_apic_write(u32 reg, u32 val)
  76 {
  77         switch (reg) {
  78         case APIC_EOI:
  79                 wrmsr(HV_X64_MSR_EOI, val, 0);
  80                 break;
  81         case APIC_TASKPRI:
  82                 wrmsr(HV_X64_MSR_TPR, val, 0);
  83                 break;
  84         default:
  85                 native_apic_mem_write(reg, val);
  86         }
  87 }
  88
  89 static void hv_apic_eoi_write(u32 reg, u32 val)
  90 {
  91         struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
  92
  93         if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
  94                 return;
  95
  96         wrmsr(HV_X64_MSR_EOI, val, 0);
  97 }
  98
  99 /*
 100  * IPI implementation on Hyper-V.
 101  */
 102 static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
 103 {
 104         struct hv_send_ipi_ex **arg;
 105         struct hv_send_ipi_ex *ipi_arg;
 106         unsigned long flags;
 107         int nr_bank = 0;
 108         u64 status = HV_STATUS_INVALID_PARAMETER;
 109
 110         if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
 111                 return false;
 112
 113         local_irq_save(flags);
 114         arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
 115
 116         ipi_arg = *arg;
 117         if (unlikely(!ipi_arg))
 118                 goto ipi_mask_ex_done;
 119
 120         ipi_arg->vector = vector;
 121         ipi_arg->reserved = 0;
 122         ipi_arg->vp_set.valid_bank_mask = 0;
 123
 124         if (!cpumask_equal(mask, cpu_present_mask)) {
 125                 ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
 126                 nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
 127         }
 128         if (nr_bank < 0)
 129                 goto ipi_mask_ex_done;
 130         if (!nr_bank)
 131                 ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
 132
 133         status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
 134                               ipi_arg, NULL);
 135
 136 ipi_mask_ex_done:
 137         local_irq_restore(flags);
 138         return hv_result_success(status);
 139 }
 140
 141 static bool __send_ipi_mask(const struct cpumask *mask, int vector)
 142 {
 143         int cur_cpu, vcpu;
 144         struct hv_send_ipi ipi_arg;
 145         u64 status;
 146
 147         trace_hyperv_send_ipi_mask(mask, vector);
 148
 149         if (cpumask_empty(mask))
 150                 return true;
 151
 152         if (!hv_hypercall_pg)
 153                 return false;
 154
 155         if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
 156                 return false;
 157
 158         /*
 159          * From the supplied CPU set we need to figure out if we can get away
 160          * with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
 161          * highest VP number in the set is < 64. As VP numbers are usually in
 162          * ascending order and match Linux CPU ids, here is an optimization:
 163          * we check the VP number for the highest bit in the supplied set first
 164          * so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
 165          * a must. We will also check all VP numbers when walking the supplied
 166          * CPU set to remain correct in all cases.
 167          */
 168         if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
 169                 goto do_ex_hypercall;
 170
 171         ipi_arg.vector = vector;
 172         ipi_arg.cpu_mask = 0;
 173
 174         for_each_cpu(cur_cpu, mask) {
 175                 vcpu = hv_cpu_number_to_vp_number(cur_cpu);
 176                 if (vcpu == VP_INVAL)
 177                         return false;
 178
 179                 /*
 180                  * This particular version of the IPI hypercall can
 181                  * only target upto 64 CPUs.
 182                  */
 183                 if (vcpu >= 64)
 184                         goto do_ex_hypercall;
 185
 186                 __set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
 187         }
 188
 189         status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
 190                                      ipi_arg.cpu_mask);
 191         return hv_result_success(status);
 192
 193 do_ex_hypercall:
 194         return __send_ipi_mask_ex(mask, vector);
 195 }
 196
 197 static bool __send_ipi_one(int cpu, int vector)
 198 {
 199         int vp = hv_cpu_number_to_vp_number(cpu);
 200         u64 status;
 201
 202         trace_hyperv_send_ipi_one(cpu, vector);
 203
 204         if (!hv_hypercall_pg || (vp == VP_INVAL))
 205                 return false;
 206
 207         if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
 208                 return false;
 209
 210         if (vp >= 64)
 211                 return __send_ipi_mask_ex(cpumask_of(cpu), vector);
 212
 213         status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
 214         return hv_result_success(status);
 215 }
 216
 217 static void hv_send_ipi(int cpu, int vector)
 218 {
 219         if (!__send_ipi_one(cpu, vector))
 220                 orig_apic.send_IPI(cpu, vector);
 221 }
 222
 223 static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
 224 {
 225         if (!__send_ipi_mask(mask, vector))
 226                 orig_apic.send_IPI_mask(mask, vector);
 227 }
 228
 229 static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
 230 {
 231         unsigned int this_cpu = smp_processor_id();
 232         struct cpumask new_mask;
 233         const struct cpumask *local_mask;
 234
 235         cpumask_copy(&new_mask, mask);
 236         cpumask_clear_cpu(this_cpu, &new_mask);
 237         local_mask = &new_mask;
 238         if (!__send_ipi_mask(local_mask, vector))
 239                 orig_apic.send_IPI_mask_allbutself(mask, vector);
 240 }
 241
 242 static void hv_send_ipi_allbutself(int vector)
 243 {
 244         hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
 245 }
 246
 247 static void hv_send_ipi_all(int vector)
 248 {
 249         if (!__send_ipi_mask(cpu_online_mask, vector))
 250                 orig_apic.send_IPI_all(vector);
 251 }
 252
 253 static void hv_send_ipi_self(int vector)
 254 {
 255         if (!__send_ipi_one(smp_processor_id(), vector))
 256                 orig_apic.send_IPI_self(vector);
 257 }
 258
 259 void __init hv_apic_init(void)
 260 {
 261         if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
 262                 pr_info("Hyper-V: Using IPI hypercalls\n");
 263                 /*
 264                  * Set the IPI entry points.
 265                  */
 266                 orig_apic = *apic;
 267
 268                 apic->send_IPI = hv_send_ipi;
 269                 apic->send_IPI_mask = hv_send_ipi_mask;
 270                 apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
 271                 apic->send_IPI_allbutself = hv_send_ipi_allbutself;
 272                 apic->send_IPI_all = hv_send_ipi_all;
 273                 apic->send_IPI_self = hv_send_ipi_self;
 274         }
 275
 276         if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
 277                 pr_info("Hyper-V: Using enlightened APIC (%s mode)",
 278                         x2apic_enabled() ? "x2apic" : "xapic");
 279                 /*
 280                  * When in x2apic mode, don't use the Hyper-V specific APIC
 281                  * accessors since the field layout in the ICR register is
 282                  * different in x2apic mode. Furthermore, the architectural
 283                  * x2apic MSRs function just as well as the Hyper-V
 284                  * synthetic APIC MSRs, so there's no benefit in having
 285                  * separate Hyper-V accessors for x2apic mode. The only
 286                  * exception is hv_apic_eoi_write, because it benefits from
 287                  * lazy EOI when available, but the same accessor works for
 288                  * both xapic and x2apic because the field layout is the same.
 289                  */
 290                 apic_set_eoi_write(hv_apic_eoi_write);
 291                 if (!x2apic_enabled()) {
 292                         apic->read      = hv_apic_read;
 293                         apic->write     = hv_apic_write;
 294                         apic->icr_write = hv_apic_icr_write;
 295                         apic->icr_read  = hv_apic_icr_read;
 296                 }
 297         }
 298 }