2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
17 #include <asm/intel_ds.h>
19 /* To enable MSR tracing please use the generic trace points. */
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
36 EXTRA_REG_NONE = -1, /* not used */
38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
40 EXTRA_REG_LBR = 2, /* lbr_select */
41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
42 EXTRA_REG_FE = 4, /* fe_* */
44 EXTRA_REG_MAX /* number of entries needed */
47 struct event_constraint {
49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
60 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
62 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */
72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */
73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */
74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */
75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */
76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */
77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */
78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */
79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */
80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */
81 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */
82 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */
83 #define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */
85 static inline bool is_topdown_count(struct perf_event *event)
87 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
90 static inline bool is_metric_event(struct perf_event *event)
92 u64 config = event->attr.config;
94 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
95 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
96 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
99 static inline bool is_slots_event(struct perf_event *event)
101 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
104 static inline bool is_topdown_event(struct perf_event *event)
106 return is_metric_event(event) || is_slots_event(event);
110 int nb_id; /* NorthBridge id */
111 int refcnt; /* reference count */
112 struct perf_event *owners[X86_PMC_IDX_MAX];
113 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
116 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
117 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
118 #define PEBS_OUTPUT_OFFSET 61
119 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
120 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
121 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
124 * Flags PEBS can handle without an PMI.
126 * TID can only be handled by flushing at context switch.
127 * REGS_USER can be handled for events limited to ring 3.
130 #define LARGE_PEBS_FLAGS \
131 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
132 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
133 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
134 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
135 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
136 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
138 #define PEBS_GP_REGS \
139 ((1ULL << PERF_REG_X86_AX) | \
140 (1ULL << PERF_REG_X86_BX) | \
141 (1ULL << PERF_REG_X86_CX) | \
142 (1ULL << PERF_REG_X86_DX) | \
143 (1ULL << PERF_REG_X86_DI) | \
144 (1ULL << PERF_REG_X86_SI) | \
145 (1ULL << PERF_REG_X86_SP) | \
146 (1ULL << PERF_REG_X86_BP) | \
147 (1ULL << PERF_REG_X86_IP) | \
148 (1ULL << PERF_REG_X86_FLAGS) | \
149 (1ULL << PERF_REG_X86_R8) | \
150 (1ULL << PERF_REG_X86_R9) | \
151 (1ULL << PERF_REG_X86_R10) | \
152 (1ULL << PERF_REG_X86_R11) | \
153 (1ULL << PERF_REG_X86_R12) | \
154 (1ULL << PERF_REG_X86_R13) | \
155 (1ULL << PERF_REG_X86_R14) | \
156 (1ULL << PERF_REG_X86_R15))
159 * Per register state.
162 raw_spinlock_t lock; /* per-core: protect structure */
163 u64 config; /* extra MSR config */
164 u64 reg; /* extra MSR number */
165 atomic_t ref; /* reference count */
171 * Used to coordinate shared registers between HT threads or
172 * among events on a single PMU.
174 struct intel_shared_regs {
175 struct er_account regs[EXTRA_REG_MAX];
176 int refcnt; /* per-core: #HT threads */
177 unsigned core_id; /* per-core: core id */
180 enum intel_excl_state_type {
181 INTEL_EXCL_UNUSED = 0, /* counter is unused */
182 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
183 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
186 struct intel_excl_states {
187 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
188 bool sched_started; /* true if scheduling has started */
191 struct intel_excl_cntrs {
194 struct intel_excl_states states[2];
197 u16 has_exclusive[2];
198 u32 exclusive_present;
201 int refcnt; /* per-core: #HT threads */
202 unsigned core_id; /* per-core: core id */
205 struct x86_perf_task_context;
206 #define MAX_LBR_ENTRIES 32
209 LBR_FORMAT_32 = 0x00,
210 LBR_FORMAT_LIP = 0x01,
211 LBR_FORMAT_EIP = 0x02,
212 LBR_FORMAT_EIP_FLAGS = 0x03,
213 LBR_FORMAT_EIP_FLAGS2 = 0x04,
214 LBR_FORMAT_INFO = 0x05,
215 LBR_FORMAT_TIME = 0x06,
216 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
220 X86_PERF_KFREE_SHARED = 0,
221 X86_PERF_KFREE_EXCL = 1,
225 struct cpu_hw_events {
227 * Generic x86 PMC bits
229 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
230 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
231 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
234 int n_events; /* the # of events in the below arrays */
235 int n_added; /* the # last events in the below arrays;
236 they've never been enabled yet */
237 int n_txn; /* the # last events in the below arrays;
238 added in the current transaction */
241 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
242 u64 tags[X86_PMC_IDX_MAX];
244 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
245 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
247 int n_excl; /* the number of exclusive events */
249 unsigned int txn_flags;
253 * Intel DebugStore bits
255 struct debug_store *ds;
264 /* Current super set of events hardware configuration */
266 u64 active_pebs_data_cfg;
267 int pebs_record_size;
274 struct perf_branch_stack lbr_stack;
275 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
277 struct er_account *lbr_sel;
278 struct er_account *lbr_ctl;
287 * Intel host/guest exclude bits
289 u64 intel_ctrl_guest_mask;
290 u64 intel_ctrl_host_mask;
291 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
294 * Intel checkpoint mask
299 * manage shared (per-core, per-cpu) registers
300 * used on Intel NHM/WSM/SNB
302 struct intel_shared_regs *shared_regs;
304 * manage exclusive counter access between hyperthread
306 struct event_constraint *constraint_list; /* in enable order */
307 struct intel_excl_cntrs *excl_cntrs;
308 int excl_thread_id; /* 0 or 1 */
311 * SKL TSX_FORCE_ABORT shadow
318 /* number of accepted metrics events */
324 struct amd_nb *amd_nb;
325 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
326 u64 perf_ctr_virt_mask;
327 int n_pair; /* Large increment events */
329 void *kfree_on_online[X86_PERF_KFREE_MAX];
332 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
333 { .idxmsk64 = (n) }, \
342 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
343 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
345 #define EVENT_CONSTRAINT(c, n, m) \
346 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
349 * The constraint_match() function only works for 'simple' event codes
350 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
352 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
353 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
355 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
356 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
357 0, PERF_X86_EVENT_EXCL)
360 * The overlap flag marks event constraints with overlapping counter
361 * masks. This is the case if the counter mask of such an event is not
362 * a subset of any other counter mask of a constraint with an equal or
363 * higher weight, e.g.:
365 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
366 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
367 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
369 * The event scheduler may not select the correct counter in the first
370 * cycle because it needs to know which subsequent events will be
371 * scheduled. It may fail to schedule the events then. So we set the
372 * overlap flag for such constraints to give the scheduler a hint which
373 * events to select for counter rescheduling.
375 * Care must be taken as the rescheduling algorithm is O(n!) which
376 * will increase scheduling cycles for an over-committed system
377 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
378 * and its counter masks must be kept at a minimum.
380 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
381 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
384 * Constraint on the Event code.
386 #define INTEL_EVENT_CONSTRAINT(c, n) \
387 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
390 * Constraint on a range of Event codes
392 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
393 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
396 * Constraint on the Event code + UMask + fixed-mask
398 * filter mask to validate fixed counter events.
399 * the following filters disqualify for fixed counters:
404 * - in_tx_checkpointed
405 * The other filters are supported by fixed counters.
406 * The any-thread option is supported starting with v3.
408 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
409 #define FIXED_EVENT_CONSTRAINT(c, n) \
410 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
413 * The special metric counters do not actually exist. They are calculated from
414 * the combination of the FxCtr3 + MSR_PERF_METRICS.
416 * The special metric counters are mapped to a dummy offset for the scheduler.
417 * The sharing between multiple users of the same metric without multiplexing
418 * is not allowed, even though the hardware supports that in principle.
421 #define METRIC_EVENT_CONSTRAINT(c, n) \
422 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
423 INTEL_ARCH_EVENT_MASK)
426 * Constraint on the Event code + UMask
428 #define INTEL_UEVENT_CONSTRAINT(c, n) \
429 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
431 /* Constraint on specific umask bit only + event */
432 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
433 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
435 /* Like UEVENT_CONSTRAINT, but match flags too */
436 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
437 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
439 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
440 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
441 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
443 #define INTEL_PLD_CONSTRAINT(c, n) \
444 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
445 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
447 #define INTEL_PSD_CONSTRAINT(c, n) \
448 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
449 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
451 #define INTEL_PST_CONSTRAINT(c, n) \
452 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
453 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
455 /* Event constraint, but match on all event flags too. */
456 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
457 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
459 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
460 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
462 /* Check only flags, but allow all event/umask */
463 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
464 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
466 /* Check flags and event code, and set the HSW store flag */
467 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
468 __EVENT_CONSTRAINT(code, n, \
469 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
470 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
472 /* Check flags and event code, and set the HSW load flag */
473 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
474 __EVENT_CONSTRAINT(code, n, \
475 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
476 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
478 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
479 __EVENT_CONSTRAINT_RANGE(code, end, n, \
480 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
481 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
483 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
484 __EVENT_CONSTRAINT(code, n, \
485 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
487 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
489 /* Check flags and event code/umask, and set the HSW store flag */
490 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
491 __EVENT_CONSTRAINT(code, n, \
492 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
493 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
495 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
496 __EVENT_CONSTRAINT(code, n, \
497 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
499 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
501 /* Check flags and event code/umask, and set the HSW load flag */
502 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
503 __EVENT_CONSTRAINT(code, n, \
504 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
505 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
507 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
508 __EVENT_CONSTRAINT(code, n, \
509 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
511 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
513 /* Check flags and event code/umask, and set the HSW N/A flag */
514 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
515 __EVENT_CONSTRAINT(code, n, \
516 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
517 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
521 * We define the end marker as having a weight of -1
522 * to enable blacklisting of events using a counter bitmask
523 * of zero and thus a weight of zero.
524 * The end marker has a weight that cannot possibly be
525 * obtained from counting the bits in the bitmask.
527 #define EVENT_CONSTRAINT_END { .weight = -1 }
530 * Check for end marker with weight == -1
532 #define for_each_event_constraint(e, c) \
533 for ((e) = (c); (e)->weight != -1; (e)++)
536 * Extra registers for specific events.
538 * Some events need large masks and require external MSRs.
539 * Those extra MSRs end up being shared for all events on
540 * a PMU and sometimes between PMU of sibling HT threads.
541 * In either case, the kernel needs to handle conflicting
542 * accesses to those extra, shared, regs. The data structure
543 * to manage those registers is stored in cpu_hw_event.
550 int idx; /* per_xxx->regs[] reg index */
551 bool extra_msr_access;
554 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
557 .config_mask = (m), \
558 .valid_mask = (vm), \
559 .idx = EXTRA_REG_##i, \
560 .extra_msr_access = true, \
563 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
564 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
566 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
567 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
568 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
570 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
571 INTEL_UEVENT_EXTRA_REG(c, \
572 MSR_PEBS_LD_LAT_THRESHOLD, \
576 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
578 union perf_capabilities {
586 * PMU supports separate counter range for writing
589 u64 full_width_write:1;
592 u64 pebs_output_pt_available:1;
593 u64 anythread_deprecated:1;
598 struct x86_pmu_quirk {
599 struct x86_pmu_quirk *next;
603 union x86_pmu_config {
624 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
627 x86_lbr_exclusive_lbr,
628 x86_lbr_exclusive_bts,
629 x86_lbr_exclusive_pt,
630 x86_lbr_exclusive_max,
634 * struct x86_pmu - generic x86 pmu
638 * Generic x86 PMC bits
642 int (*handle_irq)(struct pt_regs *);
643 void (*disable_all)(void);
644 void (*enable_all)(int added);
645 void (*enable)(struct perf_event *);
646 void (*disable)(struct perf_event *);
647 void (*add)(struct perf_event *);
648 void (*del)(struct perf_event *);
649 void (*read)(struct perf_event *event);
650 int (*hw_config)(struct perf_event *event);
651 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
654 int (*addr_offset)(int index, bool eventsel);
655 int (*rdpmc_index)(int index);
656 u64 (*event_map)(int);
659 int num_counters_fixed;
663 unsigned long events_maskl;
664 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
669 struct event_constraint *
670 (*get_event_constraints)(struct cpu_hw_events *cpuc,
672 struct perf_event *event);
674 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
675 struct perf_event *event);
677 void (*start_scheduling)(struct cpu_hw_events *cpuc);
679 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
681 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
683 struct event_constraint *event_constraints;
684 struct x86_pmu_quirk *quirks;
685 int perfctr_second_write;
686 u64 (*limit_period)(struct perf_event *event, u64 l);
688 /* PMI handler bits */
689 unsigned int late_ack :1,
694 int attr_rdpmc_broken;
696 struct attribute **format_attrs;
698 ssize_t (*events_sysfs_show)(char *page, u64 config);
699 const struct attribute_group **attr_update;
701 unsigned long attr_freeze_on_smi;
706 int (*cpu_prepare)(int cpu);
707 void (*cpu_starting)(int cpu);
708 void (*cpu_dying)(int cpu);
709 void (*cpu_dead)(int cpu);
711 void (*check_microcode)(void);
712 void (*sched_task)(struct perf_event_context *ctx,
716 * Intel Arch Perfmon v2+
719 union perf_capabilities intel_cap;
722 * Intel DebugStore bits
731 pebs_no_isolation :1,
733 int pebs_record_size;
734 int pebs_buffer_size;
736 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
737 struct event_constraint *pebs_constraints;
738 void (*pebs_aliases)(struct perf_event *event);
739 unsigned long large_pebs_flags;
745 unsigned int lbr_tos, lbr_from, lbr_to,
746 lbr_info, lbr_nr; /* LBR base regs and size */
748 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
749 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
752 const int *lbr_sel_map; /* lbr_select mappings */
753 int *lbr_ctl_map; /* LBR_CTL mappings */
755 bool lbr_double_abort; /* duplicated lbr aborts */
756 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
759 * Intel Architectural LBR CPUID Enumeration
761 unsigned int lbr_depth_mask:8;
762 unsigned int lbr_deep_c_reset:1;
763 unsigned int lbr_lip:1;
764 unsigned int lbr_cpl:1;
765 unsigned int lbr_filter:1;
766 unsigned int lbr_call_stack:1;
767 unsigned int lbr_mispred:1;
768 unsigned int lbr_timed_lbr:1;
769 unsigned int lbr_br_type:1;
771 void (*lbr_reset)(void);
772 void (*lbr_read)(struct cpu_hw_events *cpuc);
773 void (*lbr_save)(void *ctx);
774 void (*lbr_restore)(void *ctx);
777 * Intel PT/LBR/BTS are exclusive
779 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
784 int num_topdown_events;
785 u64 (*update_topdown_event)(struct perf_event *event);
786 int (*set_topdown_event_period)(struct perf_event *event);
789 * perf task context (i.e. struct perf_event_context::task_ctx_data)
790 * switch helper to bridge calls from perf/core to perf/x86.
791 * See struct pmu::swap_task_ctx() usage for examples;
793 void (*swap_task_ctx)(struct perf_event_context *prev,
794 struct perf_event_context *next);
799 unsigned int amd_nb_constraints : 1;
800 u64 perf_ctr_pair_en;
803 * Extra registers for events
805 struct extra_reg *extra_regs;
809 * Intel host/guest support (KVM)
811 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
814 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
816 int (*check_period) (struct perf_event *event, u64 period);
818 int (*aux_output_match) (struct perf_event *event);
821 struct x86_perf_task_context_opt {
822 int lbr_callstack_users;
827 struct x86_perf_task_context {
831 struct x86_perf_task_context_opt opt;
832 struct lbr_entry lbr[MAX_LBR_ENTRIES];
835 struct x86_perf_task_context_arch_lbr {
836 struct x86_perf_task_context_opt opt;
837 struct lbr_entry entries[];
841 * Add padding to guarantee the 64-byte alignment of the state buffer.
843 * The structure is dynamically allocated. The size of the LBR state may vary
844 * based on the number of LBR registers.
846 * Do not put anything after the LBR state.
848 struct x86_perf_task_context_arch_lbr_xsave {
849 struct x86_perf_task_context_opt opt;
852 struct xregs_state xsave;
854 struct fxregs_state i387;
855 struct xstate_header header;
856 struct arch_lbr_state lbr;
857 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
861 #define x86_add_quirk(func_) \
863 static struct x86_pmu_quirk __quirk __initdata = { \
866 __quirk.next = x86_pmu.quirks; \
867 x86_pmu.quirks = &__quirk; \
873 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
874 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
875 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
876 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
877 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
878 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
879 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
880 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
881 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
883 #define EVENT_VAR(_id) event_attr_##_id
884 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
886 #define EVENT_ATTR(_name, _id) \
887 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
888 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
889 .id = PERF_COUNT_HW_##_id, \
893 #define EVENT_ATTR_STR(_name, v, str) \
894 static struct perf_pmu_events_attr event_attr_##v = { \
895 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
900 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
901 static struct perf_pmu_events_ht_attr event_attr_##v = { \
902 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
904 .event_str_noht = noht, \
905 .event_str_ht = ht, \
908 struct pmu *x86_get_pmu(void);
909 extern struct x86_pmu x86_pmu __read_mostly;
911 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
913 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
914 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
916 return &((struct x86_perf_task_context *)ctx)->opt;
919 static inline bool x86_pmu_has_lbr_callstack(void)
921 return x86_pmu.lbr_sel_map &&
922 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
925 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
927 int x86_perf_event_set_period(struct perf_event *event);
930 * Generalized hw caching related hw_event table, filled
931 * in on a per model basis. A value of 0 means
932 * 'not supported', -1 means 'hw_event makes no sense on
933 * this CPU', any other value means the raw hw_event
937 #define C(x) PERF_COUNT_HW_CACHE_##x
939 extern u64 __read_mostly hw_cache_event_ids
940 [PERF_COUNT_HW_CACHE_MAX]
941 [PERF_COUNT_HW_CACHE_OP_MAX]
942 [PERF_COUNT_HW_CACHE_RESULT_MAX];
943 extern u64 __read_mostly hw_cache_extra_regs
944 [PERF_COUNT_HW_CACHE_MAX]
945 [PERF_COUNT_HW_CACHE_OP_MAX]
946 [PERF_COUNT_HW_CACHE_RESULT_MAX];
948 u64 x86_perf_event_update(struct perf_event *event);
950 static inline unsigned int x86_pmu_config_addr(int index)
952 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
953 x86_pmu.addr_offset(index, true) : index);
956 static inline unsigned int x86_pmu_event_addr(int index)
958 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
959 x86_pmu.addr_offset(index, false) : index);
962 static inline int x86_pmu_rdpmc_index(int index)
964 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
967 int x86_add_exclusive(unsigned int what);
969 void x86_del_exclusive(unsigned int what);
971 int x86_reserve_hardware(void);
973 void x86_release_hardware(void);
975 int x86_pmu_max_precise(void);
977 void hw_perf_lbr_event_destroy(struct perf_event *event);
979 int x86_setup_perfctr(struct perf_event *event);
981 int x86_pmu_hw_config(struct perf_event *event);
983 void x86_pmu_disable_all(void);
985 static inline bool is_counter_pair(struct hw_perf_event *hwc)
987 return hwc->flags & PERF_X86_EVENT_PAIR;
990 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
993 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
995 if (hwc->extra_reg.reg)
996 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
999 * Add enabled Merge event on next counter
1000 * if large increment event being enabled on this counter
1002 if (is_counter_pair(hwc))
1003 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1005 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1008 void x86_pmu_enable_all(int added);
1010 int perf_assign_events(struct event_constraint **constraints, int n,
1011 int wmin, int wmax, int gpmax, int *assign);
1012 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1014 void x86_pmu_stop(struct perf_event *event, int flags);
1016 static inline void x86_pmu_disable_event(struct perf_event *event)
1018 struct hw_perf_event *hwc = &event->hw;
1020 wrmsrl(hwc->config_base, hwc->config);
1022 if (is_counter_pair(hwc))
1023 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
1026 void x86_pmu_enable_event(struct perf_event *event);
1028 int x86_pmu_handle_irq(struct pt_regs *regs);
1030 extern struct event_constraint emptyconstraint;
1032 extern struct event_constraint unconstrained;
1034 static inline bool kernel_ip(unsigned long ip)
1036 #ifdef CONFIG_X86_32
1037 return ip > PAGE_OFFSET;
1039 return (long)ip < 0;
1044 * Not all PMUs provide the right context information to place the reported IP
1045 * into full context. Specifically segment registers are typically not
1048 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1049 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1052 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1053 * much we can do about that but pray and treat it like a linear address.
1055 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1057 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1058 if (regs->flags & X86_VM_MASK)
1059 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1063 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1064 ssize_t intel_event_sysfs_show(char *page, u64 config);
1066 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1068 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1071 static inline bool fixed_counter_disabled(int i)
1073 return !(x86_pmu.intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));
1076 #ifdef CONFIG_CPU_SUP_AMD
1078 int amd_pmu_init(void);
1080 #else /* CONFIG_CPU_SUP_AMD */
1082 static inline int amd_pmu_init(void)
1087 #endif /* CONFIG_CPU_SUP_AMD */
1089 static inline int is_pebs_pt(struct perf_event *event)
1091 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1094 #ifdef CONFIG_CPU_SUP_INTEL
1096 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1098 struct hw_perf_event *hwc = &event->hw;
1099 unsigned int hw_event, bts_event;
1101 if (event->attr.freq)
1104 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1105 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1107 return hw_event == bts_event && period == 1;
1110 static inline bool intel_pmu_has_bts(struct perf_event *event)
1112 struct hw_perf_event *hwc = &event->hw;
1114 return intel_pmu_has_bts_period(event, hwc->sample_period);
1117 int intel_pmu_save_and_restart(struct perf_event *event);
1119 struct event_constraint *
1120 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1121 struct perf_event *event);
1123 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1124 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1126 int intel_pmu_init(void);
1128 void init_debug_store_on_cpu(int cpu);
1130 void fini_debug_store_on_cpu(int cpu);
1132 void release_ds_buffers(void);
1134 void reserve_ds_buffers(void);
1136 void release_lbr_buffers(void);
1138 extern struct event_constraint bts_constraint;
1139 extern struct event_constraint vlbr_constraint;
1141 void intel_pmu_enable_bts(u64 config);
1143 void intel_pmu_disable_bts(void);
1145 int intel_pmu_drain_bts_buffer(void);
1147 extern struct event_constraint intel_core2_pebs_event_constraints[];
1149 extern struct event_constraint intel_atom_pebs_event_constraints[];
1151 extern struct event_constraint intel_slm_pebs_event_constraints[];
1153 extern struct event_constraint intel_glm_pebs_event_constraints[];
1155 extern struct event_constraint intel_glp_pebs_event_constraints[];
1157 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1159 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1161 extern struct event_constraint intel_snb_pebs_event_constraints[];
1163 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1165 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1167 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1169 extern struct event_constraint intel_skl_pebs_event_constraints[];
1171 extern struct event_constraint intel_icl_pebs_event_constraints[];
1173 extern struct event_constraint intel_spr_pebs_event_constraints[];
1175 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1177 void intel_pmu_pebs_add(struct perf_event *event);
1179 void intel_pmu_pebs_del(struct perf_event *event);
1181 void intel_pmu_pebs_enable(struct perf_event *event);
1183 void intel_pmu_pebs_disable(struct perf_event *event);
1185 void intel_pmu_pebs_enable_all(void);
1187 void intel_pmu_pebs_disable_all(void);
1189 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1191 void intel_pmu_auto_reload_read(struct perf_event *event);
1193 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1195 void intel_ds_init(void);
1197 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
1198 struct perf_event_context *next);
1200 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1202 u64 lbr_from_signext_quirk_wr(u64 val);
1204 void intel_pmu_lbr_reset(void);
1206 void intel_pmu_lbr_reset_32(void);
1208 void intel_pmu_lbr_reset_64(void);
1210 void intel_pmu_lbr_add(struct perf_event *event);
1212 void intel_pmu_lbr_del(struct perf_event *event);
1214 void intel_pmu_lbr_enable_all(bool pmi);
1216 void intel_pmu_lbr_disable_all(void);
1218 void intel_pmu_lbr_read(void);
1220 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1222 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1224 void intel_pmu_lbr_save(void *ctx);
1226 void intel_pmu_lbr_restore(void *ctx);
1228 void intel_pmu_lbr_init_core(void);
1230 void intel_pmu_lbr_init_nhm(void);
1232 void intel_pmu_lbr_init_atom(void);
1234 void intel_pmu_lbr_init_slm(void);
1236 void intel_pmu_lbr_init_snb(void);
1238 void intel_pmu_lbr_init_hsw(void);
1240 void intel_pmu_lbr_init_skl(void);
1242 void intel_pmu_lbr_init_knl(void);
1244 void intel_pmu_arch_lbr_init(void);
1246 void intel_pmu_pebs_data_source_nhm(void);
1248 void intel_pmu_pebs_data_source_skl(bool pmem);
1250 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1252 void intel_pt_interrupt(void);
1254 int intel_bts_interrupt(void);
1256 void intel_bts_enable_local(void);
1258 void intel_bts_disable_local(void);
1260 int p4_pmu_init(void);
1262 int p6_pmu_init(void);
1264 int knc_pmu_init(void);
1266 static inline int is_ht_workaround_enabled(void)
1268 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1271 #else /* CONFIG_CPU_SUP_INTEL */
1273 static inline void reserve_ds_buffers(void)
1277 static inline void release_ds_buffers(void)
1281 static inline void release_lbr_buffers(void)
1285 static inline int intel_pmu_init(void)
1290 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1295 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1299 static inline int is_ht_workaround_enabled(void)
1303 #endif /* CONFIG_CPU_SUP_INTEL */
1305 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1306 int zhaoxin_pmu_init(void);
1308 static inline int zhaoxin_pmu_init(void)
1312 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/