2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
17 #include <asm/intel_ds.h>
19 /* To enable MSR tracing please use the generic trace points. */
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
36 EXTRA_REG_NONE = -1, /* not used */
38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
40 EXTRA_REG_LBR = 2, /* lbr_select */
41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
42 EXTRA_REG_FE = 4, /* fe_* */
44 EXTRA_REG_MAX /* number of entries needed */
47 struct event_constraint {
49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
60 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
62 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */
72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */
73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */
74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */
75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */
76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */
77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */
78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */
79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */
80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */
81 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */
84 int nb_id; /* NorthBridge id */
85 int refcnt; /* reference count */
86 struct perf_event *owners[X86_PMC_IDX_MAX];
87 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
90 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
91 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
92 #define PEBS_OUTPUT_OFFSET 61
93 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
94 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
95 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
98 * Flags PEBS can handle without an PMI.
100 * TID can only be handled by flushing at context switch.
101 * REGS_USER can be handled for events limited to ring 3.
104 #define LARGE_PEBS_FLAGS \
105 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
106 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
107 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
108 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
109 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
112 #define PEBS_GP_REGS \
113 ((1ULL << PERF_REG_X86_AX) | \
114 (1ULL << PERF_REG_X86_BX) | \
115 (1ULL << PERF_REG_X86_CX) | \
116 (1ULL << PERF_REG_X86_DX) | \
117 (1ULL << PERF_REG_X86_DI) | \
118 (1ULL << PERF_REG_X86_SI) | \
119 (1ULL << PERF_REG_X86_SP) | \
120 (1ULL << PERF_REG_X86_BP) | \
121 (1ULL << PERF_REG_X86_IP) | \
122 (1ULL << PERF_REG_X86_FLAGS) | \
123 (1ULL << PERF_REG_X86_R8) | \
124 (1ULL << PERF_REG_X86_R9) | \
125 (1ULL << PERF_REG_X86_R10) | \
126 (1ULL << PERF_REG_X86_R11) | \
127 (1ULL << PERF_REG_X86_R12) | \
128 (1ULL << PERF_REG_X86_R13) | \
129 (1ULL << PERF_REG_X86_R14) | \
130 (1ULL << PERF_REG_X86_R15))
133 * Per register state.
136 raw_spinlock_t lock; /* per-core: protect structure */
137 u64 config; /* extra MSR config */
138 u64 reg; /* extra MSR number */
139 atomic_t ref; /* reference count */
145 * Used to coordinate shared registers between HT threads or
146 * among events on a single PMU.
148 struct intel_shared_regs {
149 struct er_account regs[EXTRA_REG_MAX];
150 int refcnt; /* per-core: #HT threads */
151 unsigned core_id; /* per-core: core id */
154 enum intel_excl_state_type {
155 INTEL_EXCL_UNUSED = 0, /* counter is unused */
156 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
157 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
160 struct intel_excl_states {
161 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
162 bool sched_started; /* true if scheduling has started */
165 struct intel_excl_cntrs {
168 struct intel_excl_states states[2];
171 u16 has_exclusive[2];
172 u32 exclusive_present;
175 int refcnt; /* per-core: #HT threads */
176 unsigned core_id; /* per-core: core id */
179 struct x86_perf_task_context;
180 #define MAX_LBR_ENTRIES 32
183 LBR_FORMAT_32 = 0x00,
184 LBR_FORMAT_LIP = 0x01,
185 LBR_FORMAT_EIP = 0x02,
186 LBR_FORMAT_EIP_FLAGS = 0x03,
187 LBR_FORMAT_EIP_FLAGS2 = 0x04,
188 LBR_FORMAT_INFO = 0x05,
189 LBR_FORMAT_TIME = 0x06,
190 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
194 X86_PERF_KFREE_SHARED = 0,
195 X86_PERF_KFREE_EXCL = 1,
199 struct cpu_hw_events {
201 * Generic x86 PMC bits
203 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
204 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
205 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
208 int n_events; /* the # of events in the below arrays */
209 int n_added; /* the # last events in the below arrays;
210 they've never been enabled yet */
211 int n_txn; /* the # last events in the below arrays;
212 added in the current transaction */
213 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
214 u64 tags[X86_PMC_IDX_MAX];
216 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
217 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
219 int n_excl; /* the number of exclusive events */
221 unsigned int txn_flags;
225 * Intel DebugStore bits
227 struct debug_store *ds;
236 /* Current super set of events hardware configuration */
238 u64 active_pebs_data_cfg;
239 int pebs_record_size;
246 struct perf_branch_stack lbr_stack;
247 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
249 struct er_account *lbr_sel;
250 struct er_account *lbr_ctl;
259 * Intel host/guest exclude bits
261 u64 intel_ctrl_guest_mask;
262 u64 intel_ctrl_host_mask;
263 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
266 * Intel checkpoint mask
271 * manage shared (per-core, per-cpu) registers
272 * used on Intel NHM/WSM/SNB
274 struct intel_shared_regs *shared_regs;
276 * manage exclusive counter access between hyperthread
278 struct event_constraint *constraint_list; /* in enable order */
279 struct intel_excl_cntrs *excl_cntrs;
280 int excl_thread_id; /* 0 or 1 */
283 * SKL TSX_FORCE_ABORT shadow
290 struct amd_nb *amd_nb;
291 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
292 u64 perf_ctr_virt_mask;
293 int n_pair; /* Large increment events */
295 void *kfree_on_online[X86_PERF_KFREE_MAX];
298 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
299 { .idxmsk64 = (n) }, \
308 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
309 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
311 #define EVENT_CONSTRAINT(c, n, m) \
312 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
315 * The constraint_match() function only works for 'simple' event codes
316 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
318 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
319 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
321 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
322 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
323 0, PERF_X86_EVENT_EXCL)
326 * The overlap flag marks event constraints with overlapping counter
327 * masks. This is the case if the counter mask of such an event is not
328 * a subset of any other counter mask of a constraint with an equal or
329 * higher weight, e.g.:
331 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
332 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
333 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
335 * The event scheduler may not select the correct counter in the first
336 * cycle because it needs to know which subsequent events will be
337 * scheduled. It may fail to schedule the events then. So we set the
338 * overlap flag for such constraints to give the scheduler a hint which
339 * events to select for counter rescheduling.
341 * Care must be taken as the rescheduling algorithm is O(n!) which
342 * will increase scheduling cycles for an over-committed system
343 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
344 * and its counter masks must be kept at a minimum.
346 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
347 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
350 * Constraint on the Event code.
352 #define INTEL_EVENT_CONSTRAINT(c, n) \
353 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
356 * Constraint on a range of Event codes
358 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
359 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
362 * Constraint on the Event code + UMask + fixed-mask
364 * filter mask to validate fixed counter events.
365 * the following filters disqualify for fixed counters:
370 * - in_tx_checkpointed
371 * The other filters are supported by fixed counters.
372 * The any-thread option is supported starting with v3.
374 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
375 #define FIXED_EVENT_CONSTRAINT(c, n) \
376 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
379 * Constraint on the Event code + UMask
381 #define INTEL_UEVENT_CONSTRAINT(c, n) \
382 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
384 /* Constraint on specific umask bit only + event */
385 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
386 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
388 /* Like UEVENT_CONSTRAINT, but match flags too */
389 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
390 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
392 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
393 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
394 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
396 #define INTEL_PLD_CONSTRAINT(c, n) \
397 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
398 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
400 #define INTEL_PST_CONSTRAINT(c, n) \
401 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
402 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
404 /* Event constraint, but match on all event flags too. */
405 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
406 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
408 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
409 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
411 /* Check only flags, but allow all event/umask */
412 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
413 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
415 /* Check flags and event code, and set the HSW store flag */
416 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
417 __EVENT_CONSTRAINT(code, n, \
418 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
419 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
421 /* Check flags and event code, and set the HSW load flag */
422 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
423 __EVENT_CONSTRAINT(code, n, \
424 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
425 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
427 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
428 __EVENT_CONSTRAINT_RANGE(code, end, n, \
429 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
430 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
432 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
433 __EVENT_CONSTRAINT(code, n, \
434 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
436 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
438 /* Check flags and event code/umask, and set the HSW store flag */
439 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
440 __EVENT_CONSTRAINT(code, n, \
441 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
442 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
444 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
445 __EVENT_CONSTRAINT(code, n, \
446 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
448 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
450 /* Check flags and event code/umask, and set the HSW load flag */
451 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
452 __EVENT_CONSTRAINT(code, n, \
453 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
454 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
456 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
457 __EVENT_CONSTRAINT(code, n, \
458 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
460 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
462 /* Check flags and event code/umask, and set the HSW N/A flag */
463 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
464 __EVENT_CONSTRAINT(code, n, \
465 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
466 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
470 * We define the end marker as having a weight of -1
471 * to enable blacklisting of events using a counter bitmask
472 * of zero and thus a weight of zero.
473 * The end marker has a weight that cannot possibly be
474 * obtained from counting the bits in the bitmask.
476 #define EVENT_CONSTRAINT_END { .weight = -1 }
479 * Check for end marker with weight == -1
481 #define for_each_event_constraint(e, c) \
482 for ((e) = (c); (e)->weight != -1; (e)++)
485 * Extra registers for specific events.
487 * Some events need large masks and require external MSRs.
488 * Those extra MSRs end up being shared for all events on
489 * a PMU and sometimes between PMU of sibling HT threads.
490 * In either case, the kernel needs to handle conflicting
491 * accesses to those extra, shared, regs. The data structure
492 * to manage those registers is stored in cpu_hw_event.
499 int idx; /* per_xxx->regs[] reg index */
500 bool extra_msr_access;
503 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
506 .config_mask = (m), \
507 .valid_mask = (vm), \
508 .idx = EXTRA_REG_##i, \
509 .extra_msr_access = true, \
512 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
513 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
515 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
516 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
517 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
519 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
520 INTEL_UEVENT_EXTRA_REG(c, \
521 MSR_PEBS_LD_LAT_THRESHOLD, \
525 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
527 union perf_capabilities {
535 * PMU supports separate counter range for writing
538 u64 full_width_write:1;
540 u64 pebs_metrics_available:1;
541 u64 pebs_output_pt_available:1;
546 struct x86_pmu_quirk {
547 struct x86_pmu_quirk *next;
551 union x86_pmu_config {
572 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
575 x86_lbr_exclusive_lbr,
576 x86_lbr_exclusive_bts,
577 x86_lbr_exclusive_pt,
578 x86_lbr_exclusive_max,
582 * struct x86_pmu - generic x86 pmu
586 * Generic x86 PMC bits
590 int (*handle_irq)(struct pt_regs *);
591 void (*disable_all)(void);
592 void (*enable_all)(int added);
593 void (*enable)(struct perf_event *);
594 void (*disable)(struct perf_event *);
595 void (*add)(struct perf_event *);
596 void (*del)(struct perf_event *);
597 void (*read)(struct perf_event *event);
598 int (*hw_config)(struct perf_event *event);
599 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
602 int (*addr_offset)(int index, bool eventsel);
603 int (*rdpmc_index)(int index);
604 u64 (*event_map)(int);
607 int num_counters_fixed;
611 unsigned long events_maskl;
612 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
617 struct event_constraint *
618 (*get_event_constraints)(struct cpu_hw_events *cpuc,
620 struct perf_event *event);
622 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
623 struct perf_event *event);
625 void (*start_scheduling)(struct cpu_hw_events *cpuc);
627 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
629 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
631 struct event_constraint *event_constraints;
632 struct x86_pmu_quirk *quirks;
633 int perfctr_second_write;
634 u64 (*limit_period)(struct perf_event *event, u64 l);
636 /* PMI handler bits */
637 unsigned int late_ack :1,
643 int attr_rdpmc_broken;
645 struct attribute **format_attrs;
647 ssize_t (*events_sysfs_show)(char *page, u64 config);
648 const struct attribute_group **attr_update;
650 unsigned long attr_freeze_on_smi;
655 int (*cpu_prepare)(int cpu);
656 void (*cpu_starting)(int cpu);
657 void (*cpu_dying)(int cpu);
658 void (*cpu_dead)(int cpu);
660 void (*check_microcode)(void);
661 void (*sched_task)(struct perf_event_context *ctx,
665 * Intel Arch Perfmon v2+
668 union perf_capabilities intel_cap;
671 * Intel DebugStore bits
680 pebs_no_isolation :1;
681 int pebs_record_size;
682 int pebs_buffer_size;
684 void (*drain_pebs)(struct pt_regs *regs);
685 struct event_constraint *pebs_constraints;
686 void (*pebs_aliases)(struct perf_event *event);
687 unsigned long large_pebs_flags;
693 unsigned int lbr_tos, lbr_from, lbr_to,
694 lbr_info, lbr_nr; /* LBR base regs and size */
696 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
697 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
700 const int *lbr_sel_map; /* lbr_select mappings */
701 int *lbr_ctl_map; /* LBR_CTL mappings */
703 bool lbr_double_abort; /* duplicated lbr aborts */
704 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
707 * Intel Architectural LBR CPUID Enumeration
709 unsigned int lbr_depth_mask:8;
710 unsigned int lbr_deep_c_reset:1;
711 unsigned int lbr_lip:1;
712 unsigned int lbr_cpl:1;
713 unsigned int lbr_filter:1;
714 unsigned int lbr_call_stack:1;
715 unsigned int lbr_mispred:1;
716 unsigned int lbr_timed_lbr:1;
717 unsigned int lbr_br_type:1;
719 void (*lbr_reset)(void);
720 void (*lbr_read)(struct cpu_hw_events *cpuc);
721 void (*lbr_save)(void *ctx);
722 void (*lbr_restore)(void *ctx);
725 * Intel PT/LBR/BTS are exclusive
727 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
730 * perf task context (i.e. struct perf_event_context::task_ctx_data)
731 * switch helper to bridge calls from perf/core to perf/x86.
732 * See struct pmu::swap_task_ctx() usage for examples;
734 void (*swap_task_ctx)(struct perf_event_context *prev,
735 struct perf_event_context *next);
740 unsigned int amd_nb_constraints : 1;
741 u64 perf_ctr_pair_en;
744 * Extra registers for events
746 struct extra_reg *extra_regs;
750 * Intel host/guest support (KVM)
752 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
755 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
757 int (*check_period) (struct perf_event *event, u64 period);
759 int (*aux_output_match) (struct perf_event *event);
762 struct x86_perf_task_context_opt {
763 int lbr_callstack_users;
768 struct x86_perf_task_context {
772 struct x86_perf_task_context_opt opt;
773 struct lbr_entry lbr[MAX_LBR_ENTRIES];
776 struct x86_perf_task_context_arch_lbr {
777 struct x86_perf_task_context_opt opt;
778 struct lbr_entry entries[];
782 * Add padding to guarantee the 64-byte alignment of the state buffer.
784 * The structure is dynamically allocated. The size of the LBR state may vary
785 * based on the number of LBR registers.
787 * Do not put anything after the LBR state.
789 struct x86_perf_task_context_arch_lbr_xsave {
790 struct x86_perf_task_context_opt opt;
793 struct xregs_state xsave;
795 struct fxregs_state i387;
796 struct xstate_header header;
797 struct arch_lbr_state lbr;
798 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
802 #define x86_add_quirk(func_) \
804 static struct x86_pmu_quirk __quirk __initdata = { \
807 __quirk.next = x86_pmu.quirks; \
808 x86_pmu.quirks = &__quirk; \
814 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
815 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
816 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
817 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
818 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
819 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
820 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
822 #define EVENT_VAR(_id) event_attr_##_id
823 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
825 #define EVENT_ATTR(_name, _id) \
826 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
827 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
828 .id = PERF_COUNT_HW_##_id, \
832 #define EVENT_ATTR_STR(_name, v, str) \
833 static struct perf_pmu_events_attr event_attr_##v = { \
834 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
839 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
840 static struct perf_pmu_events_ht_attr event_attr_##v = { \
841 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
843 .event_str_noht = noht, \
844 .event_str_ht = ht, \
847 struct pmu *x86_get_pmu(void);
848 extern struct x86_pmu x86_pmu __read_mostly;
850 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
852 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
853 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
855 return &((struct x86_perf_task_context *)ctx)->opt;
858 static inline bool x86_pmu_has_lbr_callstack(void)
860 return x86_pmu.lbr_sel_map &&
861 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
864 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
866 int x86_perf_event_set_period(struct perf_event *event);
869 * Generalized hw caching related hw_event table, filled
870 * in on a per model basis. A value of 0 means
871 * 'not supported', -1 means 'hw_event makes no sense on
872 * this CPU', any other value means the raw hw_event
876 #define C(x) PERF_COUNT_HW_CACHE_##x
878 extern u64 __read_mostly hw_cache_event_ids
879 [PERF_COUNT_HW_CACHE_MAX]
880 [PERF_COUNT_HW_CACHE_OP_MAX]
881 [PERF_COUNT_HW_CACHE_RESULT_MAX];
882 extern u64 __read_mostly hw_cache_extra_regs
883 [PERF_COUNT_HW_CACHE_MAX]
884 [PERF_COUNT_HW_CACHE_OP_MAX]
885 [PERF_COUNT_HW_CACHE_RESULT_MAX];
887 u64 x86_perf_event_update(struct perf_event *event);
889 static inline unsigned int x86_pmu_config_addr(int index)
891 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
892 x86_pmu.addr_offset(index, true) : index);
895 static inline unsigned int x86_pmu_event_addr(int index)
897 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
898 x86_pmu.addr_offset(index, false) : index);
901 static inline int x86_pmu_rdpmc_index(int index)
903 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
906 int x86_add_exclusive(unsigned int what);
908 void x86_del_exclusive(unsigned int what);
910 int x86_reserve_hardware(void);
912 void x86_release_hardware(void);
914 int x86_pmu_max_precise(void);
916 void hw_perf_lbr_event_destroy(struct perf_event *event);
918 int x86_setup_perfctr(struct perf_event *event);
920 int x86_pmu_hw_config(struct perf_event *event);
922 void x86_pmu_disable_all(void);
924 static inline bool is_counter_pair(struct hw_perf_event *hwc)
926 return hwc->flags & PERF_X86_EVENT_PAIR;
929 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
932 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
934 if (hwc->extra_reg.reg)
935 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
938 * Add enabled Merge event on next counter
939 * if large increment event being enabled on this counter
941 if (is_counter_pair(hwc))
942 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
944 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
947 void x86_pmu_enable_all(int added);
949 int perf_assign_events(struct event_constraint **constraints, int n,
950 int wmin, int wmax, int gpmax, int *assign);
951 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
953 void x86_pmu_stop(struct perf_event *event, int flags);
955 static inline void x86_pmu_disable_event(struct perf_event *event)
957 struct hw_perf_event *hwc = &event->hw;
959 wrmsrl(hwc->config_base, hwc->config);
961 if (is_counter_pair(hwc))
962 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
965 void x86_pmu_enable_event(struct perf_event *event);
967 int x86_pmu_handle_irq(struct pt_regs *regs);
969 extern struct event_constraint emptyconstraint;
971 extern struct event_constraint unconstrained;
973 static inline bool kernel_ip(unsigned long ip)
976 return ip > PAGE_OFFSET;
983 * Not all PMUs provide the right context information to place the reported IP
984 * into full context. Specifically segment registers are typically not
987 * Assuming the address is a linear address (it is for IBS), we fake the CS and
988 * vm86 mode using the known zero-based code segment and 'fix up' the registers
991 * Intel PEBS/LBR appear to typically provide the effective address, nothing
992 * much we can do about that but pray and treat it like a linear address.
994 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
996 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
997 if (regs->flags & X86_VM_MASK)
998 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1002 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1003 ssize_t intel_event_sysfs_show(char *page, u64 config);
1005 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1007 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1010 #ifdef CONFIG_CPU_SUP_AMD
1012 int amd_pmu_init(void);
1014 #else /* CONFIG_CPU_SUP_AMD */
1016 static inline int amd_pmu_init(void)
1021 #endif /* CONFIG_CPU_SUP_AMD */
1023 static inline int is_pebs_pt(struct perf_event *event)
1025 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1028 #ifdef CONFIG_CPU_SUP_INTEL
1030 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1032 struct hw_perf_event *hwc = &event->hw;
1033 unsigned int hw_event, bts_event;
1035 if (event->attr.freq)
1038 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1039 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1041 return hw_event == bts_event && period == 1;
1044 static inline bool intel_pmu_has_bts(struct perf_event *event)
1046 struct hw_perf_event *hwc = &event->hw;
1048 return intel_pmu_has_bts_period(event, hwc->sample_period);
1051 int intel_pmu_save_and_restart(struct perf_event *event);
1053 struct event_constraint *
1054 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1055 struct perf_event *event);
1057 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1058 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1060 int intel_pmu_init(void);
1062 void init_debug_store_on_cpu(int cpu);
1064 void fini_debug_store_on_cpu(int cpu);
1066 void release_ds_buffers(void);
1068 void reserve_ds_buffers(void);
1070 void release_lbr_buffers(void);
1072 extern struct event_constraint bts_constraint;
1073 extern struct event_constraint vlbr_constraint;
1075 void intel_pmu_enable_bts(u64 config);
1077 void intel_pmu_disable_bts(void);
1079 int intel_pmu_drain_bts_buffer(void);
1081 extern struct event_constraint intel_core2_pebs_event_constraints[];
1083 extern struct event_constraint intel_atom_pebs_event_constraints[];
1085 extern struct event_constraint intel_slm_pebs_event_constraints[];
1087 extern struct event_constraint intel_glm_pebs_event_constraints[];
1089 extern struct event_constraint intel_glp_pebs_event_constraints[];
1091 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1093 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1095 extern struct event_constraint intel_snb_pebs_event_constraints[];
1097 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1099 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1101 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1103 extern struct event_constraint intel_skl_pebs_event_constraints[];
1105 extern struct event_constraint intel_icl_pebs_event_constraints[];
1107 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1109 void intel_pmu_pebs_add(struct perf_event *event);
1111 void intel_pmu_pebs_del(struct perf_event *event);
1113 void intel_pmu_pebs_enable(struct perf_event *event);
1115 void intel_pmu_pebs_disable(struct perf_event *event);
1117 void intel_pmu_pebs_enable_all(void);
1119 void intel_pmu_pebs_disable_all(void);
1121 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1123 void intel_pmu_auto_reload_read(struct perf_event *event);
1125 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1127 void intel_ds_init(void);
1129 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
1130 struct perf_event_context *next);
1132 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1134 u64 lbr_from_signext_quirk_wr(u64 val);
1136 void intel_pmu_lbr_reset(void);
1138 void intel_pmu_lbr_reset_32(void);
1140 void intel_pmu_lbr_reset_64(void);
1142 void intel_pmu_lbr_add(struct perf_event *event);
1144 void intel_pmu_lbr_del(struct perf_event *event);
1146 void intel_pmu_lbr_enable_all(bool pmi);
1148 void intel_pmu_lbr_disable_all(void);
1150 void intel_pmu_lbr_read(void);
1152 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1154 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1156 void intel_pmu_lbr_save(void *ctx);
1158 void intel_pmu_lbr_restore(void *ctx);
1160 void intel_pmu_lbr_init_core(void);
1162 void intel_pmu_lbr_init_nhm(void);
1164 void intel_pmu_lbr_init_atom(void);
1166 void intel_pmu_lbr_init_slm(void);
1168 void intel_pmu_lbr_init_snb(void);
1170 void intel_pmu_lbr_init_hsw(void);
1172 void intel_pmu_lbr_init_skl(void);
1174 void intel_pmu_lbr_init_knl(void);
1176 void intel_pmu_arch_lbr_init(void);
1178 void intel_pmu_pebs_data_source_nhm(void);
1180 void intel_pmu_pebs_data_source_skl(bool pmem);
1182 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1184 void intel_pt_interrupt(void);
1186 int intel_bts_interrupt(void);
1188 void intel_bts_enable_local(void);
1190 void intel_bts_disable_local(void);
1192 int p4_pmu_init(void);
1194 int p6_pmu_init(void);
1196 int knc_pmu_init(void);
1198 static inline int is_ht_workaround_enabled(void)
1200 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1203 #else /* CONFIG_CPU_SUP_INTEL */
1205 static inline void reserve_ds_buffers(void)
1209 static inline void release_ds_buffers(void)
1213 static inline void release_lbr_buffers(void)
1217 static inline int intel_pmu_init(void)
1222 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1227 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1231 static inline int is_ht_workaround_enabled(void)
1235 #endif /* CONFIG_CPU_SUP_INTEL */
1237 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1238 int zhaoxin_pmu_init(void);
1240 static inline int zhaoxin_pmu_init(void)
1244 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/