2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
17 #include <asm/intel_ds.h>
19 /* To enable MSR tracing please use the generic trace points. */
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
36 EXTRA_REG_NONE = -1, /* not used */
38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
40 EXTRA_REG_LBR = 2, /* lbr_select */
41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
42 EXTRA_REG_FE = 4, /* fe_* */
44 EXTRA_REG_MAX /* number of entries needed */
47 struct event_constraint {
49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
60 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
62 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */
72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */
73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */
74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */
75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */
76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */
77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */
78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */
79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */
80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */
81 #define PERF_X86_EVENT_LBR_SELECT 0x2000 /* Save/Restore MSR_LBR_SELECT */
82 #define PERF_X86_EVENT_TOPDOWN 0x4000 /* Count Topdown slots/metrics events */
83 #define PERF_X86_EVENT_PEBS_STLAT 0x8000 /* st+stlat data address sampling */
85 static inline bool is_topdown_count(struct perf_event *event)
87 return event->hw.flags & PERF_X86_EVENT_TOPDOWN;
90 static inline bool is_metric_event(struct perf_event *event)
92 u64 config = event->attr.config;
94 return ((config & ARCH_PERFMON_EVENTSEL_EVENT) == 0) &&
95 ((config & INTEL_ARCH_EVENT_MASK) >= INTEL_TD_METRIC_RETIRING) &&
96 ((config & INTEL_ARCH_EVENT_MASK) <= INTEL_TD_METRIC_MAX);
99 static inline bool is_slots_event(struct perf_event *event)
101 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_TD_SLOTS;
104 static inline bool is_topdown_event(struct perf_event *event)
106 return is_metric_event(event) || is_slots_event(event);
110 int nb_id; /* NorthBridge id */
111 int refcnt; /* reference count */
112 struct perf_event *owners[X86_PMC_IDX_MAX];
113 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
116 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
117 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
118 #define PEBS_OUTPUT_OFFSET 61
119 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
120 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
121 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
124 * Flags PEBS can handle without an PMI.
126 * TID can only be handled by flushing at context switch.
127 * REGS_USER can be handled for events limited to ring 3.
130 #define LARGE_PEBS_FLAGS \
131 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
132 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
133 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
134 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
135 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
136 PERF_SAMPLE_PERIOD | PERF_SAMPLE_CODE_PAGE_SIZE)
138 #define PEBS_GP_REGS \
139 ((1ULL << PERF_REG_X86_AX) | \
140 (1ULL << PERF_REG_X86_BX) | \
141 (1ULL << PERF_REG_X86_CX) | \
142 (1ULL << PERF_REG_X86_DX) | \
143 (1ULL << PERF_REG_X86_DI) | \
144 (1ULL << PERF_REG_X86_SI) | \
145 (1ULL << PERF_REG_X86_SP) | \
146 (1ULL << PERF_REG_X86_BP) | \
147 (1ULL << PERF_REG_X86_IP) | \
148 (1ULL << PERF_REG_X86_FLAGS) | \
149 (1ULL << PERF_REG_X86_R8) | \
150 (1ULL << PERF_REG_X86_R9) | \
151 (1ULL << PERF_REG_X86_R10) | \
152 (1ULL << PERF_REG_X86_R11) | \
153 (1ULL << PERF_REG_X86_R12) | \
154 (1ULL << PERF_REG_X86_R13) | \
155 (1ULL << PERF_REG_X86_R14) | \
156 (1ULL << PERF_REG_X86_R15))
159 * Per register state.
162 raw_spinlock_t lock; /* per-core: protect structure */
163 u64 config; /* extra MSR config */
164 u64 reg; /* extra MSR number */
165 atomic_t ref; /* reference count */
171 * Used to coordinate shared registers between HT threads or
172 * among events on a single PMU.
174 struct intel_shared_regs {
175 struct er_account regs[EXTRA_REG_MAX];
176 int refcnt; /* per-core: #HT threads */
177 unsigned core_id; /* per-core: core id */
180 enum intel_excl_state_type {
181 INTEL_EXCL_UNUSED = 0, /* counter is unused */
182 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
183 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
186 struct intel_excl_states {
187 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
188 bool sched_started; /* true if scheduling has started */
191 struct intel_excl_cntrs {
194 struct intel_excl_states states[2];
197 u16 has_exclusive[2];
198 u32 exclusive_present;
201 int refcnt; /* per-core: #HT threads */
202 unsigned core_id; /* per-core: core id */
205 struct x86_perf_task_context;
206 #define MAX_LBR_ENTRIES 32
209 LBR_FORMAT_32 = 0x00,
210 LBR_FORMAT_LIP = 0x01,
211 LBR_FORMAT_EIP = 0x02,
212 LBR_FORMAT_EIP_FLAGS = 0x03,
213 LBR_FORMAT_EIP_FLAGS2 = 0x04,
214 LBR_FORMAT_INFO = 0x05,
215 LBR_FORMAT_TIME = 0x06,
216 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
220 X86_PERF_KFREE_SHARED = 0,
221 X86_PERF_KFREE_EXCL = 1,
225 struct cpu_hw_events {
227 * Generic x86 PMC bits
229 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
230 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
233 int n_events; /* the # of events in the below arrays */
234 int n_added; /* the # last events in the below arrays;
235 they've never been enabled yet */
236 int n_txn; /* the # last events in the below arrays;
237 added in the current transaction */
240 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
241 u64 tags[X86_PMC_IDX_MAX];
243 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
244 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
246 int n_excl; /* the number of exclusive events */
248 unsigned int txn_flags;
252 * Intel DebugStore bits
254 struct debug_store *ds;
263 /* Current super set of events hardware configuration */
265 u64 active_pebs_data_cfg;
266 int pebs_record_size;
273 struct perf_branch_stack lbr_stack;
274 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
276 struct er_account *lbr_sel;
277 struct er_account *lbr_ctl;
286 * Intel host/guest exclude bits
288 u64 intel_ctrl_guest_mask;
289 u64 intel_ctrl_host_mask;
290 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
293 * Intel checkpoint mask
298 * manage shared (per-core, per-cpu) registers
299 * used on Intel NHM/WSM/SNB
301 struct intel_shared_regs *shared_regs;
303 * manage exclusive counter access between hyperthread
305 struct event_constraint *constraint_list; /* in enable order */
306 struct intel_excl_cntrs *excl_cntrs;
307 int excl_thread_id; /* 0 or 1 */
310 * SKL TSX_FORCE_ABORT shadow
317 /* number of accepted metrics events */
323 struct amd_nb *amd_nb;
324 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
325 u64 perf_ctr_virt_mask;
326 int n_pair; /* Large increment events */
328 void *kfree_on_online[X86_PERF_KFREE_MAX];
331 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
332 { .idxmsk64 = (n) }, \
341 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
342 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
344 #define EVENT_CONSTRAINT(c, n, m) \
345 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
348 * The constraint_match() function only works for 'simple' event codes
349 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
351 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
352 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
354 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
355 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
356 0, PERF_X86_EVENT_EXCL)
359 * The overlap flag marks event constraints with overlapping counter
360 * masks. This is the case if the counter mask of such an event is not
361 * a subset of any other counter mask of a constraint with an equal or
362 * higher weight, e.g.:
364 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
365 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
366 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
368 * The event scheduler may not select the correct counter in the first
369 * cycle because it needs to know which subsequent events will be
370 * scheduled. It may fail to schedule the events then. So we set the
371 * overlap flag for such constraints to give the scheduler a hint which
372 * events to select for counter rescheduling.
374 * Care must be taken as the rescheduling algorithm is O(n!) which
375 * will increase scheduling cycles for an over-committed system
376 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
377 * and its counter masks must be kept at a minimum.
379 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
380 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
383 * Constraint on the Event code.
385 #define INTEL_EVENT_CONSTRAINT(c, n) \
386 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
389 * Constraint on a range of Event codes
391 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
392 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
395 * Constraint on the Event code + UMask + fixed-mask
397 * filter mask to validate fixed counter events.
398 * the following filters disqualify for fixed counters:
403 * - in_tx_checkpointed
404 * The other filters are supported by fixed counters.
405 * The any-thread option is supported starting with v3.
407 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
408 #define FIXED_EVENT_CONSTRAINT(c, n) \
409 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
412 * The special metric counters do not actually exist. They are calculated from
413 * the combination of the FxCtr3 + MSR_PERF_METRICS.
415 * The special metric counters are mapped to a dummy offset for the scheduler.
416 * The sharing between multiple users of the same metric without multiplexing
417 * is not allowed, even though the hardware supports that in principle.
420 #define METRIC_EVENT_CONSTRAINT(c, n) \
421 EVENT_CONSTRAINT(c, (1ULL << (INTEL_PMC_IDX_METRIC_BASE + n)), \
422 INTEL_ARCH_EVENT_MASK)
425 * Constraint on the Event code + UMask
427 #define INTEL_UEVENT_CONSTRAINT(c, n) \
428 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
430 /* Constraint on specific umask bit only + event */
431 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
432 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
434 /* Like UEVENT_CONSTRAINT, but match flags too */
435 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
436 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
438 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
439 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
440 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
442 #define INTEL_PLD_CONSTRAINT(c, n) \
443 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
444 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
446 #define INTEL_PSD_CONSTRAINT(c, n) \
447 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
448 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_STLAT)
450 #define INTEL_PST_CONSTRAINT(c, n) \
451 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
452 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
454 /* Event constraint, but match on all event flags too. */
455 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
456 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
458 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
459 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
461 /* Check only flags, but allow all event/umask */
462 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
463 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
465 /* Check flags and event code, and set the HSW store flag */
466 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
467 __EVENT_CONSTRAINT(code, n, \
468 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
469 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
471 /* Check flags and event code, and set the HSW load flag */
472 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
473 __EVENT_CONSTRAINT(code, n, \
474 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
475 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
477 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
478 __EVENT_CONSTRAINT_RANGE(code, end, n, \
479 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
480 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
482 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
483 __EVENT_CONSTRAINT(code, n, \
484 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
486 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
488 /* Check flags and event code/umask, and set the HSW store flag */
489 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
490 __EVENT_CONSTRAINT(code, n, \
491 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
492 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
494 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
495 __EVENT_CONSTRAINT(code, n, \
496 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
498 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
500 /* Check flags and event code/umask, and set the HSW load flag */
501 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
502 __EVENT_CONSTRAINT(code, n, \
503 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
504 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
506 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
507 __EVENT_CONSTRAINT(code, n, \
508 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
510 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
512 /* Check flags and event code/umask, and set the HSW N/A flag */
513 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
514 __EVENT_CONSTRAINT(code, n, \
515 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
516 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
520 * We define the end marker as having a weight of -1
521 * to enable blacklisting of events using a counter bitmask
522 * of zero and thus a weight of zero.
523 * The end marker has a weight that cannot possibly be
524 * obtained from counting the bits in the bitmask.
526 #define EVENT_CONSTRAINT_END { .weight = -1 }
529 * Check for end marker with weight == -1
531 #define for_each_event_constraint(e, c) \
532 for ((e) = (c); (e)->weight != -1; (e)++)
535 * Extra registers for specific events.
537 * Some events need large masks and require external MSRs.
538 * Those extra MSRs end up being shared for all events on
539 * a PMU and sometimes between PMU of sibling HT threads.
540 * In either case, the kernel needs to handle conflicting
541 * accesses to those extra, shared, regs. The data structure
542 * to manage those registers is stored in cpu_hw_event.
549 int idx; /* per_xxx->regs[] reg index */
550 bool extra_msr_access;
553 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
556 .config_mask = (m), \
557 .valid_mask = (vm), \
558 .idx = EXTRA_REG_##i, \
559 .extra_msr_access = true, \
562 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
563 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
565 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
566 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
567 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
569 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
570 INTEL_UEVENT_EXTRA_REG(c, \
571 MSR_PEBS_LD_LAT_THRESHOLD, \
575 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
577 union perf_capabilities {
585 * PMU supports separate counter range for writing
588 u64 full_width_write:1;
591 u64 pebs_output_pt_available:1;
592 u64 anythread_deprecated:1;
597 struct x86_pmu_quirk {
598 struct x86_pmu_quirk *next;
602 union x86_pmu_config {
623 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
626 x86_lbr_exclusive_lbr,
627 x86_lbr_exclusive_bts,
628 x86_lbr_exclusive_pt,
629 x86_lbr_exclusive_max,
633 * struct x86_pmu - generic x86 pmu
637 * Generic x86 PMC bits
641 int (*handle_irq)(struct pt_regs *);
642 void (*disable_all)(void);
643 void (*enable_all)(int added);
644 void (*enable)(struct perf_event *);
645 void (*disable)(struct perf_event *);
646 void (*add)(struct perf_event *);
647 void (*del)(struct perf_event *);
648 void (*read)(struct perf_event *event);
649 int (*hw_config)(struct perf_event *event);
650 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
653 int (*addr_offset)(int index, bool eventsel);
654 int (*rdpmc_index)(int index);
655 u64 (*event_map)(int);
658 int num_counters_fixed;
662 unsigned long events_maskl;
663 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
668 struct event_constraint *
669 (*get_event_constraints)(struct cpu_hw_events *cpuc,
671 struct perf_event *event);
673 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
674 struct perf_event *event);
676 void (*start_scheduling)(struct cpu_hw_events *cpuc);
678 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
680 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
682 struct event_constraint *event_constraints;
683 struct x86_pmu_quirk *quirks;
684 int perfctr_second_write;
685 u64 (*limit_period)(struct perf_event *event, u64 l);
687 /* PMI handler bits */
688 unsigned int late_ack :1,
693 int attr_rdpmc_broken;
695 struct attribute **format_attrs;
697 ssize_t (*events_sysfs_show)(char *page, u64 config);
698 const struct attribute_group **attr_update;
700 unsigned long attr_freeze_on_smi;
705 int (*cpu_prepare)(int cpu);
706 void (*cpu_starting)(int cpu);
707 void (*cpu_dying)(int cpu);
708 void (*cpu_dead)(int cpu);
710 void (*check_microcode)(void);
711 void (*sched_task)(struct perf_event_context *ctx,
715 * Intel Arch Perfmon v2+
718 union perf_capabilities intel_cap;
721 * Intel DebugStore bits
730 pebs_no_isolation :1,
732 int pebs_record_size;
733 int pebs_buffer_size;
735 void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data);
736 struct event_constraint *pebs_constraints;
737 void (*pebs_aliases)(struct perf_event *event);
738 unsigned long large_pebs_flags;
744 unsigned int lbr_tos, lbr_from, lbr_to,
745 lbr_info, lbr_nr; /* LBR base regs and size */
747 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
748 u64 lbr_ctl_mask; /* LBR_CTL valid bits */
751 const int *lbr_sel_map; /* lbr_select mappings */
752 int *lbr_ctl_map; /* LBR_CTL mappings */
754 bool lbr_double_abort; /* duplicated lbr aborts */
755 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
758 * Intel Architectural LBR CPUID Enumeration
760 unsigned int lbr_depth_mask:8;
761 unsigned int lbr_deep_c_reset:1;
762 unsigned int lbr_lip:1;
763 unsigned int lbr_cpl:1;
764 unsigned int lbr_filter:1;
765 unsigned int lbr_call_stack:1;
766 unsigned int lbr_mispred:1;
767 unsigned int lbr_timed_lbr:1;
768 unsigned int lbr_br_type:1;
770 void (*lbr_reset)(void);
771 void (*lbr_read)(struct cpu_hw_events *cpuc);
772 void (*lbr_save)(void *ctx);
773 void (*lbr_restore)(void *ctx);
776 * Intel PT/LBR/BTS are exclusive
778 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
783 int num_topdown_events;
784 u64 (*update_topdown_event)(struct perf_event *event);
785 int (*set_topdown_event_period)(struct perf_event *event);
788 * perf task context (i.e. struct perf_event_context::task_ctx_data)
789 * switch helper to bridge calls from perf/core to perf/x86.
790 * See struct pmu::swap_task_ctx() usage for examples;
792 void (*swap_task_ctx)(struct perf_event_context *prev,
793 struct perf_event_context *next);
798 unsigned int amd_nb_constraints : 1;
799 u64 perf_ctr_pair_en;
802 * Extra registers for events
804 struct extra_reg *extra_regs;
808 * Intel host/guest support (KVM)
810 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
813 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
815 int (*check_period) (struct perf_event *event, u64 period);
817 int (*aux_output_match) (struct perf_event *event);
820 struct x86_perf_task_context_opt {
821 int lbr_callstack_users;
826 struct x86_perf_task_context {
830 struct x86_perf_task_context_opt opt;
831 struct lbr_entry lbr[MAX_LBR_ENTRIES];
834 struct x86_perf_task_context_arch_lbr {
835 struct x86_perf_task_context_opt opt;
836 struct lbr_entry entries[];
840 * Add padding to guarantee the 64-byte alignment of the state buffer.
842 * The structure is dynamically allocated. The size of the LBR state may vary
843 * based on the number of LBR registers.
845 * Do not put anything after the LBR state.
847 struct x86_perf_task_context_arch_lbr_xsave {
848 struct x86_perf_task_context_opt opt;
851 struct xregs_state xsave;
853 struct fxregs_state i387;
854 struct xstate_header header;
855 struct arch_lbr_state lbr;
856 } __attribute__ ((packed, aligned (XSAVE_ALIGNMENT)));
860 #define x86_add_quirk(func_) \
862 static struct x86_pmu_quirk __quirk __initdata = { \
865 __quirk.next = x86_pmu.quirks; \
866 x86_pmu.quirks = &__quirk; \
872 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
873 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
874 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
875 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
876 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
877 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
878 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
879 #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */
880 #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */
882 #define EVENT_VAR(_id) event_attr_##_id
883 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
885 #define EVENT_ATTR(_name, _id) \
886 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
887 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
888 .id = PERF_COUNT_HW_##_id, \
892 #define EVENT_ATTR_STR(_name, v, str) \
893 static struct perf_pmu_events_attr event_attr_##v = { \
894 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
899 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
900 static struct perf_pmu_events_ht_attr event_attr_##v = { \
901 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
903 .event_str_noht = noht, \
904 .event_str_ht = ht, \
907 struct pmu *x86_get_pmu(void);
908 extern struct x86_pmu x86_pmu __read_mostly;
910 static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
912 if (static_cpu_has(X86_FEATURE_ARCH_LBR))
913 return &((struct x86_perf_task_context_arch_lbr *)ctx)->opt;
915 return &((struct x86_perf_task_context *)ctx)->opt;
918 static inline bool x86_pmu_has_lbr_callstack(void)
920 return x86_pmu.lbr_sel_map &&
921 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
924 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
926 int x86_perf_event_set_period(struct perf_event *event);
929 * Generalized hw caching related hw_event table, filled
930 * in on a per model basis. A value of 0 means
931 * 'not supported', -1 means 'hw_event makes no sense on
932 * this CPU', any other value means the raw hw_event
936 #define C(x) PERF_COUNT_HW_CACHE_##x
938 extern u64 __read_mostly hw_cache_event_ids
939 [PERF_COUNT_HW_CACHE_MAX]
940 [PERF_COUNT_HW_CACHE_OP_MAX]
941 [PERF_COUNT_HW_CACHE_RESULT_MAX];
942 extern u64 __read_mostly hw_cache_extra_regs
943 [PERF_COUNT_HW_CACHE_MAX]
944 [PERF_COUNT_HW_CACHE_OP_MAX]
945 [PERF_COUNT_HW_CACHE_RESULT_MAX];
947 u64 x86_perf_event_update(struct perf_event *event);
949 static inline unsigned int x86_pmu_config_addr(int index)
951 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
952 x86_pmu.addr_offset(index, true) : index);
955 static inline unsigned int x86_pmu_event_addr(int index)
957 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
958 x86_pmu.addr_offset(index, false) : index);
961 static inline int x86_pmu_rdpmc_index(int index)
963 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
966 int x86_add_exclusive(unsigned int what);
968 void x86_del_exclusive(unsigned int what);
970 int x86_reserve_hardware(void);
972 void x86_release_hardware(void);
974 int x86_pmu_max_precise(void);
976 void hw_perf_lbr_event_destroy(struct perf_event *event);
978 int x86_setup_perfctr(struct perf_event *event);
980 int x86_pmu_hw_config(struct perf_event *event);
982 void x86_pmu_disable_all(void);
984 static inline bool is_counter_pair(struct hw_perf_event *hwc)
986 return hwc->flags & PERF_X86_EVENT_PAIR;
989 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
992 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
994 if (hwc->extra_reg.reg)
995 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
998 * Add enabled Merge event on next counter
999 * if large increment event being enabled on this counter
1001 if (is_counter_pair(hwc))
1002 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en);
1004 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
1007 void x86_pmu_enable_all(int added);
1009 int perf_assign_events(struct event_constraint **constraints, int n,
1010 int wmin, int wmax, int gpmax, int *assign);
1011 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
1013 void x86_pmu_stop(struct perf_event *event, int flags);
1015 static inline void x86_pmu_disable_event(struct perf_event *event)
1017 struct hw_perf_event *hwc = &event->hw;
1019 wrmsrl(hwc->config_base, hwc->config);
1021 if (is_counter_pair(hwc))
1022 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);
1025 void x86_pmu_enable_event(struct perf_event *event);
1027 int x86_pmu_handle_irq(struct pt_regs *regs);
1029 extern struct event_constraint emptyconstraint;
1031 extern struct event_constraint unconstrained;
1033 static inline bool kernel_ip(unsigned long ip)
1035 #ifdef CONFIG_X86_32
1036 return ip > PAGE_OFFSET;
1038 return (long)ip < 0;
1043 * Not all PMUs provide the right context information to place the reported IP
1044 * into full context. Specifically segment registers are typically not
1047 * Assuming the address is a linear address (it is for IBS), we fake the CS and
1048 * vm86 mode using the known zero-based code segment and 'fix up' the registers
1051 * Intel PEBS/LBR appear to typically provide the effective address, nothing
1052 * much we can do about that but pray and treat it like a linear address.
1054 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
1056 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
1057 if (regs->flags & X86_VM_MASK)
1058 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
1062 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
1063 ssize_t intel_event_sysfs_show(char *page, u64 config);
1065 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1067 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1070 static inline bool fixed_counter_disabled(int i)
1072 return !(x86_pmu.intel_ctrl >> (i + INTEL_PMC_IDX_FIXED));
1075 #ifdef CONFIG_CPU_SUP_AMD
1077 int amd_pmu_init(void);
1079 #else /* CONFIG_CPU_SUP_AMD */
1081 static inline int amd_pmu_init(void)
1086 #endif /* CONFIG_CPU_SUP_AMD */
1088 static inline int is_pebs_pt(struct perf_event *event)
1090 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
1093 #ifdef CONFIG_CPU_SUP_INTEL
1095 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
1097 struct hw_perf_event *hwc = &event->hw;
1098 unsigned int hw_event, bts_event;
1100 if (event->attr.freq)
1103 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1104 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1106 return hw_event == bts_event && period == 1;
1109 static inline bool intel_pmu_has_bts(struct perf_event *event)
1111 struct hw_perf_event *hwc = &event->hw;
1113 return intel_pmu_has_bts_period(event, hwc->sample_period);
1116 int intel_pmu_save_and_restart(struct perf_event *event);
1118 struct event_constraint *
1119 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
1120 struct perf_event *event);
1122 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
1123 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
1125 int intel_pmu_init(void);
1127 void init_debug_store_on_cpu(int cpu);
1129 void fini_debug_store_on_cpu(int cpu);
1131 void release_ds_buffers(void);
1133 void reserve_ds_buffers(void);
1135 void release_lbr_buffers(void);
1137 extern struct event_constraint bts_constraint;
1138 extern struct event_constraint vlbr_constraint;
1140 void intel_pmu_enable_bts(u64 config);
1142 void intel_pmu_disable_bts(void);
1144 int intel_pmu_drain_bts_buffer(void);
1146 extern struct event_constraint intel_core2_pebs_event_constraints[];
1148 extern struct event_constraint intel_atom_pebs_event_constraints[];
1150 extern struct event_constraint intel_slm_pebs_event_constraints[];
1152 extern struct event_constraint intel_glm_pebs_event_constraints[];
1154 extern struct event_constraint intel_glp_pebs_event_constraints[];
1156 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1158 extern struct event_constraint intel_westmere_pebs_event_constraints[];
1160 extern struct event_constraint intel_snb_pebs_event_constraints[];
1162 extern struct event_constraint intel_ivb_pebs_event_constraints[];
1164 extern struct event_constraint intel_hsw_pebs_event_constraints[];
1166 extern struct event_constraint intel_bdw_pebs_event_constraints[];
1168 extern struct event_constraint intel_skl_pebs_event_constraints[];
1170 extern struct event_constraint intel_icl_pebs_event_constraints[];
1172 extern struct event_constraint intel_spr_pebs_event_constraints[];
1174 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1176 void intel_pmu_pebs_add(struct perf_event *event);
1178 void intel_pmu_pebs_del(struct perf_event *event);
1180 void intel_pmu_pebs_enable(struct perf_event *event);
1182 void intel_pmu_pebs_disable(struct perf_event *event);
1184 void intel_pmu_pebs_enable_all(void);
1186 void intel_pmu_pebs_disable_all(void);
1188 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1190 void intel_pmu_auto_reload_read(struct perf_event *event);
1192 void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr);
1194 void intel_ds_init(void);
1196 void intel_pmu_lbr_swap_task_ctx(struct perf_event_context *prev,
1197 struct perf_event_context *next);
1199 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1201 u64 lbr_from_signext_quirk_wr(u64 val);
1203 void intel_pmu_lbr_reset(void);
1205 void intel_pmu_lbr_reset_32(void);
1207 void intel_pmu_lbr_reset_64(void);
1209 void intel_pmu_lbr_add(struct perf_event *event);
1211 void intel_pmu_lbr_del(struct perf_event *event);
1213 void intel_pmu_lbr_enable_all(bool pmi);
1215 void intel_pmu_lbr_disable_all(void);
1217 void intel_pmu_lbr_read(void);
1219 void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
1221 void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
1223 void intel_pmu_lbr_save(void *ctx);
1225 void intel_pmu_lbr_restore(void *ctx);
1227 void intel_pmu_lbr_init_core(void);
1229 void intel_pmu_lbr_init_nhm(void);
1231 void intel_pmu_lbr_init_atom(void);
1233 void intel_pmu_lbr_init_slm(void);
1235 void intel_pmu_lbr_init_snb(void);
1237 void intel_pmu_lbr_init_hsw(void);
1239 void intel_pmu_lbr_init_skl(void);
1241 void intel_pmu_lbr_init_knl(void);
1243 void intel_pmu_arch_lbr_init(void);
1245 void intel_pmu_pebs_data_source_nhm(void);
1247 void intel_pmu_pebs_data_source_skl(bool pmem);
1249 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1251 void intel_pt_interrupt(void);
1253 int intel_bts_interrupt(void);
1255 void intel_bts_enable_local(void);
1257 void intel_bts_disable_local(void);
1259 int p4_pmu_init(void);
1261 int p6_pmu_init(void);
1263 int knc_pmu_init(void);
1265 static inline int is_ht_workaround_enabled(void)
1267 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1270 #else /* CONFIG_CPU_SUP_INTEL */
1272 static inline void reserve_ds_buffers(void)
1276 static inline void release_ds_buffers(void)
1280 static inline void release_lbr_buffers(void)
1284 static inline int intel_pmu_init(void)
1289 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1294 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1298 static inline int is_ht_workaround_enabled(void)
1302 #endif /* CONFIG_CPU_SUP_INTEL */
1304 #if ((defined CONFIG_CPU_SUP_CENTAUR) || (defined CONFIG_CPU_SUP_ZHAOXIN))
1305 int zhaoxin_pmu_init(void);
1307 static inline int zhaoxin_pmu_init(void)
1311 #endif /*CONFIG_CPU_SUP_CENTAUR or CONFIG_CPU_SUP_ZHAOXIN*/