arch/x86/events/msr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/perf_event.h>
   3 #include <linux/sysfs.h>
   4 #include <linux/nospec.h>
   5 #include <asm/intel-family.h>
   6 #include "probe.h"
   7
   8 enum perf_msr_id {
   9         PERF_MSR_TSC                    = 0,
  10         PERF_MSR_APERF                  = 1,
  11         PERF_MSR_MPERF                  = 2,
  12         PERF_MSR_PPERF                  = 3,
  13         PERF_MSR_SMI                    = 4,
  14         PERF_MSR_PTSC                   = 5,
  15         PERF_MSR_IRPERF                 = 6,
  16         PERF_MSR_THERM                  = 7,
  17         PERF_MSR_EVENT_MAX,
  18 };
  19
  20 static bool test_aperfmperf(int idx, void *data)
  21 {
  22         return boot_cpu_has(X86_FEATURE_APERFMPERF);
  23 }
  24
  25 static bool test_ptsc(int idx, void *data)
  26 {
  27         return boot_cpu_has(X86_FEATURE_PTSC);
  28 }
  29
  30 static bool test_irperf(int idx, void *data)
  31 {
  32         return boot_cpu_has(X86_FEATURE_IRPERF);
  33 }
  34
  35 static bool test_therm_status(int idx, void *data)
  36 {
  37         return boot_cpu_has(X86_FEATURE_DTHERM);
  38 }
  39
  40 static bool test_intel(int idx, void *data)
  41 {
  42         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
  43             boot_cpu_data.x86 != 6)
  44                 return false;
  45
  46         switch (boot_cpu_data.x86_model) {
  47         case INTEL_FAM6_NEHALEM:
  48         case INTEL_FAM6_NEHALEM_G:
  49         case INTEL_FAM6_NEHALEM_EP:
  50         case INTEL_FAM6_NEHALEM_EX:
  51
  52         case INTEL_FAM6_WESTMERE:
  53         case INTEL_FAM6_WESTMERE_EP:
  54         case INTEL_FAM6_WESTMERE_EX:
  55
  56         case INTEL_FAM6_SANDYBRIDGE:
  57         case INTEL_FAM6_SANDYBRIDGE_X:
  58
  59         case INTEL_FAM6_IVYBRIDGE:
  60         case INTEL_FAM6_IVYBRIDGE_X:
  61
  62         case INTEL_FAM6_HASWELL:
  63         case INTEL_FAM6_HASWELL_X:
  64         case INTEL_FAM6_HASWELL_L:
  65         case INTEL_FAM6_HASWELL_G:
  66
  67         case INTEL_FAM6_BROADWELL:
  68         case INTEL_FAM6_BROADWELL_D:
  69         case INTEL_FAM6_BROADWELL_G:
  70         case INTEL_FAM6_BROADWELL_X:
  71         case INTEL_FAM6_SAPPHIRERAPIDS_X:
  72
  73         case INTEL_FAM6_ATOM_SILVERMONT:
  74         case INTEL_FAM6_ATOM_SILVERMONT_D:
  75         case INTEL_FAM6_ATOM_AIRMONT:
  76
  77         case INTEL_FAM6_ATOM_GOLDMONT:
  78         case INTEL_FAM6_ATOM_GOLDMONT_D:
  79         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
  80         case INTEL_FAM6_ATOM_TREMONT_D:
  81         case INTEL_FAM6_ATOM_TREMONT:
  82         case INTEL_FAM6_ATOM_TREMONT_L:
  83
  84         case INTEL_FAM6_XEON_PHI_KNL:
  85         case INTEL_FAM6_XEON_PHI_KNM:
  86                 if (idx == PERF_MSR_SMI)
  87                         return true;
  88                 break;
  89
  90         case INTEL_FAM6_SKYLAKE_L:
  91         case INTEL_FAM6_SKYLAKE:
  92         case INTEL_FAM6_SKYLAKE_X:
  93         case INTEL_FAM6_KABYLAKE_L:
  94         case INTEL_FAM6_KABYLAKE:
  95         case INTEL_FAM6_COMETLAKE_L:
  96         case INTEL_FAM6_COMETLAKE:
  97         case INTEL_FAM6_ICELAKE_L:
  98         case INTEL_FAM6_ICELAKE:
  99         case INTEL_FAM6_ICELAKE_X:
 100         case INTEL_FAM6_ICELAKE_D:
 101         case INTEL_FAM6_TIGERLAKE_L:
 102         case INTEL_FAM6_TIGERLAKE:
 103         case INTEL_FAM6_ROCKETLAKE:
 104         case INTEL_FAM6_ALDERLAKE:
 105         case INTEL_FAM6_ALDERLAKE_L:
 106         case INTEL_FAM6_RAPTORLAKE:
 107                 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 108                         return true;
 109                 break;
 110         }
 111
 112         return false;
 113 }
 114
 115 PMU_EVENT_ATTR_STRING(tsc,                              attr_tsc,               "event=0x00"    );
 116 PMU_EVENT_ATTR_STRING(aperf,                            attr_aperf,             "event=0x01"    );
 117 PMU_EVENT_ATTR_STRING(mperf,                            attr_mperf,             "event=0x02"    );
 118 PMU_EVENT_ATTR_STRING(pperf,                            attr_pperf,             "event=0x03"    );
 119 PMU_EVENT_ATTR_STRING(smi,                              attr_smi,               "event=0x04"    );
 120 PMU_EVENT_ATTR_STRING(ptsc,                             attr_ptsc,              "event=0x05"    );
 121 PMU_EVENT_ATTR_STRING(irperf,                           attr_irperf,            "event=0x06"    );
 122 PMU_EVENT_ATTR_STRING(cpu_thermal_margin,               attr_therm,             "event=0x07"    );
 123 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,      attr_therm_snap,        "1"             );
 124 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,          attr_therm_unit,        "C"             );
 125
 126 static unsigned long msr_mask;
 127
 128 PMU_EVENT_GROUP(events, aperf);
 129 PMU_EVENT_GROUP(events, mperf);
 130 PMU_EVENT_GROUP(events, pperf);
 131 PMU_EVENT_GROUP(events, smi);
 132 PMU_EVENT_GROUP(events, ptsc);
 133 PMU_EVENT_GROUP(events, irperf);
 134
 135 static struct attribute *attrs_therm[] = {
 136         &attr_therm.attr.attr,
 137         &attr_therm_snap.attr.attr,
 138         &attr_therm_unit.attr.attr,
 139         NULL,
 140 };
 141
 142 static struct attribute_group group_therm = {
 143         .name  = "events",
 144         .attrs = attrs_therm,
 145 };
 146
 147 static struct perf_msr msr[] = {
 148         [PERF_MSR_TSC]          = { .no_check = true,                                                           },
 149         [PERF_MSR_APERF]        = { MSR_IA32_APERF,             &group_aperf,           test_aperfmperf,        },
 150         [PERF_MSR_MPERF]        = { MSR_IA32_MPERF,             &group_mperf,           test_aperfmperf,        },
 151         [PERF_MSR_PPERF]        = { MSR_PPERF,                  &group_pperf,           test_intel,             },
 152         [PERF_MSR_SMI]          = { MSR_SMI_COUNT,              &group_smi,             test_intel,             },
 153         [PERF_MSR_PTSC]         = { MSR_F15H_PTSC,              &group_ptsc,            test_ptsc,              },
 154         [PERF_MSR_IRPERF]       = { MSR_F17H_IRPERF,            &group_irperf,          test_irperf,            },
 155         [PERF_MSR_THERM]        = { MSR_IA32_THERM_STATUS,      &group_therm,           test_therm_status,      },
 156 };
 157
 158 static struct attribute *events_attrs[] = {
 159         &attr_tsc.attr.attr,
 160         NULL,
 161 };
 162
 163 static struct attribute_group events_attr_group = {
 164         .name = "events",
 165         .attrs = events_attrs,
 166 };
 167
 168 PMU_FORMAT_ATTR(event, "config:0-63");
 169 static struct attribute *format_attrs[] = {
 170         &format_attr_event.attr,
 171         NULL,
 172 };
 173 static struct attribute_group format_attr_group = {
 174         .name = "format",
 175         .attrs = format_attrs,
 176 };
 177
 178 static const struct attribute_group *attr_groups[] = {
 179         &events_attr_group,
 180         &format_attr_group,
 181         NULL,
 182 };
 183
 184 static const struct attribute_group *attr_update[] = {
 185         &group_aperf,
 186         &group_mperf,
 187         &group_pperf,
 188         &group_smi,
 189         &group_ptsc,
 190         &group_irperf,
 191         &group_therm,
 192         NULL,
 193 };
 194
 195 static int msr_event_init(struct perf_event *event)
 196 {
 197         u64 cfg = event->attr.config;
 198
 199         if (event->attr.type != event->pmu->type)
 200                 return -ENOENT;
 201
 202         /* unsupported modes and filters */
 203         if (event->attr.sample_period) /* no sampling */
 204                 return -EINVAL;
 205
 206         if (cfg >= PERF_MSR_EVENT_MAX)
 207                 return -EINVAL;
 208
 209         cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
 210
 211         if (!(msr_mask & (1 << cfg)))
 212                 return -EINVAL;
 213
 214         event->hw.idx           = -1;
 215         event->hw.event_base    = msr[cfg].msr;
 216         event->hw.config        = cfg;
 217
 218         return 0;
 219 }
 220
 221 static inline u64 msr_read_counter(struct perf_event *event)
 222 {
 223         u64 now;
 224
 225         if (event->hw.event_base)
 226                 rdmsrl(event->hw.event_base, now);
 227         else
 228                 now = rdtsc_ordered();
 229
 230         return now;
 231 }
 232
 233 static void msr_event_update(struct perf_event *event)
 234 {
 235         u64 prev, now;
 236         s64 delta;
 237
 238         /* Careful, an NMI might modify the previous event value: */
 239 again:
 240         prev = local64_read(&event->hw.prev_count);
 241         now = msr_read_counter(event);
 242
 243         if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
 244                 goto again;
 245
 246         delta = now - prev;
 247         if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
 248                 delta = sign_extend64(delta, 31);
 249                 local64_add(delta, &event->count);
 250         } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
 251                 /* If valid, extract digital readout, otherwise set to -1: */
 252                 now = now & (1ULL << 31) ? (now >> 16) & 0x3f :  -1;
 253                 local64_set(&event->count, now);
 254         } else {
 255                 local64_add(delta, &event->count);
 256         }
 257 }
 258
 259 static void msr_event_start(struct perf_event *event, int flags)
 260 {
 261         u64 now = msr_read_counter(event);
 262
 263         local64_set(&event->hw.prev_count, now);
 264 }
 265
 266 static void msr_event_stop(struct perf_event *event, int flags)
 267 {
 268         msr_event_update(event);
 269 }
 270
 271 static void msr_event_del(struct perf_event *event, int flags)
 272 {
 273         msr_event_stop(event, PERF_EF_UPDATE);
 274 }
 275
 276 static int msr_event_add(struct perf_event *event, int flags)
 277 {
 278         if (flags & PERF_EF_START)
 279                 msr_event_start(event, flags);
 280
 281         return 0;
 282 }
 283
 284 static struct pmu pmu_msr = {
 285         .task_ctx_nr    = perf_sw_context,
 286         .attr_groups    = attr_groups,
 287         .event_init     = msr_event_init,
 288         .add            = msr_event_add,
 289         .del            = msr_event_del,
 290         .start          = msr_event_start,
 291         .stop           = msr_event_stop,
 292         .read           = msr_event_update,
 293         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 294         .attr_update    = attr_update,
 295 };
 296
 297 static int __init msr_init(void)
 298 {
 299         if (!boot_cpu_has(X86_FEATURE_TSC)) {
 300                 pr_cont("no MSR PMU driver.\n");
 301                 return 0;
 302         }
 303
 304         msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
 305
 306         perf_pmu_register(&pmu_msr, "msr", -1);
 307
 308         return 0;
 309 }
 310 device_initcall(msr_init);