arch/x86/events/msr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/perf_event.h>
   3 #include <linux/sysfs.h>
   4 #include <linux/nospec.h>
   5 #include <asm/intel-family.h>
   6 #include "probe.h"
   7
   8 enum perf_msr_id {
   9         PERF_MSR_TSC                    = 0,
  10         PERF_MSR_APERF                  = 1,
  11         PERF_MSR_MPERF                  = 2,
  12         PERF_MSR_PPERF                  = 3,
  13         PERF_MSR_SMI                    = 4,
  14         PERF_MSR_PTSC                   = 5,
  15         PERF_MSR_IRPERF                 = 6,
  16         PERF_MSR_THERM                  = 7,
  17         PERF_MSR_EVENT_MAX,
  18 };
  19
  20 static bool test_aperfmperf(int idx, void *data)
  21 {
  22         return boot_cpu_has(X86_FEATURE_APERFMPERF);
  23 }
  24
  25 static bool test_ptsc(int idx, void *data)
  26 {
  27         return boot_cpu_has(X86_FEATURE_PTSC);
  28 }
  29
  30 static bool test_irperf(int idx, void *data)
  31 {
  32         return boot_cpu_has(X86_FEATURE_IRPERF);
  33 }
  34
  35 static bool test_therm_status(int idx, void *data)
  36 {
  37         return boot_cpu_has(X86_FEATURE_DTHERM);
  38 }
  39
  40 static bool test_intel(int idx, void *data)
  41 {
  42         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
  43             boot_cpu_data.x86 != 6)
  44                 return false;
  45
  46         switch (boot_cpu_data.x86_model) {
  47         case INTEL_FAM6_NEHALEM:
  48         case INTEL_FAM6_NEHALEM_G:
  49         case INTEL_FAM6_NEHALEM_EP:
  50         case INTEL_FAM6_NEHALEM_EX:
  51
  52         case INTEL_FAM6_WESTMERE:
  53         case INTEL_FAM6_WESTMERE_EP:
  54         case INTEL_FAM6_WESTMERE_EX:
  55
  56         case INTEL_FAM6_SANDYBRIDGE:
  57         case INTEL_FAM6_SANDYBRIDGE_X:
  58
  59         case INTEL_FAM6_IVYBRIDGE:
  60         case INTEL_FAM6_IVYBRIDGE_X:
  61
  62         case INTEL_FAM6_HASWELL:
  63         case INTEL_FAM6_HASWELL_X:
  64         case INTEL_FAM6_HASWELL_L:
  65         case INTEL_FAM6_HASWELL_G:
  66
  67         case INTEL_FAM6_BROADWELL:
  68         case INTEL_FAM6_BROADWELL_D:
  69         case INTEL_FAM6_BROADWELL_G:
  70         case INTEL_FAM6_BROADWELL_X:
  71
  72         case INTEL_FAM6_ATOM_SILVERMONT:
  73         case INTEL_FAM6_ATOM_SILVERMONT_D:
  74         case INTEL_FAM6_ATOM_AIRMONT:
  75
  76         case INTEL_FAM6_ATOM_GOLDMONT:
  77         case INTEL_FAM6_ATOM_GOLDMONT_D:
  78         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
  79         case INTEL_FAM6_ATOM_TREMONT_D:
  80         case INTEL_FAM6_ATOM_TREMONT:
  81         case INTEL_FAM6_ATOM_TREMONT_L:
  82
  83         case INTEL_FAM6_XEON_PHI_KNL:
  84         case INTEL_FAM6_XEON_PHI_KNM:
  85                 if (idx == PERF_MSR_SMI)
  86                         return true;
  87                 break;
  88
  89         case INTEL_FAM6_SKYLAKE_L:
  90         case INTEL_FAM6_SKYLAKE:
  91         case INTEL_FAM6_SKYLAKE_X:
  92         case INTEL_FAM6_KABYLAKE_L:
  93         case INTEL_FAM6_KABYLAKE:
  94         case INTEL_FAM6_COMETLAKE_L:
  95         case INTEL_FAM6_COMETLAKE:
  96         case INTEL_FAM6_ICELAKE_L:
  97         case INTEL_FAM6_ICELAKE:
  98         case INTEL_FAM6_ICELAKE_X:
  99         case INTEL_FAM6_ICELAKE_D:
 100         case INTEL_FAM6_TIGERLAKE_L:
 101         case INTEL_FAM6_TIGERLAKE:
 102                 if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 103                         return true;
 104                 break;
 105         }
 106
 107         return false;
 108 }
 109
 110 PMU_EVENT_ATTR_STRING(tsc,                              attr_tsc,               "event=0x00"    );
 111 PMU_EVENT_ATTR_STRING(aperf,                            attr_aperf,             "event=0x01"    );
 112 PMU_EVENT_ATTR_STRING(mperf,                            attr_mperf,             "event=0x02"    );
 113 PMU_EVENT_ATTR_STRING(pperf,                            attr_pperf,             "event=0x03"    );
 114 PMU_EVENT_ATTR_STRING(smi,                              attr_smi,               "event=0x04"    );
 115 PMU_EVENT_ATTR_STRING(ptsc,                             attr_ptsc,              "event=0x05"    );
 116 PMU_EVENT_ATTR_STRING(irperf,                           attr_irperf,            "event=0x06"    );
 117 PMU_EVENT_ATTR_STRING(cpu_thermal_margin,               attr_therm,             "event=0x07"    );
 118 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,      attr_therm_snap,        "1"             );
 119 PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,          attr_therm_unit,        "C"             );
 120
 121 static unsigned long msr_mask;
 122
 123 PMU_EVENT_GROUP(events, aperf);
 124 PMU_EVENT_GROUP(events, mperf);
 125 PMU_EVENT_GROUP(events, pperf);
 126 PMU_EVENT_GROUP(events, smi);
 127 PMU_EVENT_GROUP(events, ptsc);
 128 PMU_EVENT_GROUP(events, irperf);
 129
 130 static struct attribute *attrs_therm[] = {
 131         &attr_therm.attr.attr,
 132         &attr_therm_snap.attr.attr,
 133         &attr_therm_unit.attr.attr,
 134         NULL,
 135 };
 136
 137 static struct attribute_group group_therm = {
 138         .name  = "events",
 139         .attrs = attrs_therm,
 140 };
 141
 142 static struct perf_msr msr[] = {
 143         [PERF_MSR_TSC]          = { .no_check = true,                                                           },
 144         [PERF_MSR_APERF]        = { MSR_IA32_APERF,             &group_aperf,           test_aperfmperf,        },
 145         [PERF_MSR_MPERF]        = { MSR_IA32_MPERF,             &group_mperf,           test_aperfmperf,        },
 146         [PERF_MSR_PPERF]        = { MSR_PPERF,                  &group_pperf,           test_intel,             },
 147         [PERF_MSR_SMI]          = { MSR_SMI_COUNT,              &group_smi,             test_intel,             },
 148         [PERF_MSR_PTSC]         = { MSR_F15H_PTSC,              &group_ptsc,            test_ptsc,              },
 149         [PERF_MSR_IRPERF]       = { MSR_F17H_IRPERF,            &group_irperf,          test_irperf,            },
 150         [PERF_MSR_THERM]        = { MSR_IA32_THERM_STATUS,      &group_therm,           test_therm_status,      },
 151 };
 152
 153 static struct attribute *events_attrs[] = {
 154         &attr_tsc.attr.attr,
 155         NULL,
 156 };
 157
 158 static struct attribute_group events_attr_group = {
 159         .name = "events",
 160         .attrs = events_attrs,
 161 };
 162
 163 PMU_FORMAT_ATTR(event, "config:0-63");
 164 static struct attribute *format_attrs[] = {
 165         &format_attr_event.attr,
 166         NULL,
 167 };
 168 static struct attribute_group format_attr_group = {
 169         .name = "format",
 170         .attrs = format_attrs,
 171 };
 172
 173 static const struct attribute_group *attr_groups[] = {
 174         &events_attr_group,
 175         &format_attr_group,
 176         NULL,
 177 };
 178
 179 static const struct attribute_group *attr_update[] = {
 180         &group_aperf,
 181         &group_mperf,
 182         &group_pperf,
 183         &group_smi,
 184         &group_ptsc,
 185         &group_irperf,
 186         &group_therm,
 187         NULL,
 188 };
 189
 190 static int msr_event_init(struct perf_event *event)
 191 {
 192         u64 cfg = event->attr.config;
 193
 194         if (event->attr.type != event->pmu->type)
 195                 return -ENOENT;
 196
 197         /* unsupported modes and filters */
 198         if (event->attr.sample_period) /* no sampling */
 199                 return -EINVAL;
 200
 201         if (cfg >= PERF_MSR_EVENT_MAX)
 202                 return -EINVAL;
 203
 204         cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
 205
 206         if (!(msr_mask & (1 << cfg)))
 207                 return -EINVAL;
 208
 209         event->hw.idx           = -1;
 210         event->hw.event_base    = msr[cfg].msr;
 211         event->hw.config        = cfg;
 212
 213         return 0;
 214 }
 215
 216 static inline u64 msr_read_counter(struct perf_event *event)
 217 {
 218         u64 now;
 219
 220         if (event->hw.event_base)
 221                 rdmsrl(event->hw.event_base, now);
 222         else
 223                 now = rdtsc_ordered();
 224
 225         return now;
 226 }
 227
 228 static void msr_event_update(struct perf_event *event)
 229 {
 230         u64 prev, now;
 231         s64 delta;
 232
 233         /* Careful, an NMI might modify the previous event value: */
 234 again:
 235         prev = local64_read(&event->hw.prev_count);
 236         now = msr_read_counter(event);
 237
 238         if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
 239                 goto again;
 240
 241         delta = now - prev;
 242         if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) {
 243                 delta = sign_extend64(delta, 31);
 244                 local64_add(delta, &event->count);
 245         } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) {
 246                 /* If valid, extract digital readout, otherwise set to -1: */
 247                 now = now & (1ULL << 31) ? (now >> 16) & 0x3f :  -1;
 248                 local64_set(&event->count, now);
 249         } else {
 250                 local64_add(delta, &event->count);
 251         }
 252 }
 253
 254 static void msr_event_start(struct perf_event *event, int flags)
 255 {
 256         u64 now = msr_read_counter(event);
 257
 258         local64_set(&event->hw.prev_count, now);
 259 }
 260
 261 static void msr_event_stop(struct perf_event *event, int flags)
 262 {
 263         msr_event_update(event);
 264 }
 265
 266 static void msr_event_del(struct perf_event *event, int flags)
 267 {
 268         msr_event_stop(event, PERF_EF_UPDATE);
 269 }
 270
 271 static int msr_event_add(struct perf_event *event, int flags)
 272 {
 273         if (flags & PERF_EF_START)
 274                 msr_event_start(event, flags);
 275
 276         return 0;
 277 }
 278
 279 static struct pmu pmu_msr = {
 280         .task_ctx_nr    = perf_sw_context,
 281         .attr_groups    = attr_groups,
 282         .event_init     = msr_event_init,
 283         .add            = msr_event_add,
 284         .del            = msr_event_del,
 285         .start          = msr_event_start,
 286         .stop           = msr_event_stop,
 287         .read           = msr_event_update,
 288         .capabilities   = PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
 289         .attr_update    = attr_update,
 290 };
 291
 292 static int __init msr_init(void)
 293 {
 294         if (!boot_cpu_has(X86_FEATURE_TSC)) {
 295                 pr_cont("no MSR PMU driver.\n");
 296                 return 0;
 297         }
 298
 299         msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
 300
 301         perf_pmu_register(&pmu_msr, "msr", -1);
 302
 303         return 0;
 304 }
 305 device_initcall(msr_init);