1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/slab.h>
4 #include <asm/apicdef.h>
5 #include <linux/io-64-nonatomic-lo-hi.h>
7 #include <linux/perf_event.h>
8 #include "../perf_event.h"
10 #define UNCORE_PMU_NAME_LEN 32
11 #define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
12 #define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
14 #define UNCORE_FIXED_EVENT 0xff
15 #define UNCORE_PMC_IDX_MAX_GENERIC 8
16 #define UNCORE_PMC_IDX_MAX_FIXED 1
17 #define UNCORE_PMC_IDX_MAX_FREERUNNING 1
18 #define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
19 #define UNCORE_PMC_IDX_FREERUNNING (UNCORE_PMC_IDX_FIXED + \
20 UNCORE_PMC_IDX_MAX_FIXED)
21 #define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FREERUNNING + \
22 UNCORE_PMC_IDX_MAX_FREERUNNING)
24 #define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \
25 ((dev << 24) | (func << 16) | (type << 8) | idx)
26 #define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) | idx)
27 #define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff)
28 #define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff)
29 #define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
30 #define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
31 #define UNCORE_EXTRA_PCI_DEV 0xff
32 #define UNCORE_EXTRA_PCI_DEV_MAX 4
34 #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
36 struct pci_extra_dev {
37 struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
40 struct intel_uncore_ops;
41 struct intel_uncore_pmu;
42 struct intel_uncore_box;
43 struct uncore_event_desc;
44 struct freerunning_counters;
45 struct intel_uncore_topology;
47 struct intel_uncore_type {
53 int num_freerunning_types;
58 unsigned event_mask_ext;
62 u64 *box_ctls; /* Unit ctrl addr of the first box of each die */
67 unsigned mmio_map_size;
68 unsigned num_shared_regs:8;
69 unsigned single_fixed:1;
70 unsigned pair_ctr_ctl:1;
72 unsigned *msr_offsets;
73 unsigned *pci_offsets;
74 unsigned *mmio_offsets;
77 struct event_constraint unconstrainted;
78 struct event_constraint *constraints;
79 struct intel_uncore_pmu *pmus;
80 struct intel_uncore_ops *ops;
81 struct uncore_event_desc *event_descs;
82 struct freerunning_counters *freerunning;
83 const struct attribute_group *attr_groups[4];
84 const struct attribute_group **attr_update;
85 struct pmu *pmu; /* for custom pmu ops */
87 * Uncore PMU would store relevant platform topology configuration here
88 * to identify which platform component each PMON block of that type is
89 * supposed to monitor.
91 struct intel_uncore_topology *topology;
93 * Optional callbacks for managing mapping of Uncore units to PMONs
95 int (*get_topology)(struct intel_uncore_type *type);
96 int (*set_mapping)(struct intel_uncore_type *type);
97 void (*cleanup_mapping)(struct intel_uncore_type *type);
100 #define pmu_group attr_groups[0]
101 #define format_group attr_groups[1]
102 #define events_group attr_groups[2]
104 struct intel_uncore_ops {
105 void (*init_box)(struct intel_uncore_box *);
106 void (*exit_box)(struct intel_uncore_box *);
107 void (*disable_box)(struct intel_uncore_box *);
108 void (*enable_box)(struct intel_uncore_box *);
109 void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
110 void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
111 u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
112 int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
113 struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
114 struct perf_event *);
115 void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
118 struct intel_uncore_pmu {
120 char name[UNCORE_PMU_NAME_LEN];
124 atomic_t activeboxes;
125 struct intel_uncore_type *type;
126 struct intel_uncore_box **boxes;
129 struct intel_uncore_extra_reg {
131 u64 config, config1, config2;
135 struct intel_uncore_box {
136 int dieid; /* Logical die ID */
137 int n_active; /* number of active events */
139 int cpu; /* cpu to collect events */
142 struct perf_event *events[UNCORE_PMC_IDX_MAX];
143 struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
144 struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
145 unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
146 u64 tags[UNCORE_PMC_IDX_MAX];
147 struct pci_dev *pci_dev;
148 struct intel_uncore_pmu *pmu;
149 u64 hrtimer_duration; /* hrtimer timeout for this box */
150 struct hrtimer hrtimer;
151 struct list_head list;
152 struct list_head active_list;
153 void __iomem *io_addr;
154 struct intel_uncore_extra_reg shared_regs[];
157 /* CFL uncore 8th cbox MSRs */
158 #define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70
159 #define CFL_UNC_CBO_7_PER_CTR0 0xf76
161 #define UNCORE_BOX_FLAG_INITIATED 0
162 /* event config registers are 8-byte apart */
163 #define UNCORE_BOX_FLAG_CTL_OFFS8 1
164 /* CFL 8th CBOX has different MSR space */
165 #define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS 2
167 struct uncore_event_desc {
168 struct device_attribute attr;
172 struct freerunning_counters {
173 unsigned int counter_base;
174 unsigned int counter_offset;
175 unsigned int box_offset;
176 unsigned int num_counters;
178 unsigned *box_offsets;
181 struct intel_uncore_topology {
187 struct list_head list;
189 int pbus_to_dieid[256];
192 struct pci2phy_map *__find_pci2phy_map(int segment);
193 int uncore_pcibus_to_dieid(struct pci_bus *bus);
194 int uncore_die_to_segment(int die);
196 ssize_t uncore_event_show(struct device *dev,
197 struct device_attribute *attr, char *buf);
199 static inline struct intel_uncore_pmu *dev_to_uncore_pmu(struct device *dev)
201 return container_of(dev_get_drvdata(dev), struct intel_uncore_pmu, pmu);
204 #define to_device_attribute(n) container_of(n, struct device_attribute, attr)
205 #define to_dev_ext_attribute(n) container_of(n, struct dev_ext_attribute, attr)
206 #define attr_to_ext_attr(n) to_dev_ext_attribute(to_device_attribute(n))
208 extern int __uncore_max_dies;
209 #define uncore_max_dies() (__uncore_max_dies)
211 #define INTEL_UNCORE_EVENT_DESC(_name, _config) \
213 .attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
217 #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
218 static ssize_t __uncore_##_var##_show(struct device *dev, \
219 struct device_attribute *attr, \
222 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
223 return sprintf(page, _format "\n"); \
225 static struct device_attribute format_attr_##_var = \
226 __ATTR(_name, 0444, __uncore_##_var##_show, NULL)
228 static inline bool uncore_pmc_fixed(int idx)
230 return idx == UNCORE_PMC_IDX_FIXED;
233 static inline bool uncore_pmc_freerunning(int idx)
235 return idx == UNCORE_PMC_IDX_FREERUNNING;
238 static inline bool uncore_mmio_is_valid_offset(struct intel_uncore_box *box,
239 unsigned long offset)
241 if (offset < box->pmu->type->mmio_map_size)
244 pr_warn_once("perf uncore: Invalid offset 0x%lx exceeds mapped area of %s.\n",
245 offset, box->pmu->type->name);
251 unsigned int uncore_mmio_box_ctl(struct intel_uncore_box *box)
253 return box->pmu->type->box_ctl +
254 box->pmu->type->mmio_offset * box->pmu->pmu_idx;
257 static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
259 return box->pmu->type->box_ctl;
262 static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
264 return box->pmu->type->fixed_ctl;
267 static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
269 return box->pmu->type->fixed_ctr;
273 unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
275 if (test_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags))
276 return idx * 8 + box->pmu->type->event_ctl;
278 return idx * 4 + box->pmu->type->event_ctl;
282 unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
284 return idx * 8 + box->pmu->type->perf_ctr;
287 static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
289 struct intel_uncore_pmu *pmu = box->pmu;
290 return pmu->type->msr_offsets ?
291 pmu->type->msr_offsets[pmu->pmu_idx] :
292 pmu->type->msr_offset * pmu->pmu_idx;
295 static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
297 if (!box->pmu->type->box_ctl)
299 return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
302 static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
304 if (!box->pmu->type->fixed_ctl)
306 return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
309 static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
311 return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
316 * In the uncore document, there is no event-code assigned to free running
317 * counters. Some events need to be defined to indicate the free running
318 * counters. The events are encoded as event-code + umask-code.
320 * The event-code for all free running counters is 0xff, which is the same as
321 * the fixed counters.
323 * The umask-code is used to distinguish a fixed counter and a free running
324 * counter, and different types of free running counters.
325 * - For fixed counters, the umask-code is 0x0X.
326 * X indicates the index of the fixed counter, which starts from 0.
327 * - For free running counters, the umask-code uses the rest of the space.
328 * It would bare the format of 0xXY.
329 * X stands for the type of free running counters, which starts from 1.
330 * Y stands for the index of free running counters of same type, which
333 * For example, there are three types of IIO free running counters on Skylake
334 * server, IO CLOCKS counters, BANDWIDTH counters and UTILIZATION counters.
335 * The event-code for all the free running counters is 0xff.
336 * 'ioclk' is the first counter of IO CLOCKS. IO CLOCKS is the first type,
337 * which umask-code starts from 0x10.
338 * So 'ioclk' is encoded as event=0xff,umask=0x10
339 * 'bw_in_port2' is the third counter of BANDWIDTH counters. BANDWIDTH is
340 * the second type, which umask-code starts from 0x20.
341 * So 'bw_in_port2' is encoded as event=0xff,umask=0x22
343 static inline unsigned int uncore_freerunning_idx(u64 config)
345 return ((config >> 8) & 0xf);
348 #define UNCORE_FREERUNNING_UMASK_START 0x10
350 static inline unsigned int uncore_freerunning_type(u64 config)
352 return ((((config >> 8) - UNCORE_FREERUNNING_UMASK_START) >> 4) & 0xf);
356 unsigned int uncore_freerunning_counter(struct intel_uncore_box *box,
357 struct perf_event *event)
359 unsigned int type = uncore_freerunning_type(event->hw.config);
360 unsigned int idx = uncore_freerunning_idx(event->hw.config);
361 struct intel_uncore_pmu *pmu = box->pmu;
363 return pmu->type->freerunning[type].counter_base +
364 pmu->type->freerunning[type].counter_offset * idx +
365 (pmu->type->freerunning[type].box_offsets ?
366 pmu->type->freerunning[type].box_offsets[pmu->pmu_idx] :
367 pmu->type->freerunning[type].box_offset * pmu->pmu_idx);
371 unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
373 if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
374 return CFL_UNC_CBO_7_PERFEVTSEL0 +
375 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
377 return box->pmu->type->event_ctl +
378 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
379 uncore_msr_box_offset(box);
384 unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
386 if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {
387 return CFL_UNC_CBO_7_PER_CTR0 +
388 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);
390 return box->pmu->type->perf_ctr +
391 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
392 uncore_msr_box_offset(box);
397 unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
399 if (box->pci_dev || box->io_addr)
400 return uncore_pci_fixed_ctl(box);
402 return uncore_msr_fixed_ctl(box);
406 unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
408 if (box->pci_dev || box->io_addr)
409 return uncore_pci_fixed_ctr(box);
411 return uncore_msr_fixed_ctr(box);
415 unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
417 if (box->pci_dev || box->io_addr)
418 return uncore_pci_event_ctl(box, idx);
420 return uncore_msr_event_ctl(box, idx);
424 unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
426 if (box->pci_dev || box->io_addr)
427 return uncore_pci_perf_ctr(box, idx);
429 return uncore_msr_perf_ctr(box, idx);
432 static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
434 return box->pmu->type->perf_ctr_bits;
437 static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
439 return box->pmu->type->fixed_ctr_bits;
443 unsigned int uncore_freerunning_bits(struct intel_uncore_box *box,
444 struct perf_event *event)
446 unsigned int type = uncore_freerunning_type(event->hw.config);
448 return box->pmu->type->freerunning[type].bits;
451 static inline int uncore_num_freerunning(struct intel_uncore_box *box,
452 struct perf_event *event)
454 unsigned int type = uncore_freerunning_type(event->hw.config);
456 return box->pmu->type->freerunning[type].num_counters;
459 static inline int uncore_num_freerunning_types(struct intel_uncore_box *box,
460 struct perf_event *event)
462 return box->pmu->type->num_freerunning_types;
465 static inline bool check_valid_freerunning_event(struct intel_uncore_box *box,
466 struct perf_event *event)
468 unsigned int type = uncore_freerunning_type(event->hw.config);
469 unsigned int idx = uncore_freerunning_idx(event->hw.config);
471 return (type < uncore_num_freerunning_types(box, event)) &&
472 (idx < uncore_num_freerunning(box, event));
475 static inline int uncore_num_counters(struct intel_uncore_box *box)
477 return box->pmu->type->num_counters;
480 static inline bool is_freerunning_event(struct perf_event *event)
482 u64 cfg = event->attr.config;
484 return ((cfg & UNCORE_FIXED_EVENT) == UNCORE_FIXED_EVENT) &&
485 (((cfg >> 8) & 0xff) >= UNCORE_FREERUNNING_UMASK_START);
488 /* Check and reject invalid config */
489 static inline int uncore_freerunning_hw_config(struct intel_uncore_box *box,
490 struct perf_event *event)
492 if (is_freerunning_event(event))
498 static inline void uncore_disable_event(struct intel_uncore_box *box,
499 struct perf_event *event)
501 box->pmu->type->ops->disable_event(box, event);
504 static inline void uncore_enable_event(struct intel_uncore_box *box,
505 struct perf_event *event)
507 box->pmu->type->ops->enable_event(box, event);
510 static inline u64 uncore_read_counter(struct intel_uncore_box *box,
511 struct perf_event *event)
513 return box->pmu->type->ops->read_counter(box, event);
516 static inline void uncore_box_init(struct intel_uncore_box *box)
518 if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
519 if (box->pmu->type->ops->init_box)
520 box->pmu->type->ops->init_box(box);
524 static inline void uncore_box_exit(struct intel_uncore_box *box)
526 if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
527 if (box->pmu->type->ops->exit_box)
528 box->pmu->type->ops->exit_box(box);
532 static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
534 return (box->dieid < 0);
537 static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
539 return container_of(event->pmu, struct intel_uncore_pmu, pmu);
542 static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
544 return event->pmu_private;
547 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
548 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
549 void uncore_mmio_exit_box(struct intel_uncore_box *box);
550 u64 uncore_mmio_read_counter(struct intel_uncore_box *box,
551 struct perf_event *event);
552 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
553 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
554 void uncore_pmu_event_start(struct perf_event *event, int flags);
555 void uncore_pmu_event_stop(struct perf_event *event, int flags);
556 int uncore_pmu_event_add(struct perf_event *event, int flags);
557 void uncore_pmu_event_del(struct perf_event *event, int flags);
558 void uncore_pmu_event_read(struct perf_event *event);
559 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
560 struct event_constraint *
561 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
562 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
563 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
565 extern struct intel_uncore_type *empty_uncore[];
566 extern struct intel_uncore_type **uncore_msr_uncores;
567 extern struct intel_uncore_type **uncore_pci_uncores;
568 extern struct intel_uncore_type **uncore_mmio_uncores;
569 extern struct pci_driver *uncore_pci_driver;
570 extern struct pci_driver *uncore_pci_sub_driver;
571 extern raw_spinlock_t pci2phy_map_lock;
572 extern struct list_head pci2phy_map_head;
573 extern struct pci_extra_dev *uncore_extra_pci_dev;
574 extern struct event_constraint uncore_constraint_empty;
577 int snb_uncore_pci_init(void);
578 int ivb_uncore_pci_init(void);
579 int hsw_uncore_pci_init(void);
580 int bdw_uncore_pci_init(void);
581 int skl_uncore_pci_init(void);
582 void snb_uncore_cpu_init(void);
583 void nhm_uncore_cpu_init(void);
584 void skl_uncore_cpu_init(void);
585 void icl_uncore_cpu_init(void);
586 void adl_uncore_cpu_init(void);
587 void tgl_uncore_cpu_init(void);
588 void tgl_uncore_mmio_init(void);
589 void tgl_l_uncore_mmio_init(void);
590 int snb_pci2phy_map_init(int devid);
593 int snbep_uncore_pci_init(void);
594 void snbep_uncore_cpu_init(void);
595 int ivbep_uncore_pci_init(void);
596 void ivbep_uncore_cpu_init(void);
597 int hswep_uncore_pci_init(void);
598 void hswep_uncore_cpu_init(void);
599 int bdx_uncore_pci_init(void);
600 void bdx_uncore_cpu_init(void);
601 int knl_uncore_pci_init(void);
602 void knl_uncore_cpu_init(void);
603 int skx_uncore_pci_init(void);
604 void skx_uncore_cpu_init(void);
605 int snr_uncore_pci_init(void);
606 void snr_uncore_cpu_init(void);
607 void snr_uncore_mmio_init(void);
608 int icx_uncore_pci_init(void);
609 void icx_uncore_cpu_init(void);
610 void icx_uncore_mmio_init(void);
613 void nhmex_uncore_cpu_init(void);