1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel(R) Processor Trace PMU driver for perf
4 * Copyright (c) 2013-2014, Intel Corporation.
6 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
7 * Programming Reference:
8 * http://software.intel.com/en-us/intel-isa-extensions
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/types.h>
16 #include <linux/slab.h>
17 #include <linux/device.h>
19 #include <asm/perf_event.h>
22 #include <asm/intel_pt.h>
23 #include <asm/intel-family.h>
25 #include "../perf_event.h"
28 static DEFINE_PER_CPU(struct pt, pt_ctx);
30 static struct pt_pmu pt_pmu;
33 * Capabilities of Intel PT hardware, such as number of address bits or
34 * supported output schemes, are cached and exported to userspace as "caps"
35 * attribute group of pt pmu device
36 * (/sys/bus/event_source/devices/intel_pt/caps/) so that userspace can store
37 * relevant bits together with intel_pt traces.
39 * These are necessary for both trace decoding (payloads_lip, contains address
40 * width encoded in IP-related packets), and event configuration (bitmasks with
41 * permitted values for certain bit fields).
43 #define PT_CAP(_n, _l, _r, _m) \
44 [PT_CAP_ ## _n] = { .name = __stringify(_n), .leaf = _l, \
45 .reg = _r, .mask = _m }
47 static struct pt_cap_desc {
53 PT_CAP(max_subleaf, 0, CPUID_EAX, 0xffffffff),
54 PT_CAP(cr3_filtering, 0, CPUID_EBX, BIT(0)),
55 PT_CAP(psb_cyc, 0, CPUID_EBX, BIT(1)),
56 PT_CAP(ip_filtering, 0, CPUID_EBX, BIT(2)),
57 PT_CAP(mtc, 0, CPUID_EBX, BIT(3)),
58 PT_CAP(ptwrite, 0, CPUID_EBX, BIT(4)),
59 PT_CAP(power_event_trace, 0, CPUID_EBX, BIT(5)),
60 PT_CAP(topa_output, 0, CPUID_ECX, BIT(0)),
61 PT_CAP(topa_multiple_entries, 0, CPUID_ECX, BIT(1)),
62 PT_CAP(single_range_output, 0, CPUID_ECX, BIT(2)),
63 PT_CAP(output_subsys, 0, CPUID_ECX, BIT(3)),
64 PT_CAP(payloads_lip, 0, CPUID_ECX, BIT(31)),
65 PT_CAP(num_address_ranges, 1, CPUID_EAX, 0x3),
66 PT_CAP(mtc_periods, 1, CPUID_EAX, 0xffff0000),
67 PT_CAP(cycle_thresholds, 1, CPUID_EBX, 0xffff),
68 PT_CAP(psb_periods, 1, CPUID_EBX, 0xffff0000),
71 u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability)
73 struct pt_cap_desc *cd = &pt_caps[capability];
74 u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
75 unsigned int shift = __ffs(cd->mask);
77 return (c & cd->mask) >> shift;
79 EXPORT_SYMBOL_GPL(intel_pt_validate_cap);
81 u32 intel_pt_validate_hw_cap(enum pt_capabilities cap)
83 return intel_pt_validate_cap(pt_pmu.caps, cap);
85 EXPORT_SYMBOL_GPL(intel_pt_validate_hw_cap);
87 static ssize_t pt_cap_show(struct device *cdev,
88 struct device_attribute *attr,
91 struct dev_ext_attribute *ea =
92 container_of(attr, struct dev_ext_attribute, attr);
93 enum pt_capabilities cap = (long)ea->var;
95 return snprintf(buf, PAGE_SIZE, "%x\n", intel_pt_validate_hw_cap(cap));
98 static struct attribute_group pt_cap_group __ro_after_init = {
102 PMU_FORMAT_ATTR(pt, "config:0" );
103 PMU_FORMAT_ATTR(cyc, "config:1" );
104 PMU_FORMAT_ATTR(pwr_evt, "config:4" );
105 PMU_FORMAT_ATTR(fup_on_ptw, "config:5" );
106 PMU_FORMAT_ATTR(mtc, "config:9" );
107 PMU_FORMAT_ATTR(tsc, "config:10" );
108 PMU_FORMAT_ATTR(noretcomp, "config:11" );
109 PMU_FORMAT_ATTR(ptw, "config:12" );
110 PMU_FORMAT_ATTR(branch, "config:13" );
111 PMU_FORMAT_ATTR(mtc_period, "config:14-17" );
112 PMU_FORMAT_ATTR(cyc_thresh, "config:19-22" );
113 PMU_FORMAT_ATTR(psb_period, "config:24-27" );
115 static struct attribute *pt_formats_attr[] = {
116 &format_attr_pt.attr,
117 &format_attr_cyc.attr,
118 &format_attr_pwr_evt.attr,
119 &format_attr_fup_on_ptw.attr,
120 &format_attr_mtc.attr,
121 &format_attr_tsc.attr,
122 &format_attr_noretcomp.attr,
123 &format_attr_ptw.attr,
124 &format_attr_branch.attr,
125 &format_attr_mtc_period.attr,
126 &format_attr_cyc_thresh.attr,
127 &format_attr_psb_period.attr,
131 static struct attribute_group pt_format_group = {
133 .attrs = pt_formats_attr,
137 pt_timing_attr_show(struct device *dev, struct device_attribute *attr,
140 struct perf_pmu_events_attr *pmu_attr =
141 container_of(attr, struct perf_pmu_events_attr, attr);
143 switch (pmu_attr->id) {
145 return sprintf(page, "%lu\n", pt_pmu.max_nonturbo_ratio);
147 return sprintf(page, "%u:%u\n",
157 PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0,
158 pt_timing_attr_show);
159 PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1,
160 pt_timing_attr_show);
162 static struct attribute *pt_timing_attr[] = {
163 &timing_attr_max_nonturbo_ratio.attr.attr,
164 &timing_attr_tsc_art_ratio.attr.attr,
168 static struct attribute_group pt_timing_group = {
169 .attrs = pt_timing_attr,
172 static const struct attribute_group *pt_attr_groups[] = {
179 static int __init pt_pmu_hw_init(void)
181 struct dev_ext_attribute *de_attrs;
182 struct attribute **attrs;
188 rdmsrl(MSR_PLATFORM_INFO, reg);
189 pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8;
192 * if available, read in TSC to core crystal clock ratio,
193 * otherwise, zero for numerator stands for "not enumerated"
196 if (boot_cpu_data.cpuid_level >= CPUID_TSC_LEAF) {
197 u32 eax, ebx, ecx, edx;
199 cpuid(CPUID_TSC_LEAF, &eax, &ebx, &ecx, &edx);
201 pt_pmu.tsc_art_num = ebx;
202 pt_pmu.tsc_art_den = eax;
205 /* model-specific quirks */
206 switch (boot_cpu_data.x86_model) {
207 case INTEL_FAM6_BROADWELL:
208 case INTEL_FAM6_BROADWELL_D:
209 case INTEL_FAM6_BROADWELL_G:
210 case INTEL_FAM6_BROADWELL_X:
211 /* not setting BRANCH_EN will #GP, erratum BDM106 */
212 pt_pmu.branch_en_always_on = true;
218 if (boot_cpu_has(X86_FEATURE_VMX)) {
220 * Intel SDM, 36.5 "Tracing post-VMXON" says that
221 * "IA32_VMX_MISC[bit 14]" being 1 means PT can trace
224 rdmsrl(MSR_IA32_VMX_MISC, reg);
229 for (i = 0; i < PT_CPUID_LEAVES; i++) {
231 &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM],
232 &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM],
233 &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM],
234 &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]);
238 size = sizeof(struct attribute *) * (ARRAY_SIZE(pt_caps)+1);
239 attrs = kzalloc(size, GFP_KERNEL);
243 size = sizeof(struct dev_ext_attribute) * (ARRAY_SIZE(pt_caps)+1);
244 de_attrs = kzalloc(size, GFP_KERNEL);
248 for (i = 0; i < ARRAY_SIZE(pt_caps); i++) {
249 struct dev_ext_attribute *de_attr = de_attrs + i;
251 de_attr->attr.attr.name = pt_caps[i].name;
253 sysfs_attr_init(&de_attr->attr.attr);
255 de_attr->attr.attr.mode = S_IRUGO;
256 de_attr->attr.show = pt_cap_show;
257 de_attr->var = (void *)i;
259 attrs[i] = &de_attr->attr.attr;
262 pt_cap_group.attrs = attrs;
272 #define RTIT_CTL_CYC_PSB (RTIT_CTL_CYCLEACC | \
273 RTIT_CTL_CYC_THRESH | \
276 #define RTIT_CTL_MTC (RTIT_CTL_MTC_EN | \
279 #define RTIT_CTL_PTW (RTIT_CTL_PTW_EN | \
283 * Bit 0 (TraceEn) in the attr.config is meaningless as the
284 * corresponding bit in the RTIT_CTL can only be controlled
285 * by the driver; therefore, repurpose it to mean: pass
286 * through the bit that was previously assumed to be always
287 * on for PT, thereby allowing the user to *not* set it if
288 * they so wish. See also pt_event_valid() and pt_config().
290 #define RTIT_CTL_PASSTHROUGH RTIT_CTL_TRACEEN
292 #define PT_CONFIG_MASK (RTIT_CTL_TRACEEN | \
295 RTIT_CTL_BRANCH_EN | \
298 RTIT_CTL_PWR_EVT_EN | \
299 RTIT_CTL_FUP_ON_PTW | \
302 static bool pt_event_valid(struct perf_event *event)
304 u64 config = event->attr.config;
305 u64 allowed, requested;
307 if ((config & PT_CONFIG_MASK) != config)
310 if (config & RTIT_CTL_CYC_PSB) {
311 if (!intel_pt_validate_hw_cap(PT_CAP_psb_cyc))
314 allowed = intel_pt_validate_hw_cap(PT_CAP_psb_periods);
315 requested = (config & RTIT_CTL_PSB_FREQ) >>
316 RTIT_CTL_PSB_FREQ_OFFSET;
317 if (requested && (!(allowed & BIT(requested))))
320 allowed = intel_pt_validate_hw_cap(PT_CAP_cycle_thresholds);
321 requested = (config & RTIT_CTL_CYC_THRESH) >>
322 RTIT_CTL_CYC_THRESH_OFFSET;
323 if (requested && (!(allowed & BIT(requested))))
327 if (config & RTIT_CTL_MTC) {
329 * In the unlikely case that CPUID lists valid mtc periods,
330 * but not the mtc capability, drop out here.
332 * Spec says that setting mtc period bits while mtc bit in
333 * CPUID is 0 will #GP, so better safe than sorry.
335 if (!intel_pt_validate_hw_cap(PT_CAP_mtc))
338 allowed = intel_pt_validate_hw_cap(PT_CAP_mtc_periods);
342 requested = (config & RTIT_CTL_MTC_RANGE) >>
343 RTIT_CTL_MTC_RANGE_OFFSET;
345 if (!(allowed & BIT(requested)))
349 if (config & RTIT_CTL_PWR_EVT_EN &&
350 !intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
353 if (config & RTIT_CTL_PTW) {
354 if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
357 /* FUPonPTW without PTW doesn't make sense */
358 if ((config & RTIT_CTL_FUP_ON_PTW) &&
359 !(config & RTIT_CTL_PTW_EN))
364 * Setting bit 0 (TraceEn in RTIT_CTL MSR) in the attr.config
365 * clears the assumption that BranchEn must always be enabled,
366 * as was the case with the first implementation of PT.
367 * If this bit is not set, the legacy behavior is preserved
368 * for compatibility with the older userspace.
370 * Re-using bit 0 for this purpose is fine because it is never
371 * directly set by the user; previous attempts at setting it in
372 * the attr.config resulted in -EINVAL.
374 if (config & RTIT_CTL_PASSTHROUGH) {
376 * Disallow not setting BRANCH_EN where BRANCH_EN is
379 if (pt_pmu.branch_en_always_on &&
380 !(config & RTIT_CTL_BRANCH_EN))
384 * Disallow BRANCH_EN without the PASSTHROUGH.
386 if (config & RTIT_CTL_BRANCH_EN)
394 * PT configuration helpers
395 * These all are cpu affine and operate on a local PT
398 static void pt_config_start(struct perf_event *event)
400 struct pt *pt = this_cpu_ptr(&pt_ctx);
401 u64 ctl = event->hw.config;
403 ctl |= RTIT_CTL_TRACEEN;
404 if (READ_ONCE(pt->vmx_on))
405 perf_aux_output_flag(&pt->handle, PERF_AUX_FLAG_PARTIAL);
407 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
409 WRITE_ONCE(event->hw.config, ctl);
412 /* Address ranges and their corresponding msr configuration registers */
413 static const struct pt_address_range {
416 unsigned int reg_off;
417 } pt_address_ranges[] = {
419 .msr_a = MSR_IA32_RTIT_ADDR0_A,
420 .msr_b = MSR_IA32_RTIT_ADDR0_B,
421 .reg_off = RTIT_CTL_ADDR0_OFFSET,
424 .msr_a = MSR_IA32_RTIT_ADDR1_A,
425 .msr_b = MSR_IA32_RTIT_ADDR1_B,
426 .reg_off = RTIT_CTL_ADDR1_OFFSET,
429 .msr_a = MSR_IA32_RTIT_ADDR2_A,
430 .msr_b = MSR_IA32_RTIT_ADDR2_B,
431 .reg_off = RTIT_CTL_ADDR2_OFFSET,
434 .msr_a = MSR_IA32_RTIT_ADDR3_A,
435 .msr_b = MSR_IA32_RTIT_ADDR3_B,
436 .reg_off = RTIT_CTL_ADDR3_OFFSET,
440 static u64 pt_config_filters(struct perf_event *event)
442 struct pt_filters *filters = event->hw.addr_filters;
443 struct pt *pt = this_cpu_ptr(&pt_ctx);
444 unsigned int range = 0;
450 perf_event_addr_filters_sync(event);
452 for (range = 0; range < filters->nr_filters; range++) {
453 struct pt_filter *filter = &filters->filter[range];
456 * Note, if the range has zero start/end addresses due
457 * to its dynamic object not being loaded yet, we just
458 * go ahead and program zeroed range, which will simply
459 * produce no data. Note^2: if executable code at 0x0
460 * is a concern, we can set up an "invalid" configuration
461 * such as msr_b < msr_a.
464 /* avoid redundant msr writes */
465 if (pt->filters.filter[range].msr_a != filter->msr_a) {
466 wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a);
467 pt->filters.filter[range].msr_a = filter->msr_a;
470 if (pt->filters.filter[range].msr_b != filter->msr_b) {
471 wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b);
472 pt->filters.filter[range].msr_b = filter->msr_b;
475 rtit_ctl |= filter->config << pt_address_ranges[range].reg_off;
481 static void pt_config(struct perf_event *event)
483 struct pt *pt = this_cpu_ptr(&pt_ctx);
484 struct pt_buffer *buf = perf_get_aux(&pt->handle);
487 /* First round: clear STATUS, in particular the PSB byte counter. */
488 if (!event->hw.config) {
489 perf_event_itrace_started(event);
490 wrmsrl(MSR_IA32_RTIT_STATUS, 0);
493 reg = pt_config_filters(event);
494 reg |= RTIT_CTL_TRACEEN;
496 reg |= RTIT_CTL_TOPA;
499 * Previously, we had BRANCH_EN on by default, but now that PT has
500 * grown features outside of branch tracing, it is useful to allow
501 * the user to disable it. Setting bit 0 in the event's attr.config
502 * allows BRANCH_EN to pass through instead of being always on. See
503 * also the comment in pt_event_valid().
505 if (event->attr.config & BIT(0)) {
506 reg |= event->attr.config & RTIT_CTL_BRANCH_EN;
508 reg |= RTIT_CTL_BRANCH_EN;
511 if (!event->attr.exclude_kernel)
513 if (!event->attr.exclude_user)
516 reg |= (event->attr.config & PT_CONFIG_MASK);
518 event->hw.config = reg;
519 pt_config_start(event);
522 static void pt_config_stop(struct perf_event *event)
524 struct pt *pt = this_cpu_ptr(&pt_ctx);
525 u64 ctl = READ_ONCE(event->hw.config);
527 /* may be already stopped by a PMI */
528 if (!(ctl & RTIT_CTL_TRACEEN))
531 ctl &= ~RTIT_CTL_TRACEEN;
532 if (!READ_ONCE(pt->vmx_on))
533 wrmsrl(MSR_IA32_RTIT_CTL, ctl);
535 WRITE_ONCE(event->hw.config, ctl);
538 * A wrmsr that disables trace generation serializes other PT
539 * registers and causes all data packets to be written to memory,
540 * but a fence is required for the data to become globally visible.
542 * The below WMB, separating data store and aux_head store matches
543 * the consumer's RMB that separates aux_head load and data load.
549 * struct topa - ToPA metadata
550 * @list: linkage to struct pt_buffer's list of tables
551 * @offset: offset of the first entry in this table in the buffer
552 * @size: total size of all entries in this table
553 * @last: index of the last initialized entry in this table
554 * @z_count: how many times the first entry repeats
557 struct list_head list;
561 unsigned int z_count;
565 * Keep ToPA table-related metadata on the same page as the actual table,
566 * taking up a few words from the top
569 #define TENTS_PER_PAGE \
570 ((PAGE_SIZE - sizeof(struct topa)) / sizeof(struct topa_entry))
573 * struct topa_page - page-sized ToPA table with metadata at the top
574 * @table: actual ToPA table entries, as understood by PT hardware
578 struct topa_entry table[TENTS_PER_PAGE];
582 static inline struct topa_page *topa_to_page(struct topa *topa)
584 return container_of(topa, struct topa_page, topa);
587 static inline struct topa_page *topa_entry_to_page(struct topa_entry *te)
589 return (struct topa_page *)((unsigned long)te & PAGE_MASK);
592 static inline phys_addr_t topa_pfn(struct topa *topa)
594 return PFN_DOWN(virt_to_phys(topa_to_page(topa)));
597 /* make -1 stand for the last table entry */
598 #define TOPA_ENTRY(t, i) \
600 ? &topa_to_page(t)->table[(t)->last] \
601 : &topa_to_page(t)->table[(i)])
602 #define TOPA_ENTRY_SIZE(t, i) (sizes(TOPA_ENTRY((t), (i))->size))
603 #define TOPA_ENTRY_PAGES(t, i) (1 << TOPA_ENTRY((t), (i))->size)
605 static void pt_config_buffer(struct pt_buffer *buf)
607 struct pt *pt = this_cpu_ptr(&pt_ctx);
612 base = buf->data_pages[0];
613 mask = (buf->nr_pages * PAGE_SIZE - 1) >> 7;
615 base = topa_to_page(buf->cur)->table;
616 mask = (u64)buf->cur_idx;
619 reg = virt_to_phys(base);
620 if (pt->output_base != reg) {
621 pt->output_base = reg;
622 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, reg);
625 reg = 0x7f | (mask << 7) | ((u64)buf->output_off << 32);
626 if (pt->output_mask != reg) {
627 pt->output_mask = reg;
628 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg);
633 * topa_alloc() - allocate page-sized ToPA table
634 * @cpu: CPU on which to allocate.
635 * @gfp: Allocation flags.
637 * Return: On success, return the pointer to ToPA table page.
639 static struct topa *topa_alloc(int cpu, gfp_t gfp)
641 int node = cpu_to_node(cpu);
642 struct topa_page *tp;
645 p = alloc_pages_node(node, gfp | __GFP_ZERO, 0);
649 tp = page_address(p);
653 * In case of singe-entry ToPA, always put the self-referencing END
654 * link as the 2nd entry in the table
656 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
657 TOPA_ENTRY(&tp->topa, 1)->base = page_to_phys(p) >> TOPA_SHIFT;
658 TOPA_ENTRY(&tp->topa, 1)->end = 1;
665 * topa_free() - free a page-sized ToPA table
666 * @topa: Table to deallocate.
668 static void topa_free(struct topa *topa)
670 free_page((unsigned long)topa);
674 * topa_insert_table() - insert a ToPA table into a buffer
675 * @buf: PT buffer that's being extended.
676 * @topa: New topa table to be inserted.
678 * If it's the first table in this buffer, set up buffer's pointers
679 * accordingly; otherwise, add a END=1 link entry to @topa to the current
680 * "last" table and adjust the last table pointer to @topa.
682 static void topa_insert_table(struct pt_buffer *buf, struct topa *topa)
684 struct topa *last = buf->last;
686 list_add_tail(&topa->list, &buf->tables);
689 buf->first = buf->last = buf->cur = topa;
693 topa->offset = last->offset + last->size;
696 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
699 BUG_ON(last->last != TENTS_PER_PAGE - 1);
701 TOPA_ENTRY(last, -1)->base = topa_pfn(topa);
702 TOPA_ENTRY(last, -1)->end = 1;
706 * topa_table_full() - check if a ToPA table is filled up
709 static bool topa_table_full(struct topa *topa)
711 /* single-entry ToPA is a special case */
712 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
715 return topa->last == TENTS_PER_PAGE - 1;
719 * topa_insert_pages() - create a list of ToPA tables
720 * @buf: PT buffer being initialized.
721 * @gfp: Allocation flags.
723 * This initializes a list of ToPA tables with entries from
724 * the data_pages provided by rb_alloc_aux().
726 * Return: 0 on success or error code.
728 static int topa_insert_pages(struct pt_buffer *buf, int cpu, gfp_t gfp)
730 struct topa *topa = buf->last;
734 p = virt_to_page(buf->data_pages[buf->nr_pages]);
736 order = page_private(p);
738 if (topa_table_full(topa)) {
739 topa = topa_alloc(cpu, gfp);
743 topa_insert_table(buf, topa);
746 if (topa->z_count == topa->last - 1) {
747 if (order == TOPA_ENTRY(topa, topa->last - 1)->size)
751 TOPA_ENTRY(topa, -1)->base = page_to_phys(p) >> TOPA_SHIFT;
752 TOPA_ENTRY(topa, -1)->size = order;
753 if (!buf->snapshot &&
754 !intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
755 TOPA_ENTRY(topa, -1)->intr = 1;
756 TOPA_ENTRY(topa, -1)->stop = 1;
760 topa->size += sizes(order);
762 buf->nr_pages += 1ul << order;
768 * pt_topa_dump() - print ToPA tables and their entries
771 static void pt_topa_dump(struct pt_buffer *buf)
775 list_for_each_entry(topa, &buf->tables, list) {
776 struct topa_page *tp = topa_to_page(topa);
779 pr_debug("# table @%p, off %llx size %zx\n", tp->table,
780 topa->offset, topa->size);
781 for (i = 0; i < TENTS_PER_PAGE; i++) {
782 pr_debug("# entry @%p (%lx sz %u %c%c%c) raw=%16llx\n",
784 (unsigned long)tp->table[i].base << TOPA_SHIFT,
785 sizes(tp->table[i].size),
786 tp->table[i].end ? 'E' : ' ',
787 tp->table[i].intr ? 'I' : ' ',
788 tp->table[i].stop ? 'S' : ' ',
789 *(u64 *)&tp->table[i]);
790 if ((intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
791 tp->table[i].stop) ||
794 if (!i && topa->z_count)
801 * pt_buffer_advance() - advance to the next output region
804 * Advance the current pointers in the buffer to the next ToPA entry.
806 static void pt_buffer_advance(struct pt_buffer *buf)
811 if (buf->cur_idx == buf->cur->last) {
812 if (buf->cur == buf->last)
813 buf->cur = buf->first;
815 buf->cur = list_entry(buf->cur->list.next, struct topa,
822 * pt_update_head() - calculate current offsets and sizes
823 * @pt: Per-cpu pt context.
825 * Update buffer's current write pointer position and data size.
827 static void pt_update_head(struct pt *pt)
829 struct pt_buffer *buf = perf_get_aux(&pt->handle);
830 u64 topa_idx, base, old;
833 local_set(&buf->data_size, buf->output_off);
837 /* offset of the first region in this table from the beginning of buf */
838 base = buf->cur->offset + buf->output_off;
840 /* offset of the current output region within this table */
841 for (topa_idx = 0; topa_idx < buf->cur_idx; topa_idx++)
842 base += TOPA_ENTRY_SIZE(buf->cur, topa_idx);
845 local_set(&buf->data_size, base);
847 old = (local64_xchg(&buf->head, base) &
848 ((buf->nr_pages << PAGE_SHIFT) - 1));
850 base += buf->nr_pages << PAGE_SHIFT;
852 local_add(base - old, &buf->data_size);
857 * pt_buffer_region() - obtain current output region's address
860 static void *pt_buffer_region(struct pt_buffer *buf)
862 return phys_to_virt(TOPA_ENTRY(buf->cur, buf->cur_idx)->base << TOPA_SHIFT);
866 * pt_buffer_region_size() - obtain current output region's size
869 static size_t pt_buffer_region_size(struct pt_buffer *buf)
871 return TOPA_ENTRY_SIZE(buf->cur, buf->cur_idx);
875 * pt_handle_status() - take care of possible status conditions
876 * @pt: Per-cpu pt context.
878 static void pt_handle_status(struct pt *pt)
880 struct pt_buffer *buf = perf_get_aux(&pt->handle);
884 rdmsrl(MSR_IA32_RTIT_STATUS, status);
886 if (status & RTIT_STATUS_ERROR) {
887 pr_err_ratelimited("ToPA ERROR encountered, trying to recover\n");
889 status &= ~RTIT_STATUS_ERROR;
892 if (status & RTIT_STATUS_STOPPED) {
893 status &= ~RTIT_STATUS_STOPPED;
896 * On systems that only do single-entry ToPA, hitting STOP
897 * means we are already losing data; need to let the decoder
900 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) ||
901 buf->output_off == pt_buffer_region_size(buf)) {
902 perf_aux_output_flag(&pt->handle,
903 PERF_AUX_FLAG_TRUNCATED);
909 * Also on single-entry ToPA implementations, interrupt will come
910 * before the output reaches its output region's boundary.
912 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) &&
914 pt_buffer_region_size(buf) - buf->output_off <= TOPA_PMI_MARGIN) {
915 void *head = pt_buffer_region(buf);
917 /* everything within this margin needs to be zeroed out */
918 memset(head + buf->output_off, 0,
919 pt_buffer_region_size(buf) -
925 pt_buffer_advance(buf);
927 wrmsrl(MSR_IA32_RTIT_STATUS, status);
931 * pt_read_offset() - translate registers into buffer pointers
934 * Set buffer's output pointers from MSR values.
936 static void pt_read_offset(struct pt_buffer *buf)
938 struct pt *pt = this_cpu_ptr(&pt_ctx);
939 struct topa_page *tp;
942 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, pt->output_base);
943 tp = phys_to_virt(pt->output_base);
944 buf->cur = &tp->topa;
947 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, pt->output_mask);
948 /* offset within current output region */
949 buf->output_off = pt->output_mask >> 32;
950 /* index of current output region within this table */
952 buf->cur_idx = (pt->output_mask & 0xffffff80) >> 7;
955 static struct topa_entry *
956 pt_topa_entry_for_page(struct pt_buffer *buf, unsigned int pg)
958 struct topa_page *tp;
960 unsigned int idx, cur_pg = 0, z_pg = 0, start_idx = 0;
963 * Indicates a bug in the caller.
965 if (WARN_ON_ONCE(pg >= buf->nr_pages))
969 * First, find the ToPA table where @pg fits. With high
970 * order allocations, there shouldn't be many of these.
972 list_for_each_entry(topa, &buf->tables, list) {
973 if (topa->offset + topa->size > pg << PAGE_SHIFT)
978 * Hitting this means we have a problem in the ToPA
987 * Indicates a problem in the ToPA allocation code.
989 if (WARN_ON_ONCE(topa->last == -1))
992 tp = topa_to_page(topa);
993 cur_pg = PFN_DOWN(topa->offset);
995 z_pg = TOPA_ENTRY_PAGES(topa, 0) * (topa->z_count + 1);
996 start_idx = topa->z_count + 1;
1000 * Multiple entries at the beginning of the table have the same size,
1001 * ideally all of them; if @pg falls there, the search is done.
1003 if (pg >= cur_pg && pg < cur_pg + z_pg) {
1004 idx = (pg - cur_pg) / TOPA_ENTRY_PAGES(topa, 0);
1005 return &tp->table[idx];
1009 * Otherwise, slow path: iterate through the remaining entries.
1011 for (idx = start_idx, cur_pg += z_pg; idx < topa->last; idx++) {
1012 if (cur_pg + TOPA_ENTRY_PAGES(topa, idx) > pg)
1013 return &tp->table[idx];
1015 cur_pg += TOPA_ENTRY_PAGES(topa, idx);
1019 * Means we couldn't find a ToPA entry in the table that does match.
1026 static struct topa_entry *
1027 pt_topa_prev_entry(struct pt_buffer *buf, struct topa_entry *te)
1029 unsigned long table = (unsigned long)te & ~(PAGE_SIZE - 1);
1030 struct topa_page *tp;
1033 tp = (struct topa_page *)table;
1034 if (tp->table != te)
1038 if (topa == buf->first)
1041 topa = list_prev_entry(topa, list);
1043 tp = topa_to_page(topa);
1045 return &tp->table[topa->last - 1];
1049 * pt_buffer_reset_markers() - place interrupt and stop bits in the buffer
1051 * @handle: Current output handle.
1053 * Place INT and STOP marks to prevent overwriting old data that the consumer
1054 * hasn't yet collected and waking up the consumer after a certain fraction of
1055 * the buffer has filled up. Only needed and sensible for non-snapshot counters.
1057 * This obviously relies on buf::head to figure out buffer markers, so it has
1058 * to be called after pt_buffer_reset_offsets() and before the hardware tracing
1061 static int pt_buffer_reset_markers(struct pt_buffer *buf,
1062 struct perf_output_handle *handle)
1065 unsigned long head = local64_read(&buf->head);
1066 unsigned long idx, npages, wakeup;
1071 /* can't stop in the middle of an output region */
1072 if (buf->output_off + handle->size + 1 < pt_buffer_region_size(buf)) {
1073 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
1078 /* single entry ToPA is handled by marking all regions STOP=1 INT=1 */
1079 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
1082 /* clear STOP and INT from current entry */
1084 buf->stop_te->stop = 0;
1085 buf->stop_te->intr = 0;
1089 buf->intr_te->intr = 0;
1091 /* how many pages till the STOP marker */
1092 npages = handle->size >> PAGE_SHIFT;
1094 /* if it's on a page boundary, fill up one more page */
1095 if (!offset_in_page(head + handle->size + 1))
1098 idx = (head >> PAGE_SHIFT) + npages;
1099 idx &= buf->nr_pages - 1;
1101 if (idx != buf->stop_pos) {
1102 buf->stop_pos = idx;
1103 buf->stop_te = pt_topa_entry_for_page(buf, idx);
1104 buf->stop_te = pt_topa_prev_entry(buf, buf->stop_te);
1107 wakeup = handle->wakeup >> PAGE_SHIFT;
1109 /* in the worst case, wake up the consumer one page before hard stop */
1110 idx = (head >> PAGE_SHIFT) + npages - 1;
1114 idx &= buf->nr_pages - 1;
1115 if (idx != buf->intr_pos) {
1116 buf->intr_pos = idx;
1117 buf->intr_te = pt_topa_entry_for_page(buf, idx);
1118 buf->intr_te = pt_topa_prev_entry(buf, buf->intr_te);
1121 buf->stop_te->stop = 1;
1122 buf->stop_te->intr = 1;
1123 buf->intr_te->intr = 1;
1129 * pt_buffer_reset_offsets() - adjust buffer's write pointers from aux_head
1131 * @head: Write pointer (aux_head) from AUX buffer.
1133 * Find the ToPA table and entry corresponding to given @head and set buffer's
1134 * "current" pointers accordingly. This is done after we have obtained the
1135 * current aux_head position from a successful call to perf_aux_output_begin()
1136 * to make sure the hardware is writing to the right place.
1138 * This function modifies buf::{cur,cur_idx,output_off} that will be programmed
1139 * into PT msrs when the tracing is enabled and buf::head and buf::data_size,
1140 * which are used to determine INT and STOP markers' locations by a subsequent
1141 * call to pt_buffer_reset_markers().
1143 static void pt_buffer_reset_offsets(struct pt_buffer *buf, unsigned long head)
1145 struct topa_page *cur_tp;
1146 struct topa_entry *te;
1150 head &= (buf->nr_pages << PAGE_SHIFT) - 1;
1153 pg = (head >> PAGE_SHIFT) & (buf->nr_pages - 1);
1154 te = pt_topa_entry_for_page(buf, pg);
1156 cur_tp = topa_entry_to_page(te);
1157 buf->cur = &cur_tp->topa;
1158 buf->cur_idx = te - TOPA_ENTRY(buf->cur, 0);
1159 buf->output_off = head & (pt_buffer_region_size(buf) - 1);
1161 buf->output_off = head;
1164 local64_set(&buf->head, head);
1165 local_set(&buf->data_size, 0);
1169 * pt_buffer_fini_topa() - deallocate ToPA structure of a buffer
1172 static void pt_buffer_fini_topa(struct pt_buffer *buf)
1174 struct topa *topa, *iter;
1179 list_for_each_entry_safe(topa, iter, &buf->tables, list) {
1181 * right now, this is in free_aux() path only, so
1182 * no need to unlink this table from the list
1189 * pt_buffer_init_topa() - initialize ToPA table for pt buffer
1191 * @size: Total size of all regions within this ToPA.
1192 * @gfp: Allocation flags.
1194 static int pt_buffer_init_topa(struct pt_buffer *buf, int cpu,
1195 unsigned long nr_pages, gfp_t gfp)
1200 topa = topa_alloc(cpu, gfp);
1204 topa_insert_table(buf, topa);
1206 while (buf->nr_pages < nr_pages) {
1207 err = topa_insert_pages(buf, cpu, gfp);
1209 pt_buffer_fini_topa(buf);
1214 /* link last table to the first one, unless we're double buffering */
1215 if (intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries)) {
1216 TOPA_ENTRY(buf->last, -1)->base = topa_pfn(buf->first);
1217 TOPA_ENTRY(buf->last, -1)->end = 1;
1224 static int pt_buffer_try_single(struct pt_buffer *buf, int nr_pages)
1226 struct page *p = virt_to_page(buf->data_pages[0]);
1227 int ret = -ENOTSUPP, order = 0;
1230 * We can use single range output mode
1231 * + in snapshot mode, where we don't need interrupts;
1232 * + if the hardware supports it;
1233 * + if the entire buffer is one contiguous allocation.
1238 if (!intel_pt_validate_hw_cap(PT_CAP_single_range_output))
1242 order = page_private(p);
1244 if (1 << order != nr_pages)
1248 buf->nr_pages = nr_pages;
1255 * pt_buffer_setup_aux() - set up topa tables for a PT buffer
1256 * @cpu: Cpu on which to allocate, -1 means current.
1257 * @pages: Array of pointers to buffer pages passed from perf core.
1258 * @nr_pages: Number of pages in the buffer.
1259 * @snapshot: If this is a snapshot/overwrite counter.
1261 * This is a pmu::setup_aux callback that sets up ToPA tables and all the
1262 * bookkeeping for an AUX buffer.
1264 * Return: Our private PT buffer structure.
1267 pt_buffer_setup_aux(struct perf_event *event, void **pages,
1268 int nr_pages, bool snapshot)
1270 struct pt_buffer *buf;
1271 int node, ret, cpu = event->cpu;
1277 * Only support AUX sampling in snapshot mode, where we don't
1280 if (event->attr.aux_sample_size && !snapshot)
1284 cpu = raw_smp_processor_id();
1285 node = cpu_to_node(cpu);
1287 buf = kzalloc_node(sizeof(struct pt_buffer), GFP_KERNEL, node);
1291 buf->snapshot = snapshot;
1292 buf->data_pages = pages;
1296 INIT_LIST_HEAD(&buf->tables);
1298 ret = pt_buffer_try_single(buf, nr_pages);
1302 ret = pt_buffer_init_topa(buf, cpu, nr_pages, GFP_KERNEL);
1312 * pt_buffer_free_aux() - perf AUX deallocation path callback
1315 static void pt_buffer_free_aux(void *data)
1317 struct pt_buffer *buf = data;
1319 pt_buffer_fini_topa(buf);
1323 static int pt_addr_filters_init(struct perf_event *event)
1325 struct pt_filters *filters;
1326 int node = event->cpu == -1 ? -1 : cpu_to_node(event->cpu);
1328 if (!intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1331 filters = kzalloc_node(sizeof(struct pt_filters), GFP_KERNEL, node);
1336 memcpy(filters, event->parent->hw.addr_filters,
1339 event->hw.addr_filters = filters;
1344 static void pt_addr_filters_fini(struct perf_event *event)
1346 kfree(event->hw.addr_filters);
1347 event->hw.addr_filters = NULL;
1350 static inline bool valid_kernel_ip(unsigned long ip)
1352 return virt_addr_valid(ip) && kernel_ip(ip);
1355 static int pt_event_addr_filters_validate(struct list_head *filters)
1357 struct perf_addr_filter *filter;
1360 list_for_each_entry(filter, filters, entry) {
1362 * PT doesn't support single address triggers and
1365 if (!filter->size ||
1366 filter->action == PERF_ADDR_FILTER_ACTION_START)
1369 if (!filter->path.dentry) {
1370 if (!valid_kernel_ip(filter->offset))
1373 if (!valid_kernel_ip(filter->offset + filter->size))
1377 if (++range > intel_pt_validate_hw_cap(PT_CAP_num_address_ranges))
1384 static void pt_event_addr_filters_sync(struct perf_event *event)
1386 struct perf_addr_filters_head *head = perf_event_addr_filters(event);
1387 unsigned long msr_a, msr_b;
1388 struct perf_addr_filter_range *fr = event->addr_filter_ranges;
1389 struct pt_filters *filters = event->hw.addr_filters;
1390 struct perf_addr_filter *filter;
1396 list_for_each_entry(filter, &head->list, entry) {
1397 if (filter->path.dentry && !fr[range].start) {
1400 /* apply the offset */
1401 msr_a = fr[range].start;
1402 msr_b = msr_a + fr[range].size - 1;
1405 filters->filter[range].msr_a = msr_a;
1406 filters->filter[range].msr_b = msr_b;
1407 if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER)
1408 filters->filter[range].config = 1;
1410 filters->filter[range].config = 2;
1414 filters->nr_filters = range;
1418 * intel_pt_interrupt() - PT PMI handler
1420 void intel_pt_interrupt(void)
1422 struct pt *pt = this_cpu_ptr(&pt_ctx);
1423 struct pt_buffer *buf;
1424 struct perf_event *event = pt->handle.event;
1427 * There may be a dangling PT bit in the interrupt status register
1428 * after PT has been disabled by pt_event_stop(). Make sure we don't
1429 * do anything (particularly, re-enable) for this event here.
1431 if (!READ_ONCE(pt->handle_nmi))
1437 pt_config_stop(event);
1439 buf = perf_get_aux(&pt->handle);
1443 pt_read_offset(buf);
1445 pt_handle_status(pt);
1449 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
1451 if (!event->hw.state) {
1454 buf = perf_aux_output_begin(&pt->handle, event);
1456 event->hw.state = PERF_HES_STOPPED;
1460 pt_buffer_reset_offsets(buf, pt->handle.head);
1461 /* snapshot counters don't use PMI, so it's safe */
1462 ret = pt_buffer_reset_markers(buf, &pt->handle);
1464 perf_aux_output_end(&pt->handle, 0);
1468 pt_config_buffer(buf);
1469 pt_config_start(event);
1473 void intel_pt_handle_vmx(int on)
1475 struct pt *pt = this_cpu_ptr(&pt_ctx);
1476 struct perf_event *event;
1477 unsigned long flags;
1479 /* PT plays nice with VMX, do nothing */
1484 * VMXON will clear RTIT_CTL.TraceEn; we need to make
1485 * sure to not try to set it while VMX is on. Disable
1486 * interrupts to avoid racing with pmu callbacks;
1487 * concurrent PMI should be handled fine.
1489 local_irq_save(flags);
1490 WRITE_ONCE(pt->vmx_on, on);
1493 * If an AUX transaction is in progress, it will contain
1494 * gap(s), so flag it PARTIAL to inform the user.
1496 event = pt->handle.event;
1498 perf_aux_output_flag(&pt->handle,
1499 PERF_AUX_FLAG_PARTIAL);
1501 /* Turn PTs back on */
1503 wrmsrl(MSR_IA32_RTIT_CTL, event->hw.config);
1505 local_irq_restore(flags);
1507 EXPORT_SYMBOL_GPL(intel_pt_handle_vmx);
1513 static void pt_event_start(struct perf_event *event, int mode)
1515 struct hw_perf_event *hwc = &event->hw;
1516 struct pt *pt = this_cpu_ptr(&pt_ctx);
1517 struct pt_buffer *buf;
1519 buf = perf_aux_output_begin(&pt->handle, event);
1523 pt_buffer_reset_offsets(buf, pt->handle.head);
1524 if (!buf->snapshot) {
1525 if (pt_buffer_reset_markers(buf, &pt->handle))
1529 WRITE_ONCE(pt->handle_nmi, 1);
1532 pt_config_buffer(buf);
1538 perf_aux_output_end(&pt->handle, 0);
1540 hwc->state = PERF_HES_STOPPED;
1543 static void pt_event_stop(struct perf_event *event, int mode)
1545 struct pt *pt = this_cpu_ptr(&pt_ctx);
1548 * Protect against the PMI racing with disabling wrmsr,
1549 * see comment in intel_pt_interrupt().
1551 WRITE_ONCE(pt->handle_nmi, 0);
1553 pt_config_stop(event);
1555 if (event->hw.state == PERF_HES_STOPPED)
1558 event->hw.state = PERF_HES_STOPPED;
1560 if (mode & PERF_EF_UPDATE) {
1561 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1566 if (WARN_ON_ONCE(pt->handle.event != event))
1569 pt_read_offset(buf);
1571 pt_handle_status(pt);
1577 local_xchg(&buf->data_size,
1578 buf->nr_pages << PAGE_SHIFT);
1579 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0));
1583 static long pt_event_snapshot_aux(struct perf_event *event,
1584 struct perf_output_handle *handle,
1587 struct pt *pt = this_cpu_ptr(&pt_ctx);
1588 struct pt_buffer *buf = perf_get_aux(&pt->handle);
1589 unsigned long from = 0, to;
1592 if (WARN_ON_ONCE(!buf))
1596 * Sampling is only allowed on snapshot events;
1597 * see pt_buffer_setup_aux().
1599 if (WARN_ON_ONCE(!buf->snapshot))
1603 * Here, handle_nmi tells us if the tracing is on
1605 if (READ_ONCE(pt->handle_nmi))
1606 pt_config_stop(event);
1608 pt_read_offset(buf);
1611 to = local_read(&buf->data_size);
1613 from = buf->nr_pages << PAGE_SHIFT;
1616 ret = perf_output_copy_aux(&pt->handle, handle, from, to);
1619 * If the tracing was on when we turned up, restart it.
1620 * Compiler barrier not needed as we couldn't have been
1621 * preempted by anything that touches pt->handle_nmi.
1624 pt_config_start(event);
1629 static void pt_event_del(struct perf_event *event, int mode)
1631 pt_event_stop(event, PERF_EF_UPDATE);
1634 static int pt_event_add(struct perf_event *event, int mode)
1636 struct pt *pt = this_cpu_ptr(&pt_ctx);
1637 struct hw_perf_event *hwc = &event->hw;
1640 if (pt->handle.event)
1643 if (mode & PERF_EF_START) {
1644 pt_event_start(event, 0);
1646 if (hwc->state == PERF_HES_STOPPED)
1649 hwc->state = PERF_HES_STOPPED;
1658 static void pt_event_read(struct perf_event *event)
1662 static void pt_event_destroy(struct perf_event *event)
1664 pt_addr_filters_fini(event);
1665 x86_del_exclusive(x86_lbr_exclusive_pt);
1668 static int pt_event_init(struct perf_event *event)
1670 if (event->attr.type != pt_pmu.pmu.type)
1673 if (!pt_event_valid(event))
1676 if (x86_add_exclusive(x86_lbr_exclusive_pt))
1679 if (pt_addr_filters_init(event)) {
1680 x86_del_exclusive(x86_lbr_exclusive_pt);
1684 event->destroy = pt_event_destroy;
1689 void cpu_emergency_stop_pt(void)
1691 struct pt *pt = this_cpu_ptr(&pt_ctx);
1693 if (pt->handle.event)
1694 pt_event_stop(pt->handle.event, PERF_EF_UPDATE);
1697 int is_intel_pt_event(struct perf_event *event)
1699 return event->pmu == &pt_pmu.pmu;
1702 static __init int pt_init(void)
1704 int ret, cpu, prior_warn = 0;
1706 BUILD_BUG_ON(sizeof(struct topa) > PAGE_SIZE);
1708 if (!boot_cpu_has(X86_FEATURE_INTEL_PT))
1712 for_each_online_cpu(cpu) {
1715 ret = rdmsrl_safe_on_cpu(cpu, MSR_IA32_RTIT_CTL, &ctl);
1716 if (!ret && (ctl & RTIT_CTL_TRACEEN))
1722 x86_add_exclusive(x86_lbr_exclusive_pt);
1723 pr_warn("PT is enabled at boot time, doing nothing\n");
1728 ret = pt_pmu_hw_init();
1732 if (!intel_pt_validate_hw_cap(PT_CAP_topa_output)) {
1733 pr_warn("ToPA output is not supported on this CPU\n");
1737 if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries))
1738 pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG;
1740 pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE;
1741 pt_pmu.pmu.attr_groups = pt_attr_groups;
1742 pt_pmu.pmu.task_ctx_nr = perf_sw_context;
1743 pt_pmu.pmu.event_init = pt_event_init;
1744 pt_pmu.pmu.add = pt_event_add;
1745 pt_pmu.pmu.del = pt_event_del;
1746 pt_pmu.pmu.start = pt_event_start;
1747 pt_pmu.pmu.stop = pt_event_stop;
1748 pt_pmu.pmu.snapshot_aux = pt_event_snapshot_aux;
1749 pt_pmu.pmu.read = pt_event_read;
1750 pt_pmu.pmu.setup_aux = pt_buffer_setup_aux;
1751 pt_pmu.pmu.free_aux = pt_buffer_free_aux;
1752 pt_pmu.pmu.addr_filters_sync = pt_event_addr_filters_sync;
1753 pt_pmu.pmu.addr_filters_validate = pt_event_addr_filters_validate;
1754 pt_pmu.pmu.nr_addr_filters =
1755 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges);
1757 ret = perf_pmu_register(&pt_pmu.pmu, "intel_pt", -1);
1761 arch_initcall(pt_init);