1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/perf_event.h>
3 #include <linux/types.h>
5 #include <asm/perf_event.h>
9 #include "../perf_event.h"
13 LBR_FORMAT_LIP = 0x01,
14 LBR_FORMAT_EIP = 0x02,
15 LBR_FORMAT_EIP_FLAGS = 0x03,
16 LBR_FORMAT_EIP_FLAGS2 = 0x04,
17 LBR_FORMAT_INFO = 0x05,
18 LBR_FORMAT_TIME = 0x06,
19 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
25 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
26 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
27 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
31 * Intel LBR_SELECT bits
32 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
34 * Hardware branch filter (not available on all CPUs)
36 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
37 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
38 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
39 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
40 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
41 #define LBR_RETURN_BIT 5 /* do not capture near returns */
42 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
43 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
44 #define LBR_FAR_BIT 8 /* do not capture far branches */
45 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
48 * Following bit only exists in Linux; we mask it out before writing it to
49 * the actual MSR. But it helps the constraint perf code to understand
50 * that this is a separate configuration.
52 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */
54 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
55 #define LBR_USER (1 << LBR_USER_BIT)
56 #define LBR_JCC (1 << LBR_JCC_BIT)
57 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
58 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
59 #define LBR_RETURN (1 << LBR_RETURN_BIT)
60 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
61 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
62 #define LBR_FAR (1 << LBR_FAR_BIT)
63 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
64 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT)
66 #define LBR_PLM (LBR_KERNEL | LBR_USER)
68 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
69 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
70 #define LBR_IGN 0 /* ignored */
81 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
82 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
83 #define LBR_FROM_FLAG_ABORT BIT_ULL(61)
85 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
88 * x86control flow change classification
89 * x86control flow changes include branches, interrupts, traps, faults
92 X86_BR_NONE = 0, /* unknown */
94 X86_BR_USER = 1 << 0, /* branch target is user */
95 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
97 X86_BR_CALL = 1 << 2, /* call */
98 X86_BR_RET = 1 << 3, /* return */
99 X86_BR_SYSCALL = 1 << 4, /* syscall */
100 X86_BR_SYSRET = 1 << 5, /* syscall return */
101 X86_BR_INT = 1 << 6, /* sw interrupt */
102 X86_BR_IRET = 1 << 7, /* return from interrupt */
103 X86_BR_JCC = 1 << 8, /* conditional */
104 X86_BR_JMP = 1 << 9, /* jump */
105 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
106 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
107 X86_BR_ABORT = 1 << 12,/* transaction abort */
108 X86_BR_IN_TX = 1 << 13,/* in transaction */
109 X86_BR_NO_TX = 1 << 14,/* not in transaction */
110 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
111 X86_BR_CALL_STACK = 1 << 16,/* call stack */
112 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
114 X86_BR_TYPE_SAVE = 1 << 18,/* indicate to save branch type */
118 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
119 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
136 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
138 #define X86_BR_ANY_CALL \
146 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
149 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
150 * otherwise it becomes near impossible to get a reliable stack.
153 static void __intel_pmu_lbr_enable(bool pmi)
155 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
156 u64 debugctl, lbr_select = 0, orig_debugctl;
159 * No need to unfreeze manually, as v4 can do that as part
160 * of the GLOBAL_STATUS ack.
162 if (pmi && x86_pmu.version >= 4)
166 * No need to reprogram LBR_SELECT in a PMI, as it
170 lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
171 if (!pmi && cpuc->lbr_sel)
172 wrmsrl(MSR_LBR_SELECT, lbr_select);
174 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
175 orig_debugctl = debugctl;
176 debugctl |= DEBUGCTLMSR_LBR;
178 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
179 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
180 * may cause superfluous increase/decrease of LBR_TOS.
182 if (!(lbr_select & LBR_CALL_STACK))
183 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
184 if (orig_debugctl != debugctl)
185 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
188 static void __intel_pmu_lbr_disable(void)
192 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
193 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
194 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
197 static void intel_pmu_lbr_reset_32(void)
201 for (i = 0; i < x86_pmu.lbr_nr; i++)
202 wrmsrl(x86_pmu.lbr_from + i, 0);
205 static void intel_pmu_lbr_reset_64(void)
209 for (i = 0; i < x86_pmu.lbr_nr; i++) {
210 wrmsrl(x86_pmu.lbr_from + i, 0);
211 wrmsrl(x86_pmu.lbr_to + i, 0);
212 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
213 wrmsrl(MSR_LBR_INFO_0 + i, 0);
217 void intel_pmu_lbr_reset(void)
222 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
223 intel_pmu_lbr_reset_32();
225 intel_pmu_lbr_reset_64();
229 * TOS = most recently recorded branch
231 static inline u64 intel_pmu_lbr_tos(void)
235 rdmsrl(x86_pmu.lbr_tos, tos);
245 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
246 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
247 * TSX is not supported they have no consistent behavior:
249 * - For wrmsr(), bits 61:62 are considered part of the sign extension.
250 * - For HW updates (branch captures) bits 61:62 are always OFF and are not
251 * part of the sign extension.
255 * 1) LBR has TSX format
256 * 2) CPU has no TSX support enabled
258 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any
259 * value from rdmsr() must be converted to have a 61 bits sign extension,
260 * ignoring the TSX flags.
262 static inline bool lbr_from_signext_quirk_needed(void)
264 int lbr_format = x86_pmu.intel_cap.lbr_format;
265 bool tsx_support = boot_cpu_has(X86_FEATURE_HLE) ||
266 boot_cpu_has(X86_FEATURE_RTM);
268 return !tsx_support && (lbr_desc[lbr_format] & LBR_TSX);
271 DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key);
273 /* If quirk is enabled, ensure sign extension is 63 bits: */
274 inline u64 lbr_from_signext_quirk_wr(u64 val)
276 if (static_branch_unlikely(&lbr_from_quirk_key)) {
278 * Sign extend into bits 61:62 while preserving bit 63.
280 * Quirk is enabled when TSX is disabled. Therefore TSX bits
281 * in val are always OFF and must be changed to be sign
282 * extension bits. Since bits 59:60 are guaranteed to be
283 * part of the sign extension bits, we can just copy them
286 val |= (LBR_FROM_SIGNEXT_2MSB & val) << 2;
292 * If quirk is needed, ensure sign extension is 61 bits:
294 static u64 lbr_from_signext_quirk_rd(u64 val)
296 if (static_branch_unlikely(&lbr_from_quirk_key)) {
298 * Quirk is on when TSX is not enabled. Therefore TSX
299 * flags must be read as OFF.
301 val &= ~(LBR_FROM_FLAG_IN_TX | LBR_FROM_FLAG_ABORT);
306 static inline void wrlbr_from(unsigned int idx, u64 val)
308 val = lbr_from_signext_quirk_wr(val);
309 wrmsrl(x86_pmu.lbr_from + idx, val);
312 static inline void wrlbr_to(unsigned int idx, u64 val)
314 wrmsrl(x86_pmu.lbr_to + idx, val);
317 static inline u64 rdlbr_from(unsigned int idx)
321 rdmsrl(x86_pmu.lbr_from + idx, val);
323 return lbr_from_signext_quirk_rd(val);
326 static inline u64 rdlbr_to(unsigned int idx)
330 rdmsrl(x86_pmu.lbr_to + idx, val);
335 static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
338 unsigned lbr_idx, mask;
341 if (task_ctx->lbr_callstack_users == 0 ||
342 task_ctx->lbr_stack_state == LBR_NONE) {
343 intel_pmu_lbr_reset();
347 mask = x86_pmu.lbr_nr - 1;
349 for (i = 0; i < tos; i++) {
350 lbr_idx = (tos - i) & mask;
351 wrlbr_from(lbr_idx, task_ctx->lbr_from[i]);
352 wrlbr_to (lbr_idx, task_ctx->lbr_to[i]);
354 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
355 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
357 wrmsrl(x86_pmu.lbr_tos, tos);
358 task_ctx->lbr_stack_state = LBR_NONE;
361 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
363 unsigned lbr_idx, mask;
367 if (task_ctx->lbr_callstack_users == 0) {
368 task_ctx->lbr_stack_state = LBR_NONE;
372 mask = x86_pmu.lbr_nr - 1;
373 tos = intel_pmu_lbr_tos();
374 for (i = 0; i < tos; i++) {
375 lbr_idx = (tos - i) & mask;
376 task_ctx->lbr_from[i] = rdlbr_from(lbr_idx);
377 task_ctx->lbr_to[i] = rdlbr_to(lbr_idx);
378 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
379 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
382 task_ctx->lbr_stack_state = LBR_VALID;
385 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
387 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
388 struct x86_perf_task_context *task_ctx;
390 if (!cpuc->lbr_users)
394 * If LBR callstack feature is enabled and the stack was saved when
395 * the task was scheduled out, restore the stack. Otherwise flush
398 task_ctx = ctx ? ctx->task_ctx_data : NULL;
401 __intel_pmu_lbr_restore(task_ctx);
403 __intel_pmu_lbr_save(task_ctx);
408 * Since a context switch can flip the address space and LBR entries
409 * are not tagged with an identifier, we need to wipe the LBR, even for
410 * per-cpu events. You simply cannot resolve the branches from the old
414 intel_pmu_lbr_reset();
417 static inline bool branch_user_callstack(unsigned br_sel)
419 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK);
422 void intel_pmu_lbr_add(struct perf_event *event)
424 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
425 struct x86_perf_task_context *task_ctx;
430 cpuc->br_sel = event->hw.branch_reg.reg;
432 if (branch_user_callstack(cpuc->br_sel) && event->ctx->task_ctx_data) {
433 task_ctx = event->ctx->task_ctx_data;
434 task_ctx->lbr_callstack_users++;
438 * Request pmu::sched_task() callback, which will fire inside the
439 * regular perf event scheduling, so that call will:
441 * - restore or wipe; when LBR-callstack,
444 * when this is from __perf_event_task_sched_in().
446 * However, if this is from perf_install_in_context(), no such callback
447 * will follow and we'll need to reset the LBR here if this is the
450 * The problem is, we cannot tell these cases apart... but we can
451 * exclude the biggest chunk of cases by looking at
452 * event->total_time_running. An event that has accrued runtime cannot
453 * be 'new'. Conversely, a new event can get installed through the
454 * context switch path for the first time.
456 perf_sched_cb_inc(event->ctx->pmu);
457 if (!cpuc->lbr_users++ && !event->total_time_running)
458 intel_pmu_lbr_reset();
461 void intel_pmu_lbr_del(struct perf_event *event)
463 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
464 struct x86_perf_task_context *task_ctx;
469 if (branch_user_callstack(cpuc->br_sel) &&
470 event->ctx->task_ctx_data) {
471 task_ctx = event->ctx->task_ctx_data;
472 task_ctx->lbr_callstack_users--;
476 WARN_ON_ONCE(cpuc->lbr_users < 0);
477 perf_sched_cb_dec(event->ctx->pmu);
480 void intel_pmu_lbr_enable_all(bool pmi)
482 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
485 __intel_pmu_lbr_enable(pmi);
488 void intel_pmu_lbr_disable_all(void)
490 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
493 __intel_pmu_lbr_disable();
496 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
498 unsigned long mask = x86_pmu.lbr_nr - 1;
499 u64 tos = intel_pmu_lbr_tos();
502 for (i = 0; i < x86_pmu.lbr_nr; i++) {
503 unsigned long lbr_idx = (tos - i) & mask;
512 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
514 cpuc->lbr_entries[i].from = msr_lastbranch.from;
515 cpuc->lbr_entries[i].to = msr_lastbranch.to;
516 cpuc->lbr_entries[i].mispred = 0;
517 cpuc->lbr_entries[i].predicted = 0;
518 cpuc->lbr_entries[i].in_tx = 0;
519 cpuc->lbr_entries[i].abort = 0;
520 cpuc->lbr_entries[i].cycles = 0;
521 cpuc->lbr_entries[i].type = 0;
522 cpuc->lbr_entries[i].reserved = 0;
524 cpuc->lbr_stack.nr = i;
528 * Due to lack of segmentation in Linux the effective address (offset)
529 * is the same as the linear address, allowing us to merge the LIP and EIP
532 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
534 bool need_info = false;
535 unsigned long mask = x86_pmu.lbr_nr - 1;
536 int lbr_format = x86_pmu.intel_cap.lbr_format;
537 u64 tos = intel_pmu_lbr_tos();
540 int num = x86_pmu.lbr_nr;
543 need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
544 if (cpuc->lbr_sel->config & LBR_CALL_STACK)
548 for (i = 0; i < num; i++) {
549 unsigned long lbr_idx = (tos - i) & mask;
550 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
553 int lbr_flags = lbr_desc[lbr_format];
555 from = rdlbr_from(lbr_idx);
556 to = rdlbr_to(lbr_idx);
558 if (lbr_format == LBR_FORMAT_INFO && need_info) {
561 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info);
562 mis = !!(info & LBR_INFO_MISPRED);
564 in_tx = !!(info & LBR_INFO_IN_TX);
565 abort = !!(info & LBR_INFO_ABORT);
566 cycles = (info & LBR_INFO_CYCLES);
569 if (lbr_format == LBR_FORMAT_TIME) {
570 mis = !!(from & LBR_FROM_FLAG_MISPRED);
573 cycles = ((to >> 48) & LBR_INFO_CYCLES);
575 to = (u64)((((s64)to) << 16) >> 16);
578 if (lbr_flags & LBR_EIP_FLAGS) {
579 mis = !!(from & LBR_FROM_FLAG_MISPRED);
583 if (lbr_flags & LBR_TSX) {
584 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
585 abort = !!(from & LBR_FROM_FLAG_ABORT);
588 from = (u64)((((s64)from) << skip) >> skip);
591 * Some CPUs report duplicated abort records,
592 * with the second entry not having an abort bit set.
593 * Skip them here. This loop runs backwards,
594 * so we need to undo the previous record.
595 * If the abort just happened outside the window
596 * the extra entry cannot be removed.
598 if (abort && x86_pmu.lbr_double_abort && out > 0)
601 cpuc->lbr_entries[out].from = from;
602 cpuc->lbr_entries[out].to = to;
603 cpuc->lbr_entries[out].mispred = mis;
604 cpuc->lbr_entries[out].predicted = pred;
605 cpuc->lbr_entries[out].in_tx = in_tx;
606 cpuc->lbr_entries[out].abort = abort;
607 cpuc->lbr_entries[out].cycles = cycles;
608 cpuc->lbr_entries[out].type = 0;
609 cpuc->lbr_entries[out].reserved = 0;
612 cpuc->lbr_stack.nr = out;
615 void intel_pmu_lbr_read(void)
617 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
619 if (!cpuc->lbr_users)
622 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
623 intel_pmu_lbr_read_32(cpuc);
625 intel_pmu_lbr_read_64(cpuc);
627 intel_pmu_lbr_filter(cpuc);
632 * - in case there is no HW filter
633 * - in case the HW filter has errata or limitations
635 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
637 u64 br_type = event->attr.branch_sample_type;
640 if (br_type & PERF_SAMPLE_BRANCH_USER)
643 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
644 mask |= X86_BR_KERNEL;
646 /* we ignore BRANCH_HV here */
648 if (br_type & PERF_SAMPLE_BRANCH_ANY)
651 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
652 mask |= X86_BR_ANY_CALL;
654 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
655 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
657 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
658 mask |= X86_BR_IND_CALL;
660 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
661 mask |= X86_BR_ABORT;
663 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
664 mask |= X86_BR_IN_TX;
666 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
667 mask |= X86_BR_NO_TX;
669 if (br_type & PERF_SAMPLE_BRANCH_COND)
672 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) {
673 if (!x86_pmu_has_lbr_callstack())
675 if (mask & ~(X86_BR_USER | X86_BR_KERNEL))
677 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET |
681 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP)
682 mask |= X86_BR_IND_JMP;
684 if (br_type & PERF_SAMPLE_BRANCH_CALL)
685 mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
687 if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE)
688 mask |= X86_BR_TYPE_SAVE;
691 * stash actual user request into reg, it may
692 * be used by fixup code for some CPU
694 event->hw.branch_reg.reg = mask;
699 * setup the HW LBR filter
700 * Used only when available, may not be enough to disambiguate
701 * all branches, may need the help of the SW filter
703 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
705 struct hw_perf_event_extra *reg;
706 u64 br_type = event->attr.branch_sample_type;
710 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
711 if (!(br_type & (1ULL << i)))
714 v = x86_pmu.lbr_sel_map[i];
715 if (v == LBR_NOT_SUPP)
722 reg = &event->hw.branch_reg;
723 reg->idx = EXTRA_REG_LBR;
726 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
727 * in suppress mode. So LBR_SELECT should be set to
728 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
729 * But the 10th bit LBR_CALL_STACK does not operate
732 reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
734 if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
735 (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
736 (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO))
737 reg->config |= LBR_NO_INFO;
742 int intel_pmu_setup_lbr_filter(struct perf_event *event)
753 * setup SW LBR filter
755 ret = intel_pmu_setup_sw_lbr_filter(event);
760 * setup HW LBR filter, if any
762 if (x86_pmu.lbr_sel_map)
763 ret = intel_pmu_setup_hw_lbr_filter(event);
769 * return the type of control flow change at address "from"
770 * instruction is not necessarily a branch (in case of interrupt).
772 * The branch type returned also includes the priv level of the
773 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
775 * If a branch type is unknown OR the instruction cannot be
776 * decoded (e.g., text page not present), then X86_BR_NONE is
779 static int branch_type(unsigned long from, unsigned long to, int abort)
783 int bytes_read, bytes_left;
784 int ret = X86_BR_NONE;
785 int ext, to_plm, from_plm;
786 u8 buf[MAX_INSN_SIZE];
789 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
790 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
793 * maybe zero if lbr did not fill up after a reset by the time
794 * we get a PMU interrupt
796 if (from == 0 || to == 0)
800 return X86_BR_ABORT | to_plm;
802 if (from_plm == X86_BR_USER) {
804 * can happen if measuring at the user level only
805 * and we interrupt in a kernel thread, e.g., idle.
810 /* may fail if text not present */
811 bytes_left = copy_from_user_nmi(buf, (void __user *)from,
813 bytes_read = MAX_INSN_SIZE - bytes_left;
820 * The LBR logs any address in the IP, even if the IP just
821 * faulted. This means userspace can control the from address.
822 * Ensure we don't blindy read any address by validating it is
823 * a known text address.
825 if (kernel_text_address(from)) {
828 * Assume we can get the maximum possible size
829 * when grabbing kernel data. This is not
830 * _strictly_ true since we could possibly be
831 * executing up next to a memory hole, but
832 * it is very unlikely to be a problem.
834 bytes_read = MAX_INSN_SIZE;
841 * decoder needs to know the ABI especially
842 * on 64-bit systems running 32-bit apps
845 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
847 insn_init(&insn, addr, bytes_read, is64);
848 insn_get_opcode(&insn);
849 if (!insn.opcode.got)
852 switch (insn.opcode.bytes[0]) {
854 switch (insn.opcode.bytes[1]) {
855 case 0x05: /* syscall */
856 case 0x34: /* sysenter */
857 ret = X86_BR_SYSCALL;
859 case 0x07: /* sysret */
860 case 0x35: /* sysexit */
863 case 0x80 ... 0x8f: /* conditional */
870 case 0x70 ... 0x7f: /* conditional */
873 case 0xc2: /* near ret */
874 case 0xc3: /* near ret */
875 case 0xca: /* far ret */
876 case 0xcb: /* far ret */
879 case 0xcf: /* iret */
882 case 0xcc ... 0xce: /* int */
885 case 0xe8: /* call near rel */
886 insn_get_immediate(&insn);
887 if (insn.immediate1.value == 0) {
888 /* zero length call */
889 ret = X86_BR_ZERO_CALL;
892 case 0x9a: /* call far absolute */
895 case 0xe0 ... 0xe3: /* loop jmp */
898 case 0xe9 ... 0xeb: /* jmp */
901 case 0xff: /* call near absolute, call far absolute ind */
902 insn_get_modrm(&insn);
903 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
905 case 2: /* near ind call */
906 case 3: /* far ind call */
907 ret = X86_BR_IND_CALL;
911 ret = X86_BR_IND_JMP;
919 * interrupts, traps, faults (and thus ring transition) may
920 * occur on any instructions. Thus, to classify them correctly,
921 * we need to first look at the from and to priv levels. If they
922 * are different and to is in the kernel, then it indicates
923 * a ring transition. If the from instruction is not a ring
924 * transition instr (syscall, systenter, int), then it means
925 * it was a irq, trap or fault.
927 * we have no way of detecting kernel to kernel faults.
929 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
930 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
934 * branch priv level determined by target as
935 * is done by HW when LBR_SELECT is implemented
937 if (ret != X86_BR_NONE)
943 #define X86_BR_TYPE_MAP_MAX 16
945 static int branch_map[X86_BR_TYPE_MAP_MAX] = {
946 PERF_BR_CALL, /* X86_BR_CALL */
947 PERF_BR_RET, /* X86_BR_RET */
948 PERF_BR_SYSCALL, /* X86_BR_SYSCALL */
949 PERF_BR_SYSRET, /* X86_BR_SYSRET */
950 PERF_BR_UNKNOWN, /* X86_BR_INT */
951 PERF_BR_UNKNOWN, /* X86_BR_IRET */
952 PERF_BR_COND, /* X86_BR_JCC */
953 PERF_BR_UNCOND, /* X86_BR_JMP */
954 PERF_BR_UNKNOWN, /* X86_BR_IRQ */
955 PERF_BR_IND_CALL, /* X86_BR_IND_CALL */
956 PERF_BR_UNKNOWN, /* X86_BR_ABORT */
957 PERF_BR_UNKNOWN, /* X86_BR_IN_TX */
958 PERF_BR_UNKNOWN, /* X86_BR_NO_TX */
959 PERF_BR_CALL, /* X86_BR_ZERO_CALL */
960 PERF_BR_UNKNOWN, /* X86_BR_CALL_STACK */
961 PERF_BR_IND, /* X86_BR_IND_JMP */
965 common_branch_type(int type)
969 type >>= 2; /* skip X86_BR_USER and X86_BR_KERNEL */
973 if (i < X86_BR_TYPE_MAP_MAX)
974 return branch_map[i];
977 return PERF_BR_UNKNOWN;
981 * implement actual branch filter based on user demand.
982 * Hardware may not exactly satisfy that request, thus
983 * we need to inspect opcodes. Mismatched branches are
984 * discarded. Therefore, the number of branches returned
985 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
988 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
991 int br_sel = cpuc->br_sel;
993 bool compress = false;
995 /* if sampling all branches, then nothing to filter */
996 if (((br_sel & X86_BR_ALL) == X86_BR_ALL) &&
997 ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE))
1000 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
1002 from = cpuc->lbr_entries[i].from;
1003 to = cpuc->lbr_entries[i].to;
1005 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
1006 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
1007 if (cpuc->lbr_entries[i].in_tx)
1008 type |= X86_BR_IN_TX;
1010 type |= X86_BR_NO_TX;
1013 /* if type does not correspond, then discard */
1014 if (type == X86_BR_NONE || (br_sel & type) != type) {
1015 cpuc->lbr_entries[i].from = 0;
1019 if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE)
1020 cpuc->lbr_entries[i].type = common_branch_type(type);
1026 /* remove all entries with from=0 */
1027 for (i = 0; i < cpuc->lbr_stack.nr; ) {
1028 if (!cpuc->lbr_entries[i].from) {
1030 while (++j < cpuc->lbr_stack.nr)
1031 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
1032 cpuc->lbr_stack.nr--;
1033 if (!cpuc->lbr_entries[i].from)
1041 * Map interface branch filters onto LBR filters
1043 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1044 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1045 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1046 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1047 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1048 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP
1049 | LBR_IND_JMP | LBR_FAR,
1051 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
1053 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] =
1054 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
1056 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
1058 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP,
1059 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1060 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1063 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1064 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1065 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1066 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1067 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1068 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1069 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1071 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1072 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1073 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1074 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1077 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
1078 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
1079 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
1080 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
1081 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
1082 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
1083 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1085 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
1086 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
1087 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
1088 | LBR_RETURN | LBR_CALL_STACK,
1089 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
1090 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
1094 void __init intel_pmu_lbr_init_core(void)
1097 x86_pmu.lbr_tos = MSR_LBR_TOS;
1098 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1099 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1102 * SW branch filter usage:
1103 * - compensate for lack of HW filter
1107 /* nehalem/westmere */
1108 void __init intel_pmu_lbr_init_nhm(void)
1110 x86_pmu.lbr_nr = 16;
1111 x86_pmu.lbr_tos = MSR_LBR_TOS;
1112 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1113 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1115 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1116 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1119 * SW branch filter usage:
1120 * - workaround LBR_SEL errata (see above)
1121 * - support syscall, sysret capture.
1122 * That requires LBR_FAR but that means far
1123 * jmp need to be filtered out
1128 void __init intel_pmu_lbr_init_snb(void)
1130 x86_pmu.lbr_nr = 16;
1131 x86_pmu.lbr_tos = MSR_LBR_TOS;
1132 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1133 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1135 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1136 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
1139 * SW branch filter usage:
1140 * - support syscall, sysret capture.
1141 * That requires LBR_FAR but that means far
1142 * jmp need to be filtered out
1147 void intel_pmu_lbr_init_hsw(void)
1149 x86_pmu.lbr_nr = 16;
1150 x86_pmu.lbr_tos = MSR_LBR_TOS;
1151 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1152 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1154 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1155 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1157 if (lbr_from_signext_quirk_needed())
1158 static_branch_enable(&lbr_from_quirk_key);
1162 __init void intel_pmu_lbr_init_skl(void)
1164 x86_pmu.lbr_nr = 32;
1165 x86_pmu.lbr_tos = MSR_LBR_TOS;
1166 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1167 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1169 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1170 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1173 * SW branch filter usage:
1174 * - support syscall, sysret capture.
1175 * That requires LBR_FAR but that means far
1176 * jmp need to be filtered out
1181 void __init intel_pmu_lbr_init_atom(void)
1184 * only models starting at stepping 10 seems
1185 * to have an operational LBR which can freeze
1188 if (boot_cpu_data.x86_model == 28
1189 && boot_cpu_data.x86_stepping < 10) {
1190 pr_cont("LBR disabled due to erratum");
1195 x86_pmu.lbr_tos = MSR_LBR_TOS;
1196 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1197 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1200 * SW branch filter usage:
1201 * - compensate for lack of HW filter
1206 void __init intel_pmu_lbr_init_slm(void)
1209 x86_pmu.lbr_tos = MSR_LBR_TOS;
1210 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1211 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1213 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1214 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
1217 * SW branch filter usage:
1218 * - compensate for lack of HW filter
1220 pr_cont("8-deep LBR, ");
1223 /* Knights Landing */
1224 void intel_pmu_lbr_init_knl(void)
1227 x86_pmu.lbr_tos = MSR_LBR_TOS;
1228 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
1229 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
1231 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1232 x86_pmu.lbr_sel_map = snb_lbr_sel_map;