arch/x86/events/intel/ds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/bitops.h>
   3 #include <linux/types.h>
   4 #include <linux/slab.h>
   5
   6 #include <asm/cpu_entry_area.h>
   7 #include <asm/perf_event.h>
   8 #include <asm/tlbflush.h>
   9 #include <asm/insn.h>
  10 #include <asm/io.h>
  11
  12 #include "../perf_event.h"
  13
  14 /* Waste a full page so it can be mapped into the cpu_entry_area */
  15 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
  16
  17 /* The size of a BTS record in bytes: */
  18 #define BTS_RECORD_SIZE         24
  19
  20 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  21
  22 /*
  23  * pebs_record_32 for p4 and core not supported
  24
  25 struct pebs_record_32 {
  26         u32 flags, ip;
  27         u32 ax, bc, cx, dx;
  28         u32 si, di, bp, sp;
  29 };
  30
  31  */
  32
  33 union intel_x86_pebs_dse {
  34         u64 val;
  35         struct {
  36                 unsigned int ld_dse:4;
  37                 unsigned int ld_stlb_miss:1;
  38                 unsigned int ld_locked:1;
  39                 unsigned int ld_reserved:26;
  40         };
  41         struct {
  42                 unsigned int st_l1d_hit:1;
  43                 unsigned int st_reserved1:3;
  44                 unsigned int st_stlb_miss:1;
  45                 unsigned int st_locked:1;
  46                 unsigned int st_reserved2:26;
  47         };
  48 };
  49
  50
  51 /*
  52  * Map PEBS Load Latency Data Source encodings to generic
  53  * memory data source information
  54  */
  55 #define P(a, b) PERF_MEM_S(a, b)
  56 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  57 #define LEVEL(x) P(LVLNUM, x)
  58 #define REM P(REMOTE, REMOTE)
  59 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  60
  61 /* Version for Sandy Bridge and later */
  62 static u64 pebs_data_source[] = {
  63         P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  64         OP_LH | P(LVL, L1)  | LEVEL(L1) | P(SNOOP, NONE),  /* 0x01: L1 local */
  65         OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
  66         OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),  /* 0x03: L2 hit */
  67         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, NONE),  /* 0x04: L3 hit */
  68         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, MISS),  /* 0x05: L3 hit, snoop miss */
  69         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HIT),   /* 0x06: L3 hit, snoop hit */
  70         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HITM),  /* 0x07: L3 hit, snoop hitm */
  71         OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  72         OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  73         OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, HIT),       /* 0x0a: L3 miss, shared */
  74         OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  75         OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | SNOOP_NONE_MISS,     /* 0x0c: L3 miss, excl */
  76         OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
  77         OP_LH | P(LVL, IO)  | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
  78         OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
  79 };
  80
  81 /* Patch up minor differences in the bits */
  82 void __init intel_pmu_pebs_data_source_nhm(void)
  83 {
  84         pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
  85         pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  86         pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  87 }
  88
  89 void __init intel_pmu_pebs_data_source_skl(bool pmem)
  90 {
  91         u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
  92
  93         pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
  94         pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
  95         pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
  96         pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
  97         pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
  98 }
  99
 100 static u64 precise_store_data(u64 status)
 101 {
 102         union intel_x86_pebs_dse dse;
 103         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
 104
 105         dse.val = status;
 106
 107         /*
 108          * bit 4: TLB access
 109          * 1 = stored missed 2nd level TLB
 110          *
 111          * so it either hit the walker or the OS
 112          * otherwise hit 2nd level TLB
 113          */
 114         if (dse.st_stlb_miss)
 115                 val |= P(TLB, MISS);
 116         else
 117                 val |= P(TLB, HIT);
 118
 119         /*
 120          * bit 0: hit L1 data cache
 121          * if not set, then all we know is that
 122          * it missed L1D
 123          */
 124         if (dse.st_l1d_hit)
 125                 val |= P(LVL, HIT);
 126         else
 127                 val |= P(LVL, MISS);
 128
 129         /*
 130          * bit 5: Locked prefix
 131          */
 132         if (dse.st_locked)
 133                 val |= P(LOCK, LOCKED);
 134
 135         return val;
 136 }
 137
 138 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 139 {
 140         union perf_mem_data_src dse;
 141
 142         dse.val = PERF_MEM_NA;
 143
 144         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 145                 dse.mem_op = PERF_MEM_OP_STORE;
 146         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 147                 dse.mem_op = PERF_MEM_OP_LOAD;
 148
 149         /*
 150          * L1 info only valid for following events:
 151          *
 152          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 153          * MEM_UOPS_RETIRED.LOCK_STORES
 154          * MEM_UOPS_RETIRED.SPLIT_STORES
 155          * MEM_UOPS_RETIRED.ALL_STORES
 156          */
 157         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 158                 if (status & 1)
 159                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 160                 else
 161                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 162         }
 163         return dse.val;
 164 }
 165
 166 static u64 load_latency_data(u64 status)
 167 {
 168         union intel_x86_pebs_dse dse;
 169         u64 val;
 170
 171         dse.val = status;
 172
 173         /*
 174          * use the mapping table for bit 0-3
 175          */
 176         val = pebs_data_source[dse.ld_dse];
 177
 178         /*
 179          * Nehalem models do not support TLB, Lock infos
 180          */
 181         if (x86_pmu.pebs_no_tlb) {
 182                 val |= P(TLB, NA) | P(LOCK, NA);
 183                 return val;
 184         }
 185         /*
 186          * bit 4: TLB access
 187          * 0 = did not miss 2nd level TLB
 188          * 1 = missed 2nd level TLB
 189          */
 190         if (dse.ld_stlb_miss)
 191                 val |= P(TLB, MISS) | P(TLB, L2);
 192         else
 193                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 194
 195         /*
 196          * bit 5: locked prefix
 197          */
 198         if (dse.ld_locked)
 199                 val |= P(LOCK, LOCKED);
 200
 201         return val;
 202 }
 203
 204 struct pebs_record_core {
 205         u64 flags, ip;
 206         u64 ax, bx, cx, dx;
 207         u64 si, di, bp, sp;
 208         u64 r8,  r9,  r10, r11;
 209         u64 r12, r13, r14, r15;
 210 };
 211
 212 struct pebs_record_nhm {
 213         u64 flags, ip;
 214         u64 ax, bx, cx, dx;
 215         u64 si, di, bp, sp;
 216         u64 r8,  r9,  r10, r11;
 217         u64 r12, r13, r14, r15;
 218         u64 status, dla, dse, lat;
 219 };
 220
 221 /*
 222  * Same as pebs_record_nhm, with two additional fields.
 223  */
 224 struct pebs_record_hsw {
 225         u64 flags, ip;
 226         u64 ax, bx, cx, dx;
 227         u64 si, di, bp, sp;
 228         u64 r8,  r9,  r10, r11;
 229         u64 r12, r13, r14, r15;
 230         u64 status, dla, dse, lat;
 231         u64 real_ip, tsx_tuning;
 232 };
 233
 234 union hsw_tsx_tuning {
 235         struct {
 236                 u32 cycles_last_block     : 32,
 237                     hle_abort             : 1,
 238                     rtm_abort             : 1,
 239                     instruction_abort     : 1,
 240                     non_instruction_abort : 1,
 241                     retry                 : 1,
 242                     data_conflict         : 1,
 243                     capacity_writes       : 1,
 244                     capacity_reads        : 1;
 245         };
 246         u64         value;
 247 };
 248
 249 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 250
 251 /* Same as HSW, plus TSC */
 252
 253 struct pebs_record_skl {
 254         u64 flags, ip;
 255         u64 ax, bx, cx, dx;
 256         u64 si, di, bp, sp;
 257         u64 r8,  r9,  r10, r11;
 258         u64 r12, r13, r14, r15;
 259         u64 status, dla, dse, lat;
 260         u64 real_ip, tsx_tuning;
 261         u64 tsc;
 262 };
 263
 264 void init_debug_store_on_cpu(int cpu)
 265 {
 266         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 267
 268         if (!ds)
 269                 return;
 270
 271         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 272                      (u32)((u64)(unsigned long)ds),
 273                      (u32)((u64)(unsigned long)ds >> 32));
 274 }
 275
 276 void fini_debug_store_on_cpu(int cpu)
 277 {
 278         if (!per_cpu(cpu_hw_events, cpu).ds)
 279                 return;
 280
 281         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 282 }
 283
 284 static DEFINE_PER_CPU(void *, insn_buffer);
 285
 286 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
 287 {
 288         unsigned long start = (unsigned long)cea;
 289         phys_addr_t pa;
 290         size_t msz = 0;
 291
 292         pa = virt_to_phys(addr);
 293
 294         preempt_disable();
 295         for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
 296                 cea_set_pte(cea, pa, prot);
 297
 298         /*
 299          * This is a cross-CPU update of the cpu_entry_area, we must shoot down
 300          * all TLB entries for it.
 301          */
 302         flush_tlb_kernel_range(start, start + size);
 303         preempt_enable();
 304 }
 305
 306 static void ds_clear_cea(void *cea, size_t size)
 307 {
 308         unsigned long start = (unsigned long)cea;
 309         size_t msz = 0;
 310
 311         preempt_disable();
 312         for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
 313                 cea_set_pte(cea, 0, PAGE_NONE);
 314
 315         flush_tlb_kernel_range(start, start + size);
 316         preempt_enable();
 317 }
 318
 319 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
 320 {
 321         unsigned int order = get_order(size);
 322         int node = cpu_to_node(cpu);
 323         struct page *page;
 324
 325         page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
 326         return page ? page_address(page) : NULL;
 327 }
 328
 329 static void dsfree_pages(const void *buffer, size_t size)
 330 {
 331         if (buffer)
 332                 free_pages((unsigned long)buffer, get_order(size));
 333 }
 334
 335 static int alloc_pebs_buffer(int cpu)
 336 {
 337         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 338         struct debug_store *ds = hwev->ds;
 339         size_t bsiz = x86_pmu.pebs_buffer_size;
 340         int max, node = cpu_to_node(cpu);
 341         void *buffer, *insn_buff, *cea;
 342
 343         if (!x86_pmu.pebs)
 344                 return 0;
 345
 346         buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
 347         if (unlikely(!buffer))
 348                 return -ENOMEM;
 349
 350         /*
 351          * HSW+ already provides us the eventing ip; no need to allocate this
 352          * buffer then.
 353          */
 354         if (x86_pmu.intel_cap.pebs_format < 2) {
 355                 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 356                 if (!insn_buff) {
 357                         dsfree_pages(buffer, bsiz);
 358                         return -ENOMEM;
 359                 }
 360                 per_cpu(insn_buffer, cpu) = insn_buff;
 361         }
 362         hwev->ds_pebs_vaddr = buffer;
 363         /* Update the cpu entry area mapping */
 364         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
 365         ds->pebs_buffer_base = (unsigned long) cea;
 366         ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
 367         ds->pebs_index = ds->pebs_buffer_base;
 368         max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
 369         ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
 370         return 0;
 371 }
 372
 373 static void release_pebs_buffer(int cpu)
 374 {
 375         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 376         void *cea;
 377
 378         if (!x86_pmu.pebs)
 379                 return;
 380
 381         kfree(per_cpu(insn_buffer, cpu));
 382         per_cpu(insn_buffer, cpu) = NULL;
 383
 384         /* Clear the fixmap */
 385         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
 386         ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
 387         dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
 388         hwev->ds_pebs_vaddr = NULL;
 389 }
 390
 391 static int alloc_bts_buffer(int cpu)
 392 {
 393         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 394         struct debug_store *ds = hwev->ds;
 395         void *buffer, *cea;
 396         int max;
 397
 398         if (!x86_pmu.bts)
 399                 return 0;
 400
 401         buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
 402         if (unlikely(!buffer)) {
 403                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 404                 return -ENOMEM;
 405         }
 406         hwev->ds_bts_vaddr = buffer;
 407         /* Update the fixmap */
 408         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
 409         ds->bts_buffer_base = (unsigned long) cea;
 410         ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
 411         ds->bts_index = ds->bts_buffer_base;
 412         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 413         ds->bts_absolute_maximum = ds->bts_buffer_base +
 414                                         max * BTS_RECORD_SIZE;
 415         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 416                                         (max / 16) * BTS_RECORD_SIZE;
 417         return 0;
 418 }
 419
 420 static void release_bts_buffer(int cpu)
 421 {
 422         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 423         void *cea;
 424
 425         if (!x86_pmu.bts)
 426                 return;
 427
 428         /* Clear the fixmap */
 429         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
 430         ds_clear_cea(cea, BTS_BUFFER_SIZE);
 431         dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
 432         hwev->ds_bts_vaddr = NULL;
 433 }
 434
 435 static int alloc_ds_buffer(int cpu)
 436 {
 437         struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
 438
 439         memset(ds, 0, sizeof(*ds));
 440         per_cpu(cpu_hw_events, cpu).ds = ds;
 441         return 0;
 442 }
 443
 444 static void release_ds_buffer(int cpu)
 445 {
 446         per_cpu(cpu_hw_events, cpu).ds = NULL;
 447 }
 448
 449 void release_ds_buffers(void)
 450 {
 451         int cpu;
 452
 453         if (!x86_pmu.bts && !x86_pmu.pebs)
 454                 return;
 455
 456         for_each_possible_cpu(cpu)
 457                 release_ds_buffer(cpu);
 458
 459         for_each_possible_cpu(cpu) {
 460                 /*
 461                  * Again, ignore errors from offline CPUs, they will no longer
 462                  * observe cpu_hw_events.ds and not program the DS_AREA when
 463                  * they come up.
 464                  */
 465                 fini_debug_store_on_cpu(cpu);
 466         }
 467
 468         for_each_possible_cpu(cpu) {
 469                 release_pebs_buffer(cpu);
 470                 release_bts_buffer(cpu);
 471         }
 472 }
 473
 474 void reserve_ds_buffers(void)
 475 {
 476         int bts_err = 0, pebs_err = 0;
 477         int cpu;
 478
 479         x86_pmu.bts_active = 0;
 480         x86_pmu.pebs_active = 0;
 481
 482         if (!x86_pmu.bts && !x86_pmu.pebs)
 483                 return;
 484
 485         if (!x86_pmu.bts)
 486                 bts_err = 1;
 487
 488         if (!x86_pmu.pebs)
 489                 pebs_err = 1;
 490
 491         for_each_possible_cpu(cpu) {
 492                 if (alloc_ds_buffer(cpu)) {
 493                         bts_err = 1;
 494                         pebs_err = 1;
 495                 }
 496
 497                 if (!bts_err && alloc_bts_buffer(cpu))
 498                         bts_err = 1;
 499
 500                 if (!pebs_err && alloc_pebs_buffer(cpu))
 501                         pebs_err = 1;
 502
 503                 if (bts_err && pebs_err)
 504                         break;
 505         }
 506
 507         if (bts_err) {
 508                 for_each_possible_cpu(cpu)
 509                         release_bts_buffer(cpu);
 510         }
 511
 512         if (pebs_err) {
 513                 for_each_possible_cpu(cpu)
 514                         release_pebs_buffer(cpu);
 515         }
 516
 517         if (bts_err && pebs_err) {
 518                 for_each_possible_cpu(cpu)
 519                         release_ds_buffer(cpu);
 520         } else {
 521                 if (x86_pmu.bts && !bts_err)
 522                         x86_pmu.bts_active = 1;
 523
 524                 if (x86_pmu.pebs && !pebs_err)
 525                         x86_pmu.pebs_active = 1;
 526
 527                 for_each_possible_cpu(cpu) {
 528                         /*
 529                          * Ignores wrmsr_on_cpu() errors for offline CPUs they
 530                          * will get this call through intel_pmu_cpu_starting().
 531                          */
 532                         init_debug_store_on_cpu(cpu);
 533                 }
 534         }
 535 }
 536
 537 /*
 538  * BTS
 539  */
 540
 541 struct event_constraint bts_constraint =
 542         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 543
 544 void intel_pmu_enable_bts(u64 config)
 545 {
 546         unsigned long debugctlmsr;
 547
 548         debugctlmsr = get_debugctlmsr();
 549
 550         debugctlmsr |= DEBUGCTLMSR_TR;
 551         debugctlmsr |= DEBUGCTLMSR_BTS;
 552         if (config & ARCH_PERFMON_EVENTSEL_INT)
 553                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 554
 555         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 556                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 557
 558         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 559                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 560
 561         update_debugctlmsr(debugctlmsr);
 562 }
 563
 564 void intel_pmu_disable_bts(void)
 565 {
 566         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 567         unsigned long debugctlmsr;
 568
 569         if (!cpuc->ds)
 570                 return;
 571
 572         debugctlmsr = get_debugctlmsr();
 573
 574         debugctlmsr &=
 575                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 576                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 577
 578         update_debugctlmsr(debugctlmsr);
 579 }
 580
 581 int intel_pmu_drain_bts_buffer(void)
 582 {
 583         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 584         struct debug_store *ds = cpuc->ds;
 585         struct bts_record {
 586                 u64     from;
 587                 u64     to;
 588                 u64     flags;
 589         };
 590         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 591         struct bts_record *at, *base, *top;
 592         struct perf_output_handle handle;
 593         struct perf_event_header header;
 594         struct perf_sample_data data;
 595         unsigned long skip = 0;
 596         struct pt_regs regs;
 597
 598         if (!event)
 599                 return 0;
 600
 601         if (!x86_pmu.bts_active)
 602                 return 0;
 603
 604         base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 605         top  = (struct bts_record *)(unsigned long)ds->bts_index;
 606
 607         if (top <= base)
 608                 return 0;
 609
 610         memset(&regs, 0, sizeof(regs));
 611
 612         ds->bts_index = ds->bts_buffer_base;
 613
 614         perf_sample_data_init(&data, 0, event->hw.last_period);
 615
 616         /*
 617          * BTS leaks kernel addresses in branches across the cpl boundary,
 618          * such as traps or system calls, so unless the user is asking for
 619          * kernel tracing (and right now it's not possible), we'd need to
 620          * filter them out. But first we need to count how many of those we
 621          * have in the current batch. This is an extra O(n) pass, however,
 622          * it's much faster than the other one especially considering that
 623          * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
 624          * alloc_bts_buffer()).
 625          */
 626         for (at = base; at < top; at++) {
 627                 /*
 628                  * Note that right now *this* BTS code only works if
 629                  * attr::exclude_kernel is set, but let's keep this extra
 630                  * check here in case that changes.
 631                  */
 632                 if (event->attr.exclude_kernel &&
 633                     (kernel_ip(at->from) || kernel_ip(at->to)))
 634                         skip++;
 635         }
 636
 637         /*
 638          * Prepare a generic sample, i.e. fill in the invariant fields.
 639          * We will overwrite the from and to address before we output
 640          * the sample.
 641          */
 642         rcu_read_lock();
 643         perf_prepare_sample(&header, &data, event, &regs);
 644
 645         if (perf_output_begin(&handle, &data, event,
 646                               header.size * (top - base - skip)))
 647                 goto unlock;
 648
 649         for (at = base; at < top; at++) {
 650                 /* Filter out any records that contain kernel addresses. */
 651                 if (event->attr.exclude_kernel &&
 652                     (kernel_ip(at->from) || kernel_ip(at->to)))
 653                         continue;
 654
 655                 data.ip         = at->from;
 656                 data.addr       = at->to;
 657
 658                 perf_output_sample(&handle, &header, &data, event);
 659         }
 660
 661         perf_output_end(&handle);
 662
 663         /* There's new data available. */
 664         event->hw.interrupts++;
 665         event->pending_kill = POLL_IN;
 666 unlock:
 667         rcu_read_unlock();
 668         return 1;
 669 }
 670
 671 static inline void intel_pmu_drain_pebs_buffer(void)
 672 {
 673         struct perf_sample_data data;
 674
 675         x86_pmu.drain_pebs(NULL, &data);
 676 }
 677
 678 /*
 679  * PEBS
 680  */
 681 struct event_constraint intel_core2_pebs_event_constraints[] = {
 682         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 683         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 684         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 685         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 686         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 687         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 688         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
 689         EVENT_CONSTRAINT_END
 690 };
 691
 692 struct event_constraint intel_atom_pebs_event_constraints[] = {
 693         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 694         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 695         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 696         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 697         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
 698         /* Allow all events as PEBS with no flags */
 699         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 700         EVENT_CONSTRAINT_END
 701 };
 702
 703 struct event_constraint intel_slm_pebs_event_constraints[] = {
 704         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 705         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
 706         /* Allow all events as PEBS with no flags */
 707         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 708         EVENT_CONSTRAINT_END
 709 };
 710
 711 struct event_constraint intel_glm_pebs_event_constraints[] = {
 712         /* Allow all events as PEBS with no flags */
 713         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 714         EVENT_CONSTRAINT_END
 715 };
 716
 717 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 718         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 719         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 720         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 721         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 722         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 723         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 724         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 725         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 726         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 727         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 728         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 729         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 730         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 731         EVENT_CONSTRAINT_END
 732 };
 733
 734 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 735         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 736         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 737         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 738         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 739         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 740         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 741         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 742         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 743         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 744         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 745         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 746         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 747         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 748         EVENT_CONSTRAINT_END
 749 };
 750
 751 struct event_constraint intel_snb_pebs_event_constraints[] = {
 752         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 753         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 754         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 755         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 756         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 757         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 758         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 759         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 760         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 761         /* Allow all events as PEBS with no flags */
 762         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 763         EVENT_CONSTRAINT_END
 764 };
 765
 766 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 767         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 768         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 769         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 770         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 771         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 772         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 773         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 774         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 775         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 776         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 777         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 778         /* Allow all events as PEBS with no flags */
 779         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 780         EVENT_CONSTRAINT_END
 781 };
 782
 783 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 784         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 785         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 786         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 787         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 788         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 789         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 790         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 791         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 792         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 793         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 794         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 795         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 796         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 797         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 798         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 799         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 800         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 801         /* Allow all events as PEBS with no flags */
 802         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 803         EVENT_CONSTRAINT_END
 804 };
 805
 806 struct event_constraint intel_bdw_pebs_event_constraints[] = {
 807         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 808         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 809         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 810         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 811         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 812         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 813         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 814         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 815         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 816         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 817         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 818         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 819         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 820         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 821         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 822         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 823         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 824         /* Allow all events as PEBS with no flags */
 825         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 826         EVENT_CONSTRAINT_END
 827 };
 828
 829
 830 struct event_constraint intel_skl_pebs_event_constraints[] = {
 831         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 832         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 833         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 834         /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
 835         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 836         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 837         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 838         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 839         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
 840         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
 841         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
 842         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
 843         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
 844         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
 845         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
 846         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
 847         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
 848         /* Allow all events as PEBS with no flags */
 849         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 850         EVENT_CONSTRAINT_END
 851 };
 852
 853 struct event_constraint intel_icl_pebs_event_constraints[] = {
 854         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),   /* INST_RETIRED.PREC_DIST */
 855         INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),  /* SLOTS */
 856
 857         INTEL_PLD_CONSTRAINT(0x1cd, 0xff),                      /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 858         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),    /* MEM_INST_RETIRED.LOAD */
 859         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x2d0, 0xf),    /* MEM_INST_RETIRED.STORE */
 860
 861         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
 862
 863         INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),                /* MEM_INST_RETIRED.* */
 864
 865         /*
 866          * Everything else is handled by PMU_FL_PEBS_ALL, because we
 867          * need the full constraints from the main table.
 868          */
 869
 870         EVENT_CONSTRAINT_END
 871 };
 872
 873 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 874 {
 875         struct event_constraint *c;
 876
 877         if (!event->attr.precise_ip)
 878                 return NULL;
 879
 880         if (x86_pmu.pebs_constraints) {
 881                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 882                         if (constraint_match(c, event->hw.config)) {
 883                                 event->hw.flags |= c->flags;
 884                                 return c;
 885                         }
 886                 }
 887         }
 888
 889         /*
 890          * Extended PEBS support
 891          * Makes the PEBS code search the normal constraints.
 892          */
 893         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
 894                 return NULL;
 895
 896         return &emptyconstraint;
 897 }
 898
 899 /*
 900  * We need the sched_task callback even for per-cpu events when we use
 901  * the large interrupt threshold, such that we can provide PID and TID
 902  * to PEBS samples.
 903  */
 904 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
 905 {
 906         if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
 907                 return false;
 908
 909         return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
 910 }
 911
 912 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
 913 {
 914         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 915
 916         if (!sched_in && pebs_needs_sched_cb(cpuc))
 917                 intel_pmu_drain_pebs_buffer();
 918 }
 919
 920 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
 921 {
 922         struct debug_store *ds = cpuc->ds;
 923         u64 threshold;
 924         int reserved;
 925
 926         if (cpuc->n_pebs_via_pt)
 927                 return;
 928
 929         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
 930                 reserved = x86_pmu.max_pebs_events + x86_pmu.num_counters_fixed;
 931         else
 932                 reserved = x86_pmu.max_pebs_events;
 933
 934         if (cpuc->n_pebs == cpuc->n_large_pebs) {
 935                 threshold = ds->pebs_absolute_maximum -
 936                         reserved * cpuc->pebs_record_size;
 937         } else {
 938                 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
 939         }
 940
 941         ds->pebs_interrupt_threshold = threshold;
 942 }
 943
 944 static void adaptive_pebs_record_size_update(void)
 945 {
 946         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 947         u64 pebs_data_cfg = cpuc->pebs_data_cfg;
 948         int sz = sizeof(struct pebs_basic);
 949
 950         if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
 951                 sz += sizeof(struct pebs_meminfo);
 952         if (pebs_data_cfg & PEBS_DATACFG_GP)
 953                 sz += sizeof(struct pebs_gprs);
 954         if (pebs_data_cfg & PEBS_DATACFG_XMMS)
 955                 sz += sizeof(struct pebs_xmm);
 956         if (pebs_data_cfg & PEBS_DATACFG_LBRS)
 957                 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
 958
 959         cpuc->pebs_record_size = sz;
 960 }
 961
 962 #define PERF_PEBS_MEMINFO_TYPE  (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC |   \
 963                                 PERF_SAMPLE_PHYS_ADDR |                      \
 964                                 PERF_SAMPLE_WEIGHT_TYPE |                    \
 965                                 PERF_SAMPLE_TRANSACTION |                    \
 966                                 PERF_SAMPLE_DATA_PAGE_SIZE)
 967
 968 static u64 pebs_update_adaptive_cfg(struct perf_event *event)
 969 {
 970         struct perf_event_attr *attr = &event->attr;
 971         u64 sample_type = attr->sample_type;
 972         u64 pebs_data_cfg = 0;
 973         bool gprs, tsx_weight;
 974
 975         if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
 976             attr->precise_ip > 1)
 977                 return pebs_data_cfg;
 978
 979         if (sample_type & PERF_PEBS_MEMINFO_TYPE)
 980                 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
 981
 982         /*
 983          * We need GPRs when:
 984          * + user requested them
 985          * + precise_ip < 2 for the non event IP
 986          * + For RTM TSX weight we need GPRs for the abort code.
 987          */
 988         gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
 989                (attr->sample_regs_intr & PEBS_GP_REGS);
 990
 991         tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
 992                      ((attr->config & INTEL_ARCH_EVENT_MASK) ==
 993                       x86_pmu.rtm_abort_event);
 994
 995         if (gprs || (attr->precise_ip < 2) || tsx_weight)
 996                 pebs_data_cfg |= PEBS_DATACFG_GP;
 997
 998         if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
 999             (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1000                 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1001
1002         if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1003                 /*
1004                  * For now always log all LBRs. Could configure this
1005                  * later.
1006                  */
1007                 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1008                         ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1009         }
1010
1011         return pebs_data_cfg;
1012 }
1013
1014 static void
1015 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1016                   struct perf_event *event, bool add)
1017 {
1018         struct pmu *pmu = event->ctx->pmu;
1019         /*
1020          * Make sure we get updated with the first PEBS
1021          * event. It will trigger also during removal, but
1022          * that does not hurt:
1023          */
1024         bool update = cpuc->n_pebs == 1;
1025
1026         if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1027                 if (!needed_cb)
1028                         perf_sched_cb_inc(pmu);
1029                 else
1030                         perf_sched_cb_dec(pmu);
1031
1032                 update = true;
1033         }
1034
1035         /*
1036          * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1037          * iterating all remaining PEBS events to reconstruct the config.
1038          */
1039         if (x86_pmu.intel_cap.pebs_baseline && add) {
1040                 u64 pebs_data_cfg;
1041
1042                 /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1043                 if (cpuc->n_pebs == 1) {
1044                         cpuc->pebs_data_cfg = 0;
1045                         cpuc->pebs_record_size = sizeof(struct pebs_basic);
1046                 }
1047
1048                 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1049
1050                 /* Update pebs_record_size if new event requires more data. */
1051                 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1052                         cpuc->pebs_data_cfg |= pebs_data_cfg;
1053                         adaptive_pebs_record_size_update();
1054                         update = true;
1055                 }
1056         }
1057
1058         if (update)
1059                 pebs_update_threshold(cpuc);
1060 }
1061
1062 void intel_pmu_pebs_add(struct perf_event *event)
1063 {
1064         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1065         struct hw_perf_event *hwc = &event->hw;
1066         bool needed_cb = pebs_needs_sched_cb(cpuc);
1067
1068         cpuc->n_pebs++;
1069         if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1070                 cpuc->n_large_pebs++;
1071         if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1072                 cpuc->n_pebs_via_pt++;
1073
1074         pebs_update_state(needed_cb, cpuc, event, true);
1075 }
1076
1077 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1078 {
1079         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1080
1081         if (!is_pebs_pt(event))
1082                 return;
1083
1084         if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1085                 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1086 }
1087
1088 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1089 {
1090         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1091         struct hw_perf_event *hwc = &event->hw;
1092         struct debug_store *ds = cpuc->ds;
1093
1094         if (!is_pebs_pt(event))
1095                 return;
1096
1097         if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1098                 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1099
1100         cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1101
1102         wrmsrl(MSR_RELOAD_PMC0 + hwc->idx, ds->pebs_event_reset[hwc->idx]);
1103 }
1104
1105 void intel_pmu_pebs_enable(struct perf_event *event)
1106 {
1107         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1108         struct hw_perf_event *hwc = &event->hw;
1109         struct debug_store *ds = cpuc->ds;
1110
1111         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1112
1113         cpuc->pebs_enabled |= 1ULL << hwc->idx;
1114
1115         if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1116                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1117         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1118                 cpuc->pebs_enabled |= 1ULL << 63;
1119
1120         if (x86_pmu.intel_cap.pebs_baseline) {
1121                 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1122                 if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1123                         wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1124                         cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1125                 }
1126         }
1127
1128         /*
1129          * Use auto-reload if possible to save a MSR write in the PMI.
1130          * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1131          */
1132         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1133                 unsigned int idx = hwc->idx;
1134
1135                 if (idx >= INTEL_PMC_IDX_FIXED)
1136                         idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1137                 ds->pebs_event_reset[idx] =
1138                         (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1139         } else {
1140                 ds->pebs_event_reset[hwc->idx] = 0;
1141         }
1142
1143         intel_pmu_pebs_via_pt_enable(event);
1144 }
1145
1146 void intel_pmu_pebs_del(struct perf_event *event)
1147 {
1148         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1149         struct hw_perf_event *hwc = &event->hw;
1150         bool needed_cb = pebs_needs_sched_cb(cpuc);
1151
1152         cpuc->n_pebs--;
1153         if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1154                 cpuc->n_large_pebs--;
1155         if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1156                 cpuc->n_pebs_via_pt--;
1157
1158         pebs_update_state(needed_cb, cpuc, event, false);
1159 }
1160
1161 void intel_pmu_pebs_disable(struct perf_event *event)
1162 {
1163         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1164         struct hw_perf_event *hwc = &event->hw;
1165
1166         if (cpuc->n_pebs == cpuc->n_large_pebs &&
1167             cpuc->n_pebs != cpuc->n_pebs_via_pt)
1168                 intel_pmu_drain_pebs_buffer();
1169
1170         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1171
1172         if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1173             (x86_pmu.version < 5))
1174                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1175         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1176                 cpuc->pebs_enabled &= ~(1ULL << 63);
1177
1178         intel_pmu_pebs_via_pt_disable(event);
1179
1180         if (cpuc->enabled)
1181                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1182
1183         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1184 }
1185
1186 void intel_pmu_pebs_enable_all(void)
1187 {
1188         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1189
1190         if (cpuc->pebs_enabled)
1191                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1192 }
1193
1194 void intel_pmu_pebs_disable_all(void)
1195 {
1196         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1197
1198         if (cpuc->pebs_enabled)
1199                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1200 }
1201
1202 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1203 {
1204         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1205         unsigned long from = cpuc->lbr_entries[0].from;
1206         unsigned long old_to, to = cpuc->lbr_entries[0].to;
1207         unsigned long ip = regs->ip;
1208         int is_64bit = 0;
1209         void *kaddr;
1210         int size;
1211
1212         /*
1213          * We don't need to fixup if the PEBS assist is fault like
1214          */
1215         if (!x86_pmu.intel_cap.pebs_trap)
1216                 return 1;
1217
1218         /*
1219          * No LBR entry, no basic block, no rewinding
1220          */
1221         if (!cpuc->lbr_stack.nr || !from || !to)
1222                 return 0;
1223
1224         /*
1225          * Basic blocks should never cross user/kernel boundaries
1226          */
1227         if (kernel_ip(ip) != kernel_ip(to))
1228                 return 0;
1229
1230         /*
1231          * unsigned math, either ip is before the start (impossible) or
1232          * the basic block is larger than 1 page (sanity)
1233          */
1234         if ((ip - to) > PEBS_FIXUP_SIZE)
1235                 return 0;
1236
1237         /*
1238          * We sampled a branch insn, rewind using the LBR stack
1239          */
1240         if (ip == to) {
1241                 set_linear_ip(regs, from);
1242                 return 1;
1243         }
1244
1245         size = ip - to;
1246         if (!kernel_ip(ip)) {
1247                 int bytes;
1248                 u8 *buf = this_cpu_read(insn_buffer);
1249
1250                 /* 'size' must fit our buffer, see above */
1251                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1252                 if (bytes != 0)
1253                         return 0;
1254
1255                 kaddr = buf;
1256         } else {
1257                 kaddr = (void *)to;
1258         }
1259
1260         do {
1261                 struct insn insn;
1262
1263                 old_to = to;
1264
1265 #ifdef CONFIG_X86_64
1266                 is_64bit = kernel_ip(to) || any_64bit_mode(regs);
1267 #endif
1268                 insn_init(&insn, kaddr, size, is_64bit);
1269                 insn_get_length(&insn);
1270                 /*
1271                  * Make sure there was not a problem decoding the
1272                  * instruction and getting the length.  This is
1273                  * doubly important because we have an infinite
1274                  * loop if insn.length=0.
1275                  */
1276                 if (!insn.length)
1277                         break;
1278
1279                 to += insn.length;
1280                 kaddr += insn.length;
1281                 size -= insn.length;
1282         } while (to < ip);
1283
1284         if (to == ip) {
1285                 set_linear_ip(regs, old_to);
1286                 return 1;
1287         }
1288
1289         /*
1290          * Even though we decoded the basic block, the instruction stream
1291          * never matched the given IP, either the TO or the IP got corrupted.
1292          */
1293         return 0;
1294 }
1295
1296 static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1297 {
1298         if (tsx_tuning) {
1299                 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1300                 return tsx.cycles_last_block;
1301         }
1302         return 0;
1303 }
1304
1305 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1306 {
1307         u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1308
1309         /* For RTM XABORTs also log the abort code from AX */
1310         if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1311                 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1312         return txn;
1313 }
1314
1315 static inline u64 get_pebs_status(void *n)
1316 {
1317         if (x86_pmu.intel_cap.pebs_format < 4)
1318                 return ((struct pebs_record_nhm *)n)->status;
1319         return ((struct pebs_basic *)n)->applicable_counters;
1320 }
1321
1322 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1323                 (PERF_X86_EVENT_PEBS_ST_HSW | \
1324                  PERF_X86_EVENT_PEBS_LD_HSW | \
1325                  PERF_X86_EVENT_PEBS_NA_HSW)
1326
1327 static u64 get_data_src(struct perf_event *event, u64 aux)
1328 {
1329         u64 val = PERF_MEM_NA;
1330         int fl = event->hw.flags;
1331         bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1332
1333         if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1334                 val = load_latency_data(aux);
1335         else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1336                 val = precise_datala_hsw(event, aux);
1337         else if (fst)
1338                 val = precise_store_data(aux);
1339         return val;
1340 }
1341
1342 #define PERF_SAMPLE_ADDR_TYPE   (PERF_SAMPLE_ADDR |             \
1343                                  PERF_SAMPLE_PHYS_ADDR |        \
1344                                  PERF_SAMPLE_DATA_PAGE_SIZE)
1345
1346 static void setup_pebs_fixed_sample_data(struct perf_event *event,
1347                                    struct pt_regs *iregs, void *__pebs,
1348                                    struct perf_sample_data *data,
1349                                    struct pt_regs *regs)
1350 {
1351         /*
1352          * We cast to the biggest pebs_record but are careful not to
1353          * unconditionally access the 'extra' entries.
1354          */
1355         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1356         struct pebs_record_skl *pebs = __pebs;
1357         u64 sample_type;
1358         int fll;
1359
1360         if (pebs == NULL)
1361                 return;
1362
1363         sample_type = event->attr.sample_type;
1364         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1365
1366         perf_sample_data_init(data, 0, event->hw.last_period);
1367
1368         data->period = event->hw.last_period;
1369
1370         /*
1371          * Use latency for weight (only avail with PEBS-LL)
1372          */
1373         if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE))
1374                 data->weight.full = pebs->lat;
1375
1376         /*
1377          * data.data_src encodes the data source
1378          */
1379         if (sample_type & PERF_SAMPLE_DATA_SRC)
1380                 data->data_src.val = get_data_src(event, pebs->dse);
1381
1382         /*
1383          * We must however always use iregs for the unwinder to stay sane; the
1384          * record BP,SP,IP can point into thin air when the record is from a
1385          * previous PMI context or an (I)RET happened between the record and
1386          * PMI.
1387          */
1388         if (sample_type & PERF_SAMPLE_CALLCHAIN)
1389                 data->callchain = perf_callchain(event, iregs);
1390
1391         /*
1392          * We use the interrupt regs as a base because the PEBS record does not
1393          * contain a full regs set, specifically it seems to lack segment
1394          * descriptors, which get used by things like user_mode().
1395          *
1396          * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1397          */
1398         *regs = *iregs;
1399
1400         /*
1401          * Initialize regs_>flags from PEBS,
1402          * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1403          * i.e., do not rely on it being zero:
1404          */
1405         regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1406
1407         if (sample_type & PERF_SAMPLE_REGS_INTR) {
1408                 regs->ax = pebs->ax;
1409                 regs->bx = pebs->bx;
1410                 regs->cx = pebs->cx;
1411                 regs->dx = pebs->dx;
1412                 regs->si = pebs->si;
1413                 regs->di = pebs->di;
1414
1415                 regs->bp = pebs->bp;
1416                 regs->sp = pebs->sp;
1417
1418 #ifndef CONFIG_X86_32
1419                 regs->r8 = pebs->r8;
1420                 regs->r9 = pebs->r9;
1421                 regs->r10 = pebs->r10;
1422                 regs->r11 = pebs->r11;
1423                 regs->r12 = pebs->r12;
1424                 regs->r13 = pebs->r13;
1425                 regs->r14 = pebs->r14;
1426                 regs->r15 = pebs->r15;
1427 #endif
1428         }
1429
1430         if (event->attr.precise_ip > 1) {
1431                 /*
1432                  * Haswell and later processors have an 'eventing IP'
1433                  * (real IP) which fixes the off-by-1 skid in hardware.
1434                  * Use it when precise_ip >= 2 :
1435                  */
1436                 if (x86_pmu.intel_cap.pebs_format >= 2) {
1437                         set_linear_ip(regs, pebs->real_ip);
1438                         regs->flags |= PERF_EFLAGS_EXACT;
1439                 } else {
1440                         /* Otherwise, use PEBS off-by-1 IP: */
1441                         set_linear_ip(regs, pebs->ip);
1442
1443                         /*
1444                          * With precise_ip >= 2, try to fix up the off-by-1 IP
1445                          * using the LBR. If successful, the fixup function
1446                          * corrects regs->ip and calls set_linear_ip() on regs:
1447                          */
1448                         if (intel_pmu_pebs_fixup_ip(regs))
1449                                 regs->flags |= PERF_EFLAGS_EXACT;
1450                 }
1451         } else {
1452                 /*
1453                  * When precise_ip == 1, return the PEBS off-by-1 IP,
1454                  * no fixup attempted:
1455                  */
1456                 set_linear_ip(regs, pebs->ip);
1457         }
1458
1459
1460         if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
1461             x86_pmu.intel_cap.pebs_format >= 1)
1462                 data->addr = pebs->dla;
1463
1464         if (x86_pmu.intel_cap.pebs_format >= 2) {
1465                 /* Only set the TSX weight when no memory weight. */
1466                 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll)
1467                         data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
1468
1469                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1470                         data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1471                                                               pebs->ax);
1472         }
1473
1474         /*
1475          * v3 supplies an accurate time stamp, so we use that
1476          * for the time stamp.
1477          *
1478          * We can only do this for the default trace clock.
1479          */
1480         if (x86_pmu.intel_cap.pebs_format >= 3 &&
1481                 event->attr.use_clockid == 0)
1482                 data->time = native_sched_clock_from_tsc(pebs->tsc);
1483
1484         if (has_branch_stack(event))
1485                 data->br_stack = &cpuc->lbr_stack;
1486 }
1487
1488 static void adaptive_pebs_save_regs(struct pt_regs *regs,
1489                                     struct pebs_gprs *gprs)
1490 {
1491         regs->ax = gprs->ax;
1492         regs->bx = gprs->bx;
1493         regs->cx = gprs->cx;
1494         regs->dx = gprs->dx;
1495         regs->si = gprs->si;
1496         regs->di = gprs->di;
1497         regs->bp = gprs->bp;
1498         regs->sp = gprs->sp;
1499 #ifndef CONFIG_X86_32
1500         regs->r8 = gprs->r8;
1501         regs->r9 = gprs->r9;
1502         regs->r10 = gprs->r10;
1503         regs->r11 = gprs->r11;
1504         regs->r12 = gprs->r12;
1505         regs->r13 = gprs->r13;
1506         regs->r14 = gprs->r14;
1507         regs->r15 = gprs->r15;
1508 #endif
1509 }
1510
1511 /*
1512  * With adaptive PEBS the layout depends on what fields are configured.
1513  */
1514
1515 static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1516                                             struct pt_regs *iregs, void *__pebs,
1517                                             struct perf_sample_data *data,
1518                                             struct pt_regs *regs)
1519 {
1520         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1521         struct pebs_basic *basic = __pebs;
1522         void *next_record = basic + 1;
1523         u64 sample_type;
1524         u64 format_size;
1525         struct pebs_meminfo *meminfo = NULL;
1526         struct pebs_gprs *gprs = NULL;
1527         struct x86_perf_regs *perf_regs;
1528
1529         if (basic == NULL)
1530                 return;
1531
1532         perf_regs = container_of(regs, struct x86_perf_regs, regs);
1533         perf_regs->xmm_regs = NULL;
1534
1535         sample_type = event->attr.sample_type;
1536         format_size = basic->format_size;
1537         perf_sample_data_init(data, 0, event->hw.last_period);
1538         data->period = event->hw.last_period;
1539
1540         if (event->attr.use_clockid == 0)
1541                 data->time = native_sched_clock_from_tsc(basic->tsc);
1542
1543         /*
1544          * We must however always use iregs for the unwinder to stay sane; the
1545          * record BP,SP,IP can point into thin air when the record is from a
1546          * previous PMI context or an (I)RET happened between the record and
1547          * PMI.
1548          */
1549         if (sample_type & PERF_SAMPLE_CALLCHAIN)
1550                 data->callchain = perf_callchain(event, iregs);
1551
1552         *regs = *iregs;
1553         /* The ip in basic is EventingIP */
1554         set_linear_ip(regs, basic->ip);
1555         regs->flags = PERF_EFLAGS_EXACT;
1556
1557         /*
1558          * The record for MEMINFO is in front of GP
1559          * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1560          * Save the pointer here but process later.
1561          */
1562         if (format_size & PEBS_DATACFG_MEMINFO) {
1563                 meminfo = next_record;
1564                 next_record = meminfo + 1;
1565         }
1566
1567         if (format_size & PEBS_DATACFG_GP) {
1568                 gprs = next_record;
1569                 next_record = gprs + 1;
1570
1571                 if (event->attr.precise_ip < 2) {
1572                         set_linear_ip(regs, gprs->ip);
1573                         regs->flags &= ~PERF_EFLAGS_EXACT;
1574                 }
1575
1576                 if (sample_type & PERF_SAMPLE_REGS_INTR)
1577                         adaptive_pebs_save_regs(regs, gprs);
1578         }
1579
1580         if (format_size & PEBS_DATACFG_MEMINFO) {
1581                 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE)
1582                         data->weight.full = meminfo->latency ?:
1583                                 intel_get_tsx_weight(meminfo->tsx_tuning);
1584
1585                 if (sample_type & PERF_SAMPLE_DATA_SRC)
1586                         data->data_src.val = get_data_src(event, meminfo->aux);
1587
1588                 if (sample_type & PERF_SAMPLE_ADDR_TYPE)
1589                         data->addr = meminfo->address;
1590
1591                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1592                         data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
1593                                                           gprs ? gprs->ax : 0);
1594         }
1595
1596         if (format_size & PEBS_DATACFG_XMMS) {
1597                 struct pebs_xmm *xmm = next_record;
1598
1599                 next_record = xmm + 1;
1600                 perf_regs->xmm_regs = xmm->xmm;
1601         }
1602
1603         if (format_size & PEBS_DATACFG_LBRS) {
1604                 struct lbr_entry *lbr = next_record;
1605                 int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
1606                                         & 0xff) + 1;
1607                 next_record = next_record + num_lbr * sizeof(struct lbr_entry);
1608
1609                 if (has_branch_stack(event)) {
1610                         intel_pmu_store_pebs_lbrs(lbr);
1611                         data->br_stack = &cpuc->lbr_stack;
1612                 }
1613         }
1614
1615         WARN_ONCE(next_record != __pebs + (format_size >> 48),
1616                         "PEBS record size %llu, expected %llu, config %llx\n",
1617                         format_size >> 48,
1618                         (u64)(next_record - __pebs),
1619                         basic->format_size);
1620 }
1621
1622 static inline void *
1623 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1624 {
1625         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1626         void *at;
1627         u64 pebs_status;
1628
1629         /*
1630          * fmt0 does not have a status bitfield (does not use
1631          * perf_record_nhm format)
1632          */
1633         if (x86_pmu.intel_cap.pebs_format < 1)
1634                 return base;
1635
1636         if (base == NULL)
1637                 return NULL;
1638
1639         for (at = base; at < top; at += cpuc->pebs_record_size) {
1640                 unsigned long status = get_pebs_status(at);
1641
1642                 if (test_bit(bit, (unsigned long *)&status)) {
1643                         /* PEBS v3 has accurate status bits */
1644                         if (x86_pmu.intel_cap.pebs_format >= 3)
1645                                 return at;
1646
1647                         if (status == (1 << bit))
1648                                 return at;
1649
1650                         /* clear non-PEBS bit and re-check */
1651                         pebs_status = status & cpuc->pebs_enabled;
1652                         pebs_status &= PEBS_COUNTER_MASK;
1653                         if (pebs_status == (1 << bit))
1654                                 return at;
1655                 }
1656         }
1657         return NULL;
1658 }
1659
1660 void intel_pmu_auto_reload_read(struct perf_event *event)
1661 {
1662         WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
1663
1664         perf_pmu_disable(event->pmu);
1665         intel_pmu_drain_pebs_buffer();
1666         perf_pmu_enable(event->pmu);
1667 }
1668
1669 /*
1670  * Special variant of intel_pmu_save_and_restart() for auto-reload.
1671  */
1672 static int
1673 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1674 {
1675         struct hw_perf_event *hwc = &event->hw;
1676         int shift = 64 - x86_pmu.cntval_bits;
1677         u64 period = hwc->sample_period;
1678         u64 prev_raw_count, new_raw_count;
1679         s64 new, old;
1680
1681         WARN_ON(!period);
1682
1683         /*
1684          * drain_pebs() only happens when the PMU is disabled.
1685          */
1686         WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1687
1688         prev_raw_count = local64_read(&hwc->prev_count);
1689         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1690         local64_set(&hwc->prev_count, new_raw_count);
1691
1692         /*
1693          * Since the counter increments a negative counter value and
1694          * overflows on the sign switch, giving the interval:
1695          *
1696          *   [-period, 0]
1697          *
1698          * the difference between two consequtive reads is:
1699          *
1700          *   A) value2 - value1;
1701          *      when no overflows have happened in between,
1702          *
1703          *   B) (0 - value1) + (value2 - (-period));
1704          *      when one overflow happened in between,
1705          *
1706          *   C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1707          *      when @n overflows happened in between.
1708          *
1709          * Here A) is the obvious difference, B) is the extension to the
1710          * discrete interval, where the first term is to the top of the
1711          * interval and the second term is from the bottom of the next
1712          * interval and C) the extension to multiple intervals, where the
1713          * middle term is the whole intervals covered.
1714          *
1715          * An equivalent of C, by reduction, is:
1716          *
1717          *   value2 - value1 + n * period
1718          */
1719         new = ((s64)(new_raw_count << shift) >> shift);
1720         old = ((s64)(prev_raw_count << shift) >> shift);
1721         local64_add(new - old + count * period, &event->count);
1722
1723         local64_set(&hwc->period_left, -new);
1724
1725         perf_event_update_userpage(event);
1726
1727         return 0;
1728 }
1729
1730 static __always_inline void
1731 __intel_pmu_pebs_event(struct perf_event *event,
1732                        struct pt_regs *iregs,
1733                        struct perf_sample_data *data,
1734                        void *base, void *top,
1735                        int bit, int count,
1736                        void (*setup_sample)(struct perf_event *,
1737                                             struct pt_regs *,
1738                                             void *,
1739                                             struct perf_sample_data *,
1740                                             struct pt_regs *))
1741 {
1742         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1743         struct hw_perf_event *hwc = &event->hw;
1744         struct x86_perf_regs perf_regs;
1745         struct pt_regs *regs = &perf_regs.regs;
1746         void *at = get_next_pebs_record_by_bit(base, top, bit);
1747         static struct pt_regs dummy_iregs;
1748
1749         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1750                 /*
1751                  * Now, auto-reload is only enabled in fixed period mode.
1752                  * The reload value is always hwc->sample_period.
1753                  * May need to change it, if auto-reload is enabled in
1754                  * freq mode later.
1755                  */
1756                 intel_pmu_save_and_restart_reload(event, count);
1757         } else if (!intel_pmu_save_and_restart(event))
1758                 return;
1759
1760         if (!iregs)
1761                 iregs = &dummy_iregs;
1762
1763         while (count > 1) {
1764                 setup_sample(event, iregs, at, data, regs);
1765                 perf_event_output(event, data, regs);
1766                 at += cpuc->pebs_record_size;
1767                 at = get_next_pebs_record_by_bit(at, top, bit);
1768                 count--;
1769         }
1770
1771         setup_sample(event, iregs, at, data, regs);
1772         if (iregs == &dummy_iregs) {
1773                 /*
1774                  * The PEBS records may be drained in the non-overflow context,
1775                  * e.g., large PEBS + context switch. Perf should treat the
1776                  * last record the same as other PEBS records, and doesn't
1777                  * invoke the generic overflow handler.
1778                  */
1779                 perf_event_output(event, data, regs);
1780         } else {
1781                 /*
1782                  * All but the last records are processed.
1783                  * The last one is left to be able to call the overflow handler.
1784                  */
1785                 if (perf_event_overflow(event, data, regs))
1786                         x86_pmu_stop(event, 0);
1787         }
1788 }
1789
1790 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
1791 {
1792         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1793         struct debug_store *ds = cpuc->ds;
1794         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1795         struct pebs_record_core *at, *top;
1796         int n;
1797
1798         if (!x86_pmu.pebs_active)
1799                 return;
1800
1801         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1802         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1803
1804         /*
1805          * Whatever else happens, drain the thing
1806          */
1807         ds->pebs_index = ds->pebs_buffer_base;
1808
1809         if (!test_bit(0, cpuc->active_mask))
1810                 return;
1811
1812         WARN_ON_ONCE(!event);
1813
1814         if (!event->attr.precise_ip)
1815                 return;
1816
1817         n = top - at;
1818         if (n <= 0) {
1819                 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1820                         intel_pmu_save_and_restart_reload(event, 0);
1821                 return;
1822         }
1823
1824         __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n,
1825                                setup_pebs_fixed_sample_data);
1826 }
1827
1828 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
1829 {
1830         struct perf_event *event;
1831         int bit;
1832
1833         /*
1834          * The drain_pebs() could be called twice in a short period
1835          * for auto-reload event in pmu::read(). There are no
1836          * overflows have happened in between.
1837          * It needs to call intel_pmu_save_and_restart_reload() to
1838          * update the event->count for this case.
1839          */
1840         for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
1841                 event = cpuc->events[bit];
1842                 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1843                         intel_pmu_save_and_restart_reload(event, 0);
1844         }
1845 }
1846
1847 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
1848 {
1849         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1850         struct debug_store *ds = cpuc->ds;
1851         struct perf_event *event;
1852         void *base, *at, *top;
1853         short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1854         short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1855         int bit, i, size;
1856         u64 mask;
1857
1858         if (!x86_pmu.pebs_active)
1859                 return;
1860
1861         base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1862         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1863
1864         ds->pebs_index = ds->pebs_buffer_base;
1865
1866         mask = (1ULL << x86_pmu.max_pebs_events) - 1;
1867         size = x86_pmu.max_pebs_events;
1868         if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
1869                 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
1870                 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
1871         }
1872
1873         if (unlikely(base >= top)) {
1874                 intel_pmu_pebs_event_update_no_drain(cpuc, size);
1875                 return;
1876         }
1877
1878         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1879                 struct pebs_record_nhm *p = at;
1880                 u64 pebs_status;
1881
1882                 pebs_status = p->status & cpuc->pebs_enabled;
1883                 pebs_status &= mask;
1884
1885                 /* PEBS v3 has more accurate status bits */
1886                 if (x86_pmu.intel_cap.pebs_format >= 3) {
1887                         for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
1888                                 counts[bit]++;
1889
1890                         continue;
1891                 }
1892
1893                 /*
1894                  * On some CPUs the PEBS status can be zero when PEBS is
1895                  * racing with clearing of GLOBAL_STATUS.
1896                  *
1897                  * Normally we would drop that record, but in the
1898                  * case when there is only a single active PEBS event
1899                  * we can assume it's for that event.
1900                  */
1901                 if (!pebs_status && cpuc->pebs_enabled &&
1902                         !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1903                         pebs_status = cpuc->pebs_enabled;
1904
1905                 bit = find_first_bit((unsigned long *)&pebs_status,
1906                                         x86_pmu.max_pebs_events);
1907                 if (bit >= x86_pmu.max_pebs_events)
1908                         continue;
1909
1910                 /*
1911                  * The PEBS hardware does not deal well with the situation
1912                  * when events happen near to each other and multiple bits
1913                  * are set. But it should happen rarely.
1914                  *
1915                  * If these events include one PEBS and multiple non-PEBS
1916                  * events, it doesn't impact PEBS record. The record will
1917                  * be handled normally. (slow path)
1918                  *
1919                  * If these events include two or more PEBS events, the
1920                  * records for the events can be collapsed into a single
1921                  * one, and it's not possible to reconstruct all events
1922                  * that caused the PEBS record. It's called collision.
1923                  * If collision happened, the record will be dropped.
1924                  */
1925                 if (pebs_status != (1ULL << bit)) {
1926                         for_each_set_bit(i, (unsigned long *)&pebs_status, size)
1927                                 error[i]++;
1928                         continue;
1929                 }
1930
1931                 counts[bit]++;
1932         }
1933
1934         for_each_set_bit(bit, (unsigned long *)&mask, size) {
1935                 if ((counts[bit] == 0) && (error[bit] == 0))
1936                         continue;
1937
1938                 event = cpuc->events[bit];
1939                 if (WARN_ON_ONCE(!event))
1940                         continue;
1941
1942                 if (WARN_ON_ONCE(!event->attr.precise_ip))
1943                         continue;
1944
1945                 /* log dropped samples number */
1946                 if (error[bit]) {
1947                         perf_log_lost_samples(event, error[bit]);
1948
1949                         if (iregs && perf_event_account_interrupt(event))
1950                                 x86_pmu_stop(event, 0);
1951                 }
1952
1953                 if (counts[bit]) {
1954                         __intel_pmu_pebs_event(event, iregs, data, base,
1955                                                top, bit, counts[bit],
1956                                                setup_pebs_fixed_sample_data);
1957                 }
1958         }
1959 }
1960
1961 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
1962 {
1963         short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1964         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1965         struct debug_store *ds = cpuc->ds;
1966         struct perf_event *event;
1967         void *base, *at, *top;
1968         int bit, size;
1969         u64 mask;
1970
1971         if (!x86_pmu.pebs_active)
1972                 return;
1973
1974         base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
1975         top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
1976
1977         ds->pebs_index = ds->pebs_buffer_base;
1978
1979         mask = ((1ULL << x86_pmu.max_pebs_events) - 1) |
1980                (((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
1981         size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
1982
1983         if (unlikely(base >= top)) {
1984                 intel_pmu_pebs_event_update_no_drain(cpuc, size);
1985                 return;
1986         }
1987
1988         for (at = base; at < top; at += cpuc->pebs_record_size) {
1989                 u64 pebs_status;
1990
1991                 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
1992                 pebs_status &= mask;
1993
1994                 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
1995                         counts[bit]++;
1996         }
1997
1998         for_each_set_bit(bit, (unsigned long *)&mask, size) {
1999                 if (counts[bit] == 0)
2000                         continue;
2001
2002                 event = cpuc->events[bit];
2003                 if (WARN_ON_ONCE(!event))
2004                         continue;
2005
2006                 if (WARN_ON_ONCE(!event->attr.precise_ip))
2007                         continue;
2008
2009                 __intel_pmu_pebs_event(event, iregs, data, base,
2010                                        top, bit, counts[bit],
2011                                        setup_pebs_adaptive_sample_data);
2012         }
2013 }
2014
2015 /*
2016  * BTS, PEBS probe and setup
2017  */
2018
2019 void __init intel_ds_init(void)
2020 {
2021         /*
2022          * No support for 32bit formats
2023          */
2024         if (!boot_cpu_has(X86_FEATURE_DTES64))
2025                 return;
2026
2027         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
2028         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2029         x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2030         if (x86_pmu.version <= 4)
2031                 x86_pmu.pebs_no_isolation = 1;
2032
2033         if (x86_pmu.pebs) {
2034                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
2035                 char *pebs_qual = "";
2036                 int format = x86_pmu.intel_cap.pebs_format;
2037
2038                 if (format < 4)
2039                         x86_pmu.intel_cap.pebs_baseline = 0;
2040
2041                 switch (format) {
2042                 case 0:
2043                         pr_cont("PEBS fmt0%c, ", pebs_type);
2044                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2045                         /*
2046                          * Using >PAGE_SIZE buffers makes the WRMSR to
2047                          * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2048                          * mysteriously hang on Core2.
2049                          *
2050                          * As a workaround, we don't do this.
2051                          */
2052                         x86_pmu.pebs_buffer_size = PAGE_SIZE;
2053                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2054                         break;
2055
2056                 case 1:
2057                         pr_cont("PEBS fmt1%c, ", pebs_type);
2058                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2059                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2060                         break;
2061
2062                 case 2:
2063                         pr_cont("PEBS fmt2%c, ", pebs_type);
2064                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2065                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2066                         break;
2067
2068                 case 3:
2069                         pr_cont("PEBS fmt3%c, ", pebs_type);
2070                         x86_pmu.pebs_record_size =
2071                                                 sizeof(struct pebs_record_skl);
2072                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2073                         x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2074                         break;
2075
2076                 case 4:
2077                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2078                         x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2079                         if (x86_pmu.intel_cap.pebs_baseline) {
2080                                 x86_pmu.large_pebs_flags |=
2081                                         PERF_SAMPLE_BRANCH_STACK |
2082                                         PERF_SAMPLE_TIME;
2083                                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
2084                                 pebs_qual = "-baseline";
2085                                 x86_get_pmu()->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2086                         } else {
2087                                 /* Only basic record supported */
2088                                 x86_pmu.large_pebs_flags &=
2089                                         ~(PERF_SAMPLE_ADDR |
2090                                           PERF_SAMPLE_TIME |
2091                                           PERF_SAMPLE_DATA_SRC |
2092                                           PERF_SAMPLE_TRANSACTION |
2093                                           PERF_SAMPLE_REGS_USER |
2094                                           PERF_SAMPLE_REGS_INTR);
2095                         }
2096                         pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2097
2098                         if (x86_pmu.intel_cap.pebs_output_pt_available) {
2099                                 pr_cont("PEBS-via-PT, ");
2100                                 x86_get_pmu()->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2101                         }
2102
2103                         break;
2104
2105                 default:
2106                         pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2107                         x86_pmu.pebs = 0;
2108                 }
2109         }
2110 }
2111
2112 void perf_restore_debug_store(void)
2113 {
2114         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2115
2116         if (!x86_pmu.bts && !x86_pmu.pebs)
2117                 return;
2118
2119         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2120 }