arch/x86/events/intel/ds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/bitops.h>
   3 #include <linux/types.h>
   4 #include <linux/slab.h>
   5
   6 #include <asm/cpu_entry_area.h>
   7 #include <asm/perf_event.h>
   8 #include <asm/tlbflush.h>
   9 #include <asm/insn.h>
  10 #include <asm/io.h>
  11
  12 #include "../perf_event.h"
  13
  14 /* Waste a full page so it can be mapped into the cpu_entry_area */
  15 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
  16
  17 /* The size of a BTS record in bytes: */
  18 #define BTS_RECORD_SIZE         24
  19
  20 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  21
  22 /*
  23  * pebs_record_32 for p4 and core not supported
  24
  25 struct pebs_record_32 {
  26         u32 flags, ip;
  27         u32 ax, bc, cx, dx;
  28         u32 si, di, bp, sp;
  29 };
  30
  31  */
  32
  33 union intel_x86_pebs_dse {
  34         u64 val;
  35         struct {
  36                 unsigned int ld_dse:4;
  37                 unsigned int ld_stlb_miss:1;
  38                 unsigned int ld_locked:1;
  39                 unsigned int ld_data_blk:1;
  40                 unsigned int ld_addr_blk:1;
  41                 unsigned int ld_reserved:24;
  42         };
  43         struct {
  44                 unsigned int st_l1d_hit:1;
  45                 unsigned int st_reserved1:3;
  46                 unsigned int st_stlb_miss:1;
  47                 unsigned int st_locked:1;
  48                 unsigned int st_reserved2:26;
  49         };
  50         struct {
  51                 unsigned int st_lat_dse:4;
  52                 unsigned int st_lat_stlb_miss:1;
  53                 unsigned int st_lat_locked:1;
  54                 unsigned int ld_reserved3:26;
  55         };
  56 };
  57
  58
  59 /*
  60  * Map PEBS Load Latency Data Source encodings to generic
  61  * memory data source information
  62  */
  63 #define P(a, b) PERF_MEM_S(a, b)
  64 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  65 #define LEVEL(x) P(LVLNUM, x)
  66 #define REM P(REMOTE, REMOTE)
  67 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  68
  69 /* Version for Sandy Bridge and later */
  70 static u64 pebs_data_source[] = {
  71         P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  72         OP_LH | P(LVL, L1)  | LEVEL(L1) | P(SNOOP, NONE),  /* 0x01: L1 local */
  73         OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
  74         OP_LH | P(LVL, L2)  | LEVEL(L2) | P(SNOOP, NONE),  /* 0x03: L2 hit */
  75         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, NONE),  /* 0x04: L3 hit */
  76         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, MISS),  /* 0x05: L3 hit, snoop miss */
  77         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HIT),   /* 0x06: L3 hit, snoop hit */
  78         OP_LH | P(LVL, L3)  | LEVEL(L3) | P(SNOOP, HITM),  /* 0x07: L3 hit, snoop hitm */
  79         OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  80         OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  81         OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, HIT),       /* 0x0a: L3 miss, shared */
  82         OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  83         OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | SNOOP_NONE_MISS,     /* 0x0c: L3 miss, excl */
  84         OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
  85         OP_LH | P(LVL, IO)  | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
  86         OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
  87 };
  88
  89 /* Patch up minor differences in the bits */
  90 void __init intel_pmu_pebs_data_source_nhm(void)
  91 {
  92         pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
  93         pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  94         pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  95 }
  96
  97 void __init intel_pmu_pebs_data_source_skl(bool pmem)
  98 {
  99         u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
 100
 101         pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
 102         pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
 103         pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
 104         pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
 105         pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
 106 }
 107
 108 static u64 precise_store_data(u64 status)
 109 {
 110         union intel_x86_pebs_dse dse;
 111         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
 112
 113         dse.val = status;
 114
 115         /*
 116          * bit 4: TLB access
 117          * 1 = stored missed 2nd level TLB
 118          *
 119          * so it either hit the walker or the OS
 120          * otherwise hit 2nd level TLB
 121          */
 122         if (dse.st_stlb_miss)
 123                 val |= P(TLB, MISS);
 124         else
 125                 val |= P(TLB, HIT);
 126
 127         /*
 128          * bit 0: hit L1 data cache
 129          * if not set, then all we know is that
 130          * it missed L1D
 131          */
 132         if (dse.st_l1d_hit)
 133                 val |= P(LVL, HIT);
 134         else
 135                 val |= P(LVL, MISS);
 136
 137         /*
 138          * bit 5: Locked prefix
 139          */
 140         if (dse.st_locked)
 141                 val |= P(LOCK, LOCKED);
 142
 143         return val;
 144 }
 145
 146 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 147 {
 148         union perf_mem_data_src dse;
 149
 150         dse.val = PERF_MEM_NA;
 151
 152         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 153                 dse.mem_op = PERF_MEM_OP_STORE;
 154         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 155                 dse.mem_op = PERF_MEM_OP_LOAD;
 156
 157         /*
 158          * L1 info only valid for following events:
 159          *
 160          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 161          * MEM_UOPS_RETIRED.LOCK_STORES
 162          * MEM_UOPS_RETIRED.SPLIT_STORES
 163          * MEM_UOPS_RETIRED.ALL_STORES
 164          */
 165         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 166                 if (status & 1)
 167                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 168                 else
 169                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 170         }
 171         return dse.val;
 172 }
 173
 174 static u64 load_latency_data(u64 status)
 175 {
 176         union intel_x86_pebs_dse dse;
 177         u64 val;
 178
 179         dse.val = status;
 180
 181         /*
 182          * use the mapping table for bit 0-3
 183          */
 184         val = pebs_data_source[dse.ld_dse];
 185
 186         /*
 187          * Nehalem models do not support TLB, Lock infos
 188          */
 189         if (x86_pmu.pebs_no_tlb) {
 190                 val |= P(TLB, NA) | P(LOCK, NA);
 191                 return val;
 192         }
 193         /*
 194          * bit 4: TLB access
 195          * 0 = did not miss 2nd level TLB
 196          * 1 = missed 2nd level TLB
 197          */
 198         if (dse.ld_stlb_miss)
 199                 val |= P(TLB, MISS) | P(TLB, L2);
 200         else
 201                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 202
 203         /*
 204          * bit 5: locked prefix
 205          */
 206         if (dse.ld_locked)
 207                 val |= P(LOCK, LOCKED);
 208
 209         /*
 210          * Ice Lake and earlier models do not support block infos.
 211          */
 212         if (!x86_pmu.pebs_block) {
 213                 val |= P(BLK, NA);
 214                 return val;
 215         }
 216         /*
 217          * bit 6: load was blocked since its data could not be forwarded
 218          *        from a preceding store
 219          */
 220         if (dse.ld_data_blk)
 221                 val |= P(BLK, DATA);
 222
 223         /*
 224          * bit 7: load was blocked due to potential address conflict with
 225          *        a preceding store
 226          */
 227         if (dse.ld_addr_blk)
 228                 val |= P(BLK, ADDR);
 229
 230         if (!dse.ld_data_blk && !dse.ld_addr_blk)
 231                 val |= P(BLK, NA);
 232
 233         return val;
 234 }
 235
 236 static u64 store_latency_data(u64 status)
 237 {
 238         union intel_x86_pebs_dse dse;
 239         u64 val;
 240
 241         dse.val = status;
 242
 243         /*
 244          * use the mapping table for bit 0-3
 245          */
 246         val = pebs_data_source[dse.st_lat_dse];
 247
 248         /*
 249          * bit 4: TLB access
 250          * 0 = did not miss 2nd level TLB
 251          * 1 = missed 2nd level TLB
 252          */
 253         if (dse.st_lat_stlb_miss)
 254                 val |= P(TLB, MISS) | P(TLB, L2);
 255         else
 256                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 257
 258         /*
 259          * bit 5: locked prefix
 260          */
 261         if (dse.st_lat_locked)
 262                 val |= P(LOCK, LOCKED);
 263
 264         val |= P(BLK, NA);
 265
 266         return val;
 267 }
 268
 269 struct pebs_record_core {
 270         u64 flags, ip;
 271         u64 ax, bx, cx, dx;
 272         u64 si, di, bp, sp;
 273         u64 r8,  r9,  r10, r11;
 274         u64 r12, r13, r14, r15;
 275 };
 276
 277 struct pebs_record_nhm {
 278         u64 flags, ip;
 279         u64 ax, bx, cx, dx;
 280         u64 si, di, bp, sp;
 281         u64 r8,  r9,  r10, r11;
 282         u64 r12, r13, r14, r15;
 283         u64 status, dla, dse, lat;
 284 };
 285
 286 /*
 287  * Same as pebs_record_nhm, with two additional fields.
 288  */
 289 struct pebs_record_hsw {
 290         u64 flags, ip;
 291         u64 ax, bx, cx, dx;
 292         u64 si, di, bp, sp;
 293         u64 r8,  r9,  r10, r11;
 294         u64 r12, r13, r14, r15;
 295         u64 status, dla, dse, lat;
 296         u64 real_ip, tsx_tuning;
 297 };
 298
 299 union hsw_tsx_tuning {
 300         struct {
 301                 u32 cycles_last_block     : 32,
 302                     hle_abort             : 1,
 303                     rtm_abort             : 1,
 304                     instruction_abort     : 1,
 305                     non_instruction_abort : 1,
 306                     retry                 : 1,
 307                     data_conflict         : 1,
 308                     capacity_writes       : 1,
 309                     capacity_reads        : 1;
 310         };
 311         u64         value;
 312 };
 313
 314 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 315
 316 /* Same as HSW, plus TSC */
 317
 318 struct pebs_record_skl {
 319         u64 flags, ip;
 320         u64 ax, bx, cx, dx;
 321         u64 si, di, bp, sp;
 322         u64 r8,  r9,  r10, r11;
 323         u64 r12, r13, r14, r15;
 324         u64 status, dla, dse, lat;
 325         u64 real_ip, tsx_tuning;
 326         u64 tsc;
 327 };
 328
 329 void init_debug_store_on_cpu(int cpu)
 330 {
 331         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 332
 333         if (!ds)
 334                 return;
 335
 336         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 337                      (u32)((u64)(unsigned long)ds),
 338                      (u32)((u64)(unsigned long)ds >> 32));
 339 }
 340
 341 void fini_debug_store_on_cpu(int cpu)
 342 {
 343         if (!per_cpu(cpu_hw_events, cpu).ds)
 344                 return;
 345
 346         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 347 }
 348
 349 static DEFINE_PER_CPU(void *, insn_buffer);
 350
 351 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
 352 {
 353         unsigned long start = (unsigned long)cea;
 354         phys_addr_t pa;
 355         size_t msz = 0;
 356
 357         pa = virt_to_phys(addr);
 358
 359         preempt_disable();
 360         for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
 361                 cea_set_pte(cea, pa, prot);
 362
 363         /*
 364          * This is a cross-CPU update of the cpu_entry_area, we must shoot down
 365          * all TLB entries for it.
 366          */
 367         flush_tlb_kernel_range(start, start + size);
 368         preempt_enable();
 369 }
 370
 371 static void ds_clear_cea(void *cea, size_t size)
 372 {
 373         unsigned long start = (unsigned long)cea;
 374         size_t msz = 0;
 375
 376         preempt_disable();
 377         for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
 378                 cea_set_pte(cea, 0, PAGE_NONE);
 379
 380         flush_tlb_kernel_range(start, start + size);
 381         preempt_enable();
 382 }
 383
 384 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
 385 {
 386         unsigned int order = get_order(size);
 387         int node = cpu_to_node(cpu);
 388         struct page *page;
 389
 390         page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
 391         return page ? page_address(page) : NULL;
 392 }
 393
 394 static void dsfree_pages(const void *buffer, size_t size)
 395 {
 396         if (buffer)
 397                 free_pages((unsigned long)buffer, get_order(size));
 398 }
 399
 400 static int alloc_pebs_buffer(int cpu)
 401 {
 402         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 403         struct debug_store *ds = hwev->ds;
 404         size_t bsiz = x86_pmu.pebs_buffer_size;
 405         int max, node = cpu_to_node(cpu);
 406         void *buffer, *insn_buff, *cea;
 407
 408         if (!x86_pmu.pebs)
 409                 return 0;
 410
 411         buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
 412         if (unlikely(!buffer))
 413                 return -ENOMEM;
 414
 415         /*
 416          * HSW+ already provides us the eventing ip; no need to allocate this
 417          * buffer then.
 418          */
 419         if (x86_pmu.intel_cap.pebs_format < 2) {
 420                 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 421                 if (!insn_buff) {
 422                         dsfree_pages(buffer, bsiz);
 423                         return -ENOMEM;
 424                 }
 425                 per_cpu(insn_buffer, cpu) = insn_buff;
 426         }
 427         hwev->ds_pebs_vaddr = buffer;
 428         /* Update the cpu entry area mapping */
 429         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
 430         ds->pebs_buffer_base = (unsigned long) cea;
 431         ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
 432         ds->pebs_index = ds->pebs_buffer_base;
 433         max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
 434         ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
 435         return 0;
 436 }
 437
 438 static void release_pebs_buffer(int cpu)
 439 {
 440         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 441         void *cea;
 442
 443         if (!x86_pmu.pebs)
 444                 return;
 445
 446         kfree(per_cpu(insn_buffer, cpu));
 447         per_cpu(insn_buffer, cpu) = NULL;
 448
 449         /* Clear the fixmap */
 450         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
 451         ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
 452         dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
 453         hwev->ds_pebs_vaddr = NULL;
 454 }
 455
 456 static int alloc_bts_buffer(int cpu)
 457 {
 458         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 459         struct debug_store *ds = hwev->ds;
 460         void *buffer, *cea;
 461         int max;
 462
 463         if (!x86_pmu.bts)
 464                 return 0;
 465
 466         buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
 467         if (unlikely(!buffer)) {
 468                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 469                 return -ENOMEM;
 470         }
 471         hwev->ds_bts_vaddr = buffer;
 472         /* Update the fixmap */
 473         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
 474         ds->bts_buffer_base = (unsigned long) cea;
 475         ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
 476         ds->bts_index = ds->bts_buffer_base;
 477         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 478         ds->bts_absolute_maximum = ds->bts_buffer_base +
 479                                         max * BTS_RECORD_SIZE;
 480         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 481                                         (max / 16) * BTS_RECORD_SIZE;
 482         return 0;
 483 }
 484
 485 static void release_bts_buffer(int cpu)
 486 {
 487         struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
 488         void *cea;
 489
 490         if (!x86_pmu.bts)
 491                 return;
 492
 493         /* Clear the fixmap */
 494         cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
 495         ds_clear_cea(cea, BTS_BUFFER_SIZE);
 496         dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
 497         hwev->ds_bts_vaddr = NULL;
 498 }
 499
 500 static int alloc_ds_buffer(int cpu)
 501 {
 502         struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
 503
 504         memset(ds, 0, sizeof(*ds));
 505         per_cpu(cpu_hw_events, cpu).ds = ds;
 506         return 0;
 507 }
 508
 509 static void release_ds_buffer(int cpu)
 510 {
 511         per_cpu(cpu_hw_events, cpu).ds = NULL;
 512 }
 513
 514 void release_ds_buffers(void)
 515 {
 516         int cpu;
 517
 518         if (!x86_pmu.bts && !x86_pmu.pebs)
 519                 return;
 520
 521         for_each_possible_cpu(cpu)
 522                 release_ds_buffer(cpu);
 523
 524         for_each_possible_cpu(cpu) {
 525                 /*
 526                  * Again, ignore errors from offline CPUs, they will no longer
 527                  * observe cpu_hw_events.ds and not program the DS_AREA when
 528                  * they come up.
 529                  */
 530                 fini_debug_store_on_cpu(cpu);
 531         }
 532
 533         for_each_possible_cpu(cpu) {
 534                 release_pebs_buffer(cpu);
 535                 release_bts_buffer(cpu);
 536         }
 537 }
 538
 539 void reserve_ds_buffers(void)
 540 {
 541         int bts_err = 0, pebs_err = 0;
 542         int cpu;
 543
 544         x86_pmu.bts_active = 0;
 545         x86_pmu.pebs_active = 0;
 546
 547         if (!x86_pmu.bts && !x86_pmu.pebs)
 548                 return;
 549
 550         if (!x86_pmu.bts)
 551                 bts_err = 1;
 552
 553         if (!x86_pmu.pebs)
 554                 pebs_err = 1;
 555
 556         for_each_possible_cpu(cpu) {
 557                 if (alloc_ds_buffer(cpu)) {
 558                         bts_err = 1;
 559                         pebs_err = 1;
 560                 }
 561
 562                 if (!bts_err && alloc_bts_buffer(cpu))
 563                         bts_err = 1;
 564
 565                 if (!pebs_err && alloc_pebs_buffer(cpu))
 566                         pebs_err = 1;
 567
 568                 if (bts_err && pebs_err)
 569                         break;
 570         }
 571
 572         if (bts_err) {
 573                 for_each_possible_cpu(cpu)
 574                         release_bts_buffer(cpu);
 575         }
 576
 577         if (pebs_err) {
 578                 for_each_possible_cpu(cpu)
 579                         release_pebs_buffer(cpu);
 580         }
 581
 582         if (bts_err && pebs_err) {
 583                 for_each_possible_cpu(cpu)
 584                         release_ds_buffer(cpu);
 585         } else {
 586                 if (x86_pmu.bts && !bts_err)
 587                         x86_pmu.bts_active = 1;
 588
 589                 if (x86_pmu.pebs && !pebs_err)
 590                         x86_pmu.pebs_active = 1;
 591
 592                 for_each_possible_cpu(cpu) {
 593                         /*
 594                          * Ignores wrmsr_on_cpu() errors for offline CPUs they
 595                          * will get this call through intel_pmu_cpu_starting().
 596                          */
 597                         init_debug_store_on_cpu(cpu);
 598                 }
 599         }
 600 }
 601
 602 /*
 603  * BTS
 604  */
 605
 606 struct event_constraint bts_constraint =
 607         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 608
 609 void intel_pmu_enable_bts(u64 config)
 610 {
 611         unsigned long debugctlmsr;
 612
 613         debugctlmsr = get_debugctlmsr();
 614
 615         debugctlmsr |= DEBUGCTLMSR_TR;
 616         debugctlmsr |= DEBUGCTLMSR_BTS;
 617         if (config & ARCH_PERFMON_EVENTSEL_INT)
 618                 debugctlmsr |= DEBUGCTLMSR_BTINT;
 619
 620         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 621                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 622
 623         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 624                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 625
 626         update_debugctlmsr(debugctlmsr);
 627 }
 628
 629 void intel_pmu_disable_bts(void)
 630 {
 631         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 632         unsigned long debugctlmsr;
 633
 634         if (!cpuc->ds)
 635                 return;
 636
 637         debugctlmsr = get_debugctlmsr();
 638
 639         debugctlmsr &=
 640                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 641                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 642
 643         update_debugctlmsr(debugctlmsr);
 644 }
 645
 646 int intel_pmu_drain_bts_buffer(void)
 647 {
 648         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 649         struct debug_store *ds = cpuc->ds;
 650         struct bts_record {
 651                 u64     from;
 652                 u64     to;
 653                 u64     flags;
 654         };
 655         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 656         struct bts_record *at, *base, *top;
 657         struct perf_output_handle handle;
 658         struct perf_event_header header;
 659         struct perf_sample_data data;
 660         unsigned long skip = 0;
 661         struct pt_regs regs;
 662
 663         if (!event)
 664                 return 0;
 665
 666         if (!x86_pmu.bts_active)
 667                 return 0;
 668
 669         base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 670         top  = (struct bts_record *)(unsigned long)ds->bts_index;
 671
 672         if (top <= base)
 673                 return 0;
 674
 675         memset(&regs, 0, sizeof(regs));
 676
 677         ds->bts_index = ds->bts_buffer_base;
 678
 679         perf_sample_data_init(&data, 0, event->hw.last_period);
 680
 681         /*
 682          * BTS leaks kernel addresses in branches across the cpl boundary,
 683          * such as traps or system calls, so unless the user is asking for
 684          * kernel tracing (and right now it's not possible), we'd need to
 685          * filter them out. But first we need to count how many of those we
 686          * have in the current batch. This is an extra O(n) pass, however,
 687          * it's much faster than the other one especially considering that
 688          * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
 689          * alloc_bts_buffer()).
 690          */
 691         for (at = base; at < top; at++) {
 692                 /*
 693                  * Note that right now *this* BTS code only works if
 694                  * attr::exclude_kernel is set, but let's keep this extra
 695                  * check here in case that changes.
 696                  */
 697                 if (event->attr.exclude_kernel &&
 698                     (kernel_ip(at->from) || kernel_ip(at->to)))
 699                         skip++;
 700         }
 701
 702         /*
 703          * Prepare a generic sample, i.e. fill in the invariant fields.
 704          * We will overwrite the from and to address before we output
 705          * the sample.
 706          */
 707         rcu_read_lock();
 708         perf_prepare_sample(&header, &data, event, &regs);
 709
 710         if (perf_output_begin(&handle, &data, event,
 711                               header.size * (top - base - skip)))
 712                 goto unlock;
 713
 714         for (at = base; at < top; at++) {
 715                 /* Filter out any records that contain kernel addresses. */
 716                 if (event->attr.exclude_kernel &&
 717                     (kernel_ip(at->from) || kernel_ip(at->to)))
 718                         continue;
 719
 720                 data.ip         = at->from;
 721                 data.addr       = at->to;
 722
 723                 perf_output_sample(&handle, &header, &data, event);
 724         }
 725
 726         perf_output_end(&handle);
 727
 728         /* There's new data available. */
 729         event->hw.interrupts++;
 730         event->pending_kill = POLL_IN;
 731 unlock:
 732         rcu_read_unlock();
 733         return 1;
 734 }
 735
 736 static inline void intel_pmu_drain_pebs_buffer(void)
 737 {
 738         struct perf_sample_data data;
 739
 740         x86_pmu.drain_pebs(NULL, &data);
 741 }
 742
 743 /*
 744  * PEBS
 745  */
 746 struct event_constraint intel_core2_pebs_event_constraints[] = {
 747         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 748         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 749         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 750         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 751         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 752         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 753         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
 754         EVENT_CONSTRAINT_END
 755 };
 756
 757 struct event_constraint intel_atom_pebs_event_constraints[] = {
 758         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 759         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 760         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 761         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 762         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
 763         /* Allow all events as PEBS with no flags */
 764         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 765         EVENT_CONSTRAINT_END
 766 };
 767
 768 struct event_constraint intel_slm_pebs_event_constraints[] = {
 769         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 770         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
 771         /* Allow all events as PEBS with no flags */
 772         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 773         EVENT_CONSTRAINT_END
 774 };
 775
 776 struct event_constraint intel_glm_pebs_event_constraints[] = {
 777         /* Allow all events as PEBS with no flags */
 778         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 779         EVENT_CONSTRAINT_END
 780 };
 781
 782 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 783         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 784         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 785         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 786         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 787         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 788         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 789         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 790         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 791         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 792         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 793         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 794         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 795         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 796         EVENT_CONSTRAINT_END
 797 };
 798
 799 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 800         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 801         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 802         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 803         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 804         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 805         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 806         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 807         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 808         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 809         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 810         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 811         /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
 812         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 813         EVENT_CONSTRAINT_END
 814 };
 815
 816 struct event_constraint intel_snb_pebs_event_constraints[] = {
 817         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 818         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 819         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 820         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 821         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 822         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 823         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 824         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 825         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 826         /* Allow all events as PEBS with no flags */
 827         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 828         EVENT_CONSTRAINT_END
 829 };
 830
 831 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 832         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 833         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 834         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 835         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 836         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 837         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 838         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 839         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 840         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 841         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 842         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 843         /* Allow all events as PEBS with no flags */
 844         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 845         EVENT_CONSTRAINT_END
 846 };
 847
 848 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 849         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 850         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 851         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 852         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 853         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 854         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 855         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 856         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 857         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 858         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 859         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 860         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 861         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 862         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 863         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 864         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 865         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 866         /* Allow all events as PEBS with no flags */
 867         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 868         EVENT_CONSTRAINT_END
 869 };
 870
 871 struct event_constraint intel_bdw_pebs_event_constraints[] = {
 872         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 873         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 874         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 875         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
 876         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 877         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 878         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 879         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 880         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 881         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 882         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 883         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 884         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 885         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 886         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 887         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 888         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 889         /* Allow all events as PEBS with no flags */
 890         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 891         EVENT_CONSTRAINT_END
 892 };
 893
 894
 895 struct event_constraint intel_skl_pebs_event_constraints[] = {
 896         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),      /* INST_RETIRED.PREC_DIST */
 897         /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
 898         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
 899         /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
 900         INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
 901         INTEL_PLD_CONSTRAINT(0x1cd, 0xf),                     /* MEM_TRANS_RETIRED.* */
 902         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
 903         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
 904         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
 905         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
 906         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
 907         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
 908         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
 909         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
 910         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_RETIRED.* */
 911         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_L3_HIT_RETIRED.* */
 912         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_L3_MISS_RETIRED.* */
 913         /* Allow all events as PEBS with no flags */
 914         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 915         EVENT_CONSTRAINT_END
 916 };
 917
 918 struct event_constraint intel_icl_pebs_event_constraints[] = {
 919         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),   /* INST_RETIRED.PREC_DIST */
 920         INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),  /* SLOTS */
 921
 922         INTEL_PLD_CONSTRAINT(0x1cd, 0xff),                      /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 923         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),    /* MEM_INST_RETIRED.LOAD */
 924         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x2d0, 0xf),    /* MEM_INST_RETIRED.STORE */
 925
 926         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
 927
 928         INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),                /* MEM_INST_RETIRED.* */
 929
 930         /*
 931          * Everything else is handled by PMU_FL_PEBS_ALL, because we
 932          * need the full constraints from the main table.
 933          */
 934
 935         EVENT_CONSTRAINT_END
 936 };
 937
 938 struct event_constraint intel_spr_pebs_event_constraints[] = {
 939         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL),
 940         INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
 941
 942         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
 943         INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
 944         INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
 945         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf),
 946         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x2d0, 0xf),
 947
 948         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
 949
 950         INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
 951
 952         /*
 953          * Everything else is handled by PMU_FL_PEBS_ALL, because we
 954          * need the full constraints from the main table.
 955          */
 956
 957         EVENT_CONSTRAINT_END
 958 };
 959
 960 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 961 {
 962         struct event_constraint *c;
 963
 964         if (!event->attr.precise_ip)
 965                 return NULL;
 966
 967         if (x86_pmu.pebs_constraints) {
 968                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 969                         if (constraint_match(c, event->hw.config)) {
 970                                 event->hw.flags |= c->flags;
 971                                 return c;
 972                         }
 973                 }
 974         }
 975
 976         /*
 977          * Extended PEBS support
 978          * Makes the PEBS code search the normal constraints.
 979          */
 980         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
 981                 return NULL;
 982
 983         return &emptyconstraint;
 984 }
 985
 986 /*
 987  * We need the sched_task callback even for per-cpu events when we use
 988  * the large interrupt threshold, such that we can provide PID and TID
 989  * to PEBS samples.
 990  */
 991 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
 992 {
 993         if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
 994                 return false;
 995
 996         return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
 997 }
 998
 999 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
1000 {
1001         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1002
1003         if (!sched_in && pebs_needs_sched_cb(cpuc))
1004                 intel_pmu_drain_pebs_buffer();
1005 }
1006
1007 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
1008 {
1009         struct debug_store *ds = cpuc->ds;
1010         int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
1011         int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1012         u64 threshold;
1013         int reserved;
1014
1015         if (cpuc->n_pebs_via_pt)
1016                 return;
1017
1018         if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1019                 reserved = max_pebs_events + num_counters_fixed;
1020         else
1021                 reserved = max_pebs_events;
1022
1023         if (cpuc->n_pebs == cpuc->n_large_pebs) {
1024                 threshold = ds->pebs_absolute_maximum -
1025                         reserved * cpuc->pebs_record_size;
1026         } else {
1027                 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
1028         }
1029
1030         ds->pebs_interrupt_threshold = threshold;
1031 }
1032
1033 static void adaptive_pebs_record_size_update(void)
1034 {
1035         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1036         u64 pebs_data_cfg = cpuc->pebs_data_cfg;
1037         int sz = sizeof(struct pebs_basic);
1038
1039         if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
1040                 sz += sizeof(struct pebs_meminfo);
1041         if (pebs_data_cfg & PEBS_DATACFG_GP)
1042                 sz += sizeof(struct pebs_gprs);
1043         if (pebs_data_cfg & PEBS_DATACFG_XMMS)
1044                 sz += sizeof(struct pebs_xmm);
1045         if (pebs_data_cfg & PEBS_DATACFG_LBRS)
1046                 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1047
1048         cpuc->pebs_record_size = sz;
1049 }
1050
1051 #define PERF_PEBS_MEMINFO_TYPE  (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC |   \
1052                                 PERF_SAMPLE_PHYS_ADDR |                      \
1053                                 PERF_SAMPLE_WEIGHT_TYPE |                    \
1054                                 PERF_SAMPLE_TRANSACTION |                    \
1055                                 PERF_SAMPLE_DATA_PAGE_SIZE)
1056
1057 static u64 pebs_update_adaptive_cfg(struct perf_event *event)
1058 {
1059         struct perf_event_attr *attr = &event->attr;
1060         u64 sample_type = attr->sample_type;
1061         u64 pebs_data_cfg = 0;
1062         bool gprs, tsx_weight;
1063
1064         if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
1065             attr->precise_ip > 1)
1066                 return pebs_data_cfg;
1067
1068         if (sample_type & PERF_PEBS_MEMINFO_TYPE)
1069                 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
1070
1071         /*
1072          * We need GPRs when:
1073          * + user requested them
1074          * + precise_ip < 2 for the non event IP
1075          * + For RTM TSX weight we need GPRs for the abort code.
1076          */
1077         gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
1078                (attr->sample_regs_intr & PEBS_GP_REGS);
1079
1080         tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
1081                      ((attr->config & INTEL_ARCH_EVENT_MASK) ==
1082                       x86_pmu.rtm_abort_event);
1083
1084         if (gprs || (attr->precise_ip < 2) || tsx_weight)
1085                 pebs_data_cfg |= PEBS_DATACFG_GP;
1086
1087         if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
1088             (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1089                 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1090
1091         if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1092                 /*
1093                  * For now always log all LBRs. Could configure this
1094                  * later.
1095                  */
1096                 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1097                         ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1098         }
1099
1100         return pebs_data_cfg;
1101 }
1102
1103 static void
1104 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1105                   struct perf_event *event, bool add)
1106 {
1107         struct pmu *pmu = event->ctx->pmu;
1108         /*
1109          * Make sure we get updated with the first PEBS
1110          * event. It will trigger also during removal, but
1111          * that does not hurt:
1112          */
1113         bool update = cpuc->n_pebs == 1;
1114
1115         if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1116                 if (!needed_cb)
1117                         perf_sched_cb_inc(pmu);
1118                 else
1119                         perf_sched_cb_dec(pmu);
1120
1121                 update = true;
1122         }
1123
1124         /*
1125          * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1126          * iterating all remaining PEBS events to reconstruct the config.
1127          */
1128         if (x86_pmu.intel_cap.pebs_baseline && add) {
1129                 u64 pebs_data_cfg;
1130
1131                 /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1132                 if (cpuc->n_pebs == 1) {
1133                         cpuc->pebs_data_cfg = 0;
1134                         cpuc->pebs_record_size = sizeof(struct pebs_basic);
1135                 }
1136
1137                 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1138
1139                 /* Update pebs_record_size if new event requires more data. */
1140                 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1141                         cpuc->pebs_data_cfg |= pebs_data_cfg;
1142                         adaptive_pebs_record_size_update();
1143                         update = true;
1144                 }
1145         }
1146
1147         if (update)
1148                 pebs_update_threshold(cpuc);
1149 }
1150
1151 void intel_pmu_pebs_add(struct perf_event *event)
1152 {
1153         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1154         struct hw_perf_event *hwc = &event->hw;
1155         bool needed_cb = pebs_needs_sched_cb(cpuc);
1156
1157         cpuc->n_pebs++;
1158         if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1159                 cpuc->n_large_pebs++;
1160         if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1161                 cpuc->n_pebs_via_pt++;
1162
1163         pebs_update_state(needed_cb, cpuc, event, true);
1164 }
1165
1166 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1167 {
1168         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1169
1170         if (!is_pebs_pt(event))
1171                 return;
1172
1173         if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1174                 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1175 }
1176
1177 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1178 {
1179         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1180         struct hw_perf_event *hwc = &event->hw;
1181         struct debug_store *ds = cpuc->ds;
1182
1183         if (!is_pebs_pt(event))
1184                 return;
1185
1186         if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1187                 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1188
1189         cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1190
1191         wrmsrl(MSR_RELOAD_PMC0 + hwc->idx, ds->pebs_event_reset[hwc->idx]);
1192 }
1193
1194 void intel_pmu_pebs_enable(struct perf_event *event)
1195 {
1196         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1197         struct hw_perf_event *hwc = &event->hw;
1198         struct debug_store *ds = cpuc->ds;
1199
1200         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1201
1202         cpuc->pebs_enabled |= 1ULL << hwc->idx;
1203
1204         if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1205                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1206         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1207                 cpuc->pebs_enabled |= 1ULL << 63;
1208
1209         if (x86_pmu.intel_cap.pebs_baseline) {
1210                 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1211                 if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1212                         wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1213                         cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1214                 }
1215         }
1216
1217         /*
1218          * Use auto-reload if possible to save a MSR write in the PMI.
1219          * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1220          */
1221         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1222                 unsigned int idx = hwc->idx;
1223
1224                 if (idx >= INTEL_PMC_IDX_FIXED)
1225                         idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1226                 ds->pebs_event_reset[idx] =
1227                         (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1228         } else {
1229                 ds->pebs_event_reset[hwc->idx] = 0;
1230         }
1231
1232         intel_pmu_pebs_via_pt_enable(event);
1233 }
1234
1235 void intel_pmu_pebs_del(struct perf_event *event)
1236 {
1237         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1238         struct hw_perf_event *hwc = &event->hw;
1239         bool needed_cb = pebs_needs_sched_cb(cpuc);
1240
1241         cpuc->n_pebs--;
1242         if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1243                 cpuc->n_large_pebs--;
1244         if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1245                 cpuc->n_pebs_via_pt--;
1246
1247         pebs_update_state(needed_cb, cpuc, event, false);
1248 }
1249
1250 void intel_pmu_pebs_disable(struct perf_event *event)
1251 {
1252         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1253         struct hw_perf_event *hwc = &event->hw;
1254
1255         if (cpuc->n_pebs == cpuc->n_large_pebs &&
1256             cpuc->n_pebs != cpuc->n_pebs_via_pt)
1257                 intel_pmu_drain_pebs_buffer();
1258
1259         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1260
1261         if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1262             (x86_pmu.version < 5))
1263                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1264         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1265                 cpuc->pebs_enabled &= ~(1ULL << 63);
1266
1267         intel_pmu_pebs_via_pt_disable(event);
1268
1269         if (cpuc->enabled)
1270                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1271
1272         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1273 }
1274
1275 void intel_pmu_pebs_enable_all(void)
1276 {
1277         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1278
1279         if (cpuc->pebs_enabled)
1280                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1281 }
1282
1283 void intel_pmu_pebs_disable_all(void)
1284 {
1285         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1286
1287         if (cpuc->pebs_enabled)
1288                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1289 }
1290
1291 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1292 {
1293         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1294         unsigned long from = cpuc->lbr_entries[0].from;
1295         unsigned long old_to, to = cpuc->lbr_entries[0].to;
1296         unsigned long ip = regs->ip;
1297         int is_64bit = 0;
1298         void *kaddr;
1299         int size;
1300
1301         /*
1302          * We don't need to fixup if the PEBS assist is fault like
1303          */
1304         if (!x86_pmu.intel_cap.pebs_trap)
1305                 return 1;
1306
1307         /*
1308          * No LBR entry, no basic block, no rewinding
1309          */
1310         if (!cpuc->lbr_stack.nr || !from || !to)
1311                 return 0;
1312
1313         /*
1314          * Basic blocks should never cross user/kernel boundaries
1315          */
1316         if (kernel_ip(ip) != kernel_ip(to))
1317                 return 0;
1318
1319         /*
1320          * unsigned math, either ip is before the start (impossible) or
1321          * the basic block is larger than 1 page (sanity)
1322          */
1323         if ((ip - to) > PEBS_FIXUP_SIZE)
1324                 return 0;
1325
1326         /*
1327          * We sampled a branch insn, rewind using the LBR stack
1328          */
1329         if (ip == to) {
1330                 set_linear_ip(regs, from);
1331                 return 1;
1332         }
1333
1334         size = ip - to;
1335         if (!kernel_ip(ip)) {
1336                 int bytes;
1337                 u8 *buf = this_cpu_read(insn_buffer);
1338
1339                 /* 'size' must fit our buffer, see above */
1340                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1341                 if (bytes != 0)
1342                         return 0;
1343
1344                 kaddr = buf;
1345         } else {
1346                 kaddr = (void *)to;
1347         }
1348
1349         do {
1350                 struct insn insn;
1351
1352                 old_to = to;
1353
1354 #ifdef CONFIG_X86_64
1355                 is_64bit = kernel_ip(to) || any_64bit_mode(regs);
1356 #endif
1357                 insn_init(&insn, kaddr, size, is_64bit);
1358                 insn_get_length(&insn);
1359                 /*
1360                  * Make sure there was not a problem decoding the
1361                  * instruction and getting the length.  This is
1362                  * doubly important because we have an infinite
1363                  * loop if insn.length=0.
1364                  */
1365                 if (!insn.length)
1366                         break;
1367
1368                 to += insn.length;
1369                 kaddr += insn.length;
1370                 size -= insn.length;
1371         } while (to < ip);
1372
1373         if (to == ip) {
1374                 set_linear_ip(regs, old_to);
1375                 return 1;
1376         }
1377
1378         /*
1379          * Even though we decoded the basic block, the instruction stream
1380          * never matched the given IP, either the TO or the IP got corrupted.
1381          */
1382         return 0;
1383 }
1384
1385 static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1386 {
1387         if (tsx_tuning) {
1388                 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1389                 return tsx.cycles_last_block;
1390         }
1391         return 0;
1392 }
1393
1394 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1395 {
1396         u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1397
1398         /* For RTM XABORTs also log the abort code from AX */
1399         if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1400                 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1401         return txn;
1402 }
1403
1404 static inline u64 get_pebs_status(void *n)
1405 {
1406         if (x86_pmu.intel_cap.pebs_format < 4)
1407                 return ((struct pebs_record_nhm *)n)->status;
1408         return ((struct pebs_basic *)n)->applicable_counters;
1409 }
1410
1411 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1412                 (PERF_X86_EVENT_PEBS_ST_HSW | \
1413                  PERF_X86_EVENT_PEBS_LD_HSW | \
1414                  PERF_X86_EVENT_PEBS_NA_HSW)
1415
1416 static u64 get_data_src(struct perf_event *event, u64 aux)
1417 {
1418         u64 val = PERF_MEM_NA;
1419         int fl = event->hw.flags;
1420         bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1421
1422         if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1423                 val = load_latency_data(aux);
1424         else if (fl & PERF_X86_EVENT_PEBS_STLAT)
1425                 val = store_latency_data(aux);
1426         else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1427                 val = precise_datala_hsw(event, aux);
1428         else if (fst)
1429                 val = precise_store_data(aux);
1430         return val;
1431 }
1432
1433 #define PERF_SAMPLE_ADDR_TYPE   (PERF_SAMPLE_ADDR |             \
1434                                  PERF_SAMPLE_PHYS_ADDR |        \
1435                                  PERF_SAMPLE_DATA_PAGE_SIZE)
1436
1437 static void setup_pebs_fixed_sample_data(struct perf_event *event,
1438                                    struct pt_regs *iregs, void *__pebs,
1439                                    struct perf_sample_data *data,
1440                                    struct pt_regs *regs)
1441 {
1442         /*
1443          * We cast to the biggest pebs_record but are careful not to
1444          * unconditionally access the 'extra' entries.
1445          */
1446         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1447         struct pebs_record_skl *pebs = __pebs;
1448         u64 sample_type;
1449         int fll;
1450
1451         if (pebs == NULL)
1452                 return;
1453
1454         sample_type = event->attr.sample_type;
1455         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1456
1457         perf_sample_data_init(data, 0, event->hw.last_period);
1458
1459         data->period = event->hw.last_period;
1460
1461         /*
1462          * Use latency for weight (only avail with PEBS-LL)
1463          */
1464         if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE))
1465                 data->weight.full = pebs->lat;
1466
1467         /*
1468          * data.data_src encodes the data source
1469          */
1470         if (sample_type & PERF_SAMPLE_DATA_SRC)
1471                 data->data_src.val = get_data_src(event, pebs->dse);
1472
1473         /*
1474          * We must however always use iregs for the unwinder to stay sane; the
1475          * record BP,SP,IP can point into thin air when the record is from a
1476          * previous PMI context or an (I)RET happened between the record and
1477          * PMI.
1478          */
1479         if (sample_type & PERF_SAMPLE_CALLCHAIN)
1480                 data->callchain = perf_callchain(event, iregs);
1481
1482         /*
1483          * We use the interrupt regs as a base because the PEBS record does not
1484          * contain a full regs set, specifically it seems to lack segment
1485          * descriptors, which get used by things like user_mode().
1486          *
1487          * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1488          */
1489         *regs = *iregs;
1490
1491         /*
1492          * Initialize regs_>flags from PEBS,
1493          * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1494          * i.e., do not rely on it being zero:
1495          */
1496         regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1497
1498         if (sample_type & PERF_SAMPLE_REGS_INTR) {
1499                 regs->ax = pebs->ax;
1500                 regs->bx = pebs->bx;
1501                 regs->cx = pebs->cx;
1502                 regs->dx = pebs->dx;
1503                 regs->si = pebs->si;
1504                 regs->di = pebs->di;
1505
1506                 regs->bp = pebs->bp;
1507                 regs->sp = pebs->sp;
1508
1509 #ifndef CONFIG_X86_32
1510                 regs->r8 = pebs->r8;
1511                 regs->r9 = pebs->r9;
1512                 regs->r10 = pebs->r10;
1513                 regs->r11 = pebs->r11;
1514                 regs->r12 = pebs->r12;
1515                 regs->r13 = pebs->r13;
1516                 regs->r14 = pebs->r14;
1517                 regs->r15 = pebs->r15;
1518 #endif
1519         }
1520
1521         if (event->attr.precise_ip > 1) {
1522                 /*
1523                  * Haswell and later processors have an 'eventing IP'
1524                  * (real IP) which fixes the off-by-1 skid in hardware.
1525                  * Use it when precise_ip >= 2 :
1526                  */
1527                 if (x86_pmu.intel_cap.pebs_format >= 2) {
1528                         set_linear_ip(regs, pebs->real_ip);
1529                         regs->flags |= PERF_EFLAGS_EXACT;
1530                 } else {
1531                         /* Otherwise, use PEBS off-by-1 IP: */
1532                         set_linear_ip(regs, pebs->ip);
1533
1534                         /*
1535                          * With precise_ip >= 2, try to fix up the off-by-1 IP
1536                          * using the LBR. If successful, the fixup function
1537                          * corrects regs->ip and calls set_linear_ip() on regs:
1538                          */
1539                         if (intel_pmu_pebs_fixup_ip(regs))
1540                                 regs->flags |= PERF_EFLAGS_EXACT;
1541                 }
1542         } else {
1543                 /*
1544                  * When precise_ip == 1, return the PEBS off-by-1 IP,
1545                  * no fixup attempted:
1546                  */
1547                 set_linear_ip(regs, pebs->ip);
1548         }
1549
1550
1551         if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
1552             x86_pmu.intel_cap.pebs_format >= 1)
1553                 data->addr = pebs->dla;
1554
1555         if (x86_pmu.intel_cap.pebs_format >= 2) {
1556                 /* Only set the TSX weight when no memory weight. */
1557                 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll)
1558                         data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
1559
1560                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1561                         data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1562                                                               pebs->ax);
1563         }
1564
1565         /*
1566          * v3 supplies an accurate time stamp, so we use that
1567          * for the time stamp.
1568          *
1569          * We can only do this for the default trace clock.
1570          */
1571         if (x86_pmu.intel_cap.pebs_format >= 3 &&
1572                 event->attr.use_clockid == 0)
1573                 data->time = native_sched_clock_from_tsc(pebs->tsc);
1574
1575         if (has_branch_stack(event))
1576                 data->br_stack = &cpuc->lbr_stack;
1577 }
1578
1579 static void adaptive_pebs_save_regs(struct pt_regs *regs,
1580                                     struct pebs_gprs *gprs)
1581 {
1582         regs->ax = gprs->ax;
1583         regs->bx = gprs->bx;
1584         regs->cx = gprs->cx;
1585         regs->dx = gprs->dx;
1586         regs->si = gprs->si;
1587         regs->di = gprs->di;
1588         regs->bp = gprs->bp;
1589         regs->sp = gprs->sp;
1590 #ifndef CONFIG_X86_32
1591         regs->r8 = gprs->r8;
1592         regs->r9 = gprs->r9;
1593         regs->r10 = gprs->r10;
1594         regs->r11 = gprs->r11;
1595         regs->r12 = gprs->r12;
1596         regs->r13 = gprs->r13;
1597         regs->r14 = gprs->r14;
1598         regs->r15 = gprs->r15;
1599 #endif
1600 }
1601
1602 #define PEBS_LATENCY_MASK                       0xffff
1603 #define PEBS_CACHE_LATENCY_OFFSET               32
1604
1605 /*
1606  * With adaptive PEBS the layout depends on what fields are configured.
1607  */
1608
1609 static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1610                                             struct pt_regs *iregs, void *__pebs,
1611                                             struct perf_sample_data *data,
1612                                             struct pt_regs *regs)
1613 {
1614         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1615         struct pebs_basic *basic = __pebs;
1616         void *next_record = basic + 1;
1617         u64 sample_type;
1618         u64 format_size;
1619         struct pebs_meminfo *meminfo = NULL;
1620         struct pebs_gprs *gprs = NULL;
1621         struct x86_perf_regs *perf_regs;
1622
1623         if (basic == NULL)
1624                 return;
1625
1626         perf_regs = container_of(regs, struct x86_perf_regs, regs);
1627         perf_regs->xmm_regs = NULL;
1628
1629         sample_type = event->attr.sample_type;
1630         format_size = basic->format_size;
1631         perf_sample_data_init(data, 0, event->hw.last_period);
1632         data->period = event->hw.last_period;
1633
1634         if (event->attr.use_clockid == 0)
1635                 data->time = native_sched_clock_from_tsc(basic->tsc);
1636
1637         /*
1638          * We must however always use iregs for the unwinder to stay sane; the
1639          * record BP,SP,IP can point into thin air when the record is from a
1640          * previous PMI context or an (I)RET happened between the record and
1641          * PMI.
1642          */
1643         if (sample_type & PERF_SAMPLE_CALLCHAIN)
1644                 data->callchain = perf_callchain(event, iregs);
1645
1646         *regs = *iregs;
1647         /* The ip in basic is EventingIP */
1648         set_linear_ip(regs, basic->ip);
1649         regs->flags = PERF_EFLAGS_EXACT;
1650
1651         /*
1652          * The record for MEMINFO is in front of GP
1653          * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1654          * Save the pointer here but process later.
1655          */
1656         if (format_size & PEBS_DATACFG_MEMINFO) {
1657                 meminfo = next_record;
1658                 next_record = meminfo + 1;
1659         }
1660
1661         if (format_size & PEBS_DATACFG_GP) {
1662                 gprs = next_record;
1663                 next_record = gprs + 1;
1664
1665                 if (event->attr.precise_ip < 2) {
1666                         set_linear_ip(regs, gprs->ip);
1667                         regs->flags &= ~PERF_EFLAGS_EXACT;
1668                 }
1669
1670                 if (sample_type & PERF_SAMPLE_REGS_INTR)
1671                         adaptive_pebs_save_regs(regs, gprs);
1672         }
1673
1674         if (format_size & PEBS_DATACFG_MEMINFO) {
1675                 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1676                         u64 weight = meminfo->latency;
1677
1678                         if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) {
1679                                 data->weight.var2_w = weight & PEBS_LATENCY_MASK;
1680                                 weight >>= PEBS_CACHE_LATENCY_OFFSET;
1681                         }
1682
1683                         /*
1684                          * Although meminfo::latency is defined as a u64,
1685                          * only the lower 32 bits include the valid data
1686                          * in practice on Ice Lake and earlier platforms.
1687                          */
1688                         if (sample_type & PERF_SAMPLE_WEIGHT) {
1689                                 data->weight.full = weight ?:
1690                                         intel_get_tsx_weight(meminfo->tsx_tuning);
1691                         } else {
1692                                 data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?:
1693                                         intel_get_tsx_weight(meminfo->tsx_tuning);
1694                         }
1695                 }
1696
1697                 if (sample_type & PERF_SAMPLE_DATA_SRC)
1698                         data->data_src.val = get_data_src(event, meminfo->aux);
1699
1700                 if (sample_type & PERF_SAMPLE_ADDR_TYPE)
1701                         data->addr = meminfo->address;
1702
1703                 if (sample_type & PERF_SAMPLE_TRANSACTION)
1704                         data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
1705                                                           gprs ? gprs->ax : 0);
1706         }
1707
1708         if (format_size & PEBS_DATACFG_XMMS) {
1709                 struct pebs_xmm *xmm = next_record;
1710
1711                 next_record = xmm + 1;
1712                 perf_regs->xmm_regs = xmm->xmm;
1713         }
1714
1715         if (format_size & PEBS_DATACFG_LBRS) {
1716                 struct lbr_entry *lbr = next_record;
1717                 int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
1718                                         & 0xff) + 1;
1719                 next_record = next_record + num_lbr * sizeof(struct lbr_entry);
1720
1721                 if (has_branch_stack(event)) {
1722                         intel_pmu_store_pebs_lbrs(lbr);
1723                         data->br_stack = &cpuc->lbr_stack;
1724                 }
1725         }
1726
1727         WARN_ONCE(next_record != __pebs + (format_size >> 48),
1728                         "PEBS record size %llu, expected %llu, config %llx\n",
1729                         format_size >> 48,
1730                         (u64)(next_record - __pebs),
1731                         basic->format_size);
1732 }
1733
1734 static inline void *
1735 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1736 {
1737         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1738         void *at;
1739         u64 pebs_status;
1740
1741         /*
1742          * fmt0 does not have a status bitfield (does not use
1743          * perf_record_nhm format)
1744          */
1745         if (x86_pmu.intel_cap.pebs_format < 1)
1746                 return base;
1747
1748         if (base == NULL)
1749                 return NULL;
1750
1751         for (at = base; at < top; at += cpuc->pebs_record_size) {
1752                 unsigned long status = get_pebs_status(at);
1753
1754                 if (test_bit(bit, (unsigned long *)&status)) {
1755                         /* PEBS v3 has accurate status bits */
1756                         if (x86_pmu.intel_cap.pebs_format >= 3)
1757                                 return at;
1758
1759                         if (status == (1 << bit))
1760                                 return at;
1761
1762                         /* clear non-PEBS bit and re-check */
1763                         pebs_status = status & cpuc->pebs_enabled;
1764                         pebs_status &= PEBS_COUNTER_MASK;
1765                         if (pebs_status == (1 << bit))
1766                                 return at;
1767                 }
1768         }
1769         return NULL;
1770 }
1771
1772 void intel_pmu_auto_reload_read(struct perf_event *event)
1773 {
1774         WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
1775
1776         perf_pmu_disable(event->pmu);
1777         intel_pmu_drain_pebs_buffer();
1778         perf_pmu_enable(event->pmu);
1779 }
1780
1781 /*
1782  * Special variant of intel_pmu_save_and_restart() for auto-reload.
1783  */
1784 static int
1785 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1786 {
1787         struct hw_perf_event *hwc = &event->hw;
1788         int shift = 64 - x86_pmu.cntval_bits;
1789         u64 period = hwc->sample_period;
1790         u64 prev_raw_count, new_raw_count;
1791         s64 new, old;
1792
1793         WARN_ON(!period);
1794
1795         /*
1796          * drain_pebs() only happens when the PMU is disabled.
1797          */
1798         WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1799
1800         prev_raw_count = local64_read(&hwc->prev_count);
1801         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1802         local64_set(&hwc->prev_count, new_raw_count);
1803
1804         /*
1805          * Since the counter increments a negative counter value and
1806          * overflows on the sign switch, giving the interval:
1807          *
1808          *   [-period, 0]
1809          *
1810          * the difference between two consequtive reads is:
1811          *
1812          *   A) value2 - value1;
1813          *      when no overflows have happened in between,
1814          *
1815          *   B) (0 - value1) + (value2 - (-period));
1816          *      when one overflow happened in between,
1817          *
1818          *   C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1819          *      when @n overflows happened in between.
1820          *
1821          * Here A) is the obvious difference, B) is the extension to the
1822          * discrete interval, where the first term is to the top of the
1823          * interval and the second term is from the bottom of the next
1824          * interval and C) the extension to multiple intervals, where the
1825          * middle term is the whole intervals covered.
1826          *
1827          * An equivalent of C, by reduction, is:
1828          *
1829          *   value2 - value1 + n * period
1830          */
1831         new = ((s64)(new_raw_count << shift) >> shift);
1832         old = ((s64)(prev_raw_count << shift) >> shift);
1833         local64_add(new - old + count * period, &event->count);
1834
1835         local64_set(&hwc->period_left, -new);
1836
1837         perf_event_update_userpage(event);
1838
1839         return 0;
1840 }
1841
1842 static __always_inline void
1843 __intel_pmu_pebs_event(struct perf_event *event,
1844                        struct pt_regs *iregs,
1845                        struct perf_sample_data *data,
1846                        void *base, void *top,
1847                        int bit, int count,
1848                        void (*setup_sample)(struct perf_event *,
1849                                             struct pt_regs *,
1850                                             void *,
1851                                             struct perf_sample_data *,
1852                                             struct pt_regs *))
1853 {
1854         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1855         struct hw_perf_event *hwc = &event->hw;
1856         struct x86_perf_regs perf_regs;
1857         struct pt_regs *regs = &perf_regs.regs;
1858         void *at = get_next_pebs_record_by_bit(base, top, bit);
1859         static struct pt_regs dummy_iregs;
1860
1861         if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1862                 /*
1863                  * Now, auto-reload is only enabled in fixed period mode.
1864                  * The reload value is always hwc->sample_period.
1865                  * May need to change it, if auto-reload is enabled in
1866                  * freq mode later.
1867                  */
1868                 intel_pmu_save_and_restart_reload(event, count);
1869         } else if (!intel_pmu_save_and_restart(event))
1870                 return;
1871
1872         if (!iregs)
1873                 iregs = &dummy_iregs;
1874
1875         while (count > 1) {
1876                 setup_sample(event, iregs, at, data, regs);
1877                 perf_event_output(event, data, regs);
1878                 at += cpuc->pebs_record_size;
1879                 at = get_next_pebs_record_by_bit(at, top, bit);
1880                 count--;
1881         }
1882
1883         setup_sample(event, iregs, at, data, regs);
1884         if (iregs == &dummy_iregs) {
1885                 /*
1886                  * The PEBS records may be drained in the non-overflow context,
1887                  * e.g., large PEBS + context switch. Perf should treat the
1888                  * last record the same as other PEBS records, and doesn't
1889                  * invoke the generic overflow handler.
1890                  */
1891                 perf_event_output(event, data, regs);
1892         } else {
1893                 /*
1894                  * All but the last records are processed.
1895                  * The last one is left to be able to call the overflow handler.
1896                  */
1897                 if (perf_event_overflow(event, data, regs))
1898                         x86_pmu_stop(event, 0);
1899         }
1900 }
1901
1902 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
1903 {
1904         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1905         struct debug_store *ds = cpuc->ds;
1906         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1907         struct pebs_record_core *at, *top;
1908         int n;
1909
1910         if (!x86_pmu.pebs_active)
1911                 return;
1912
1913         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1914         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1915
1916         /*
1917          * Whatever else happens, drain the thing
1918          */
1919         ds->pebs_index = ds->pebs_buffer_base;
1920
1921         if (!test_bit(0, cpuc->active_mask))
1922                 return;
1923
1924         WARN_ON_ONCE(!event);
1925
1926         if (!event->attr.precise_ip)
1927                 return;
1928
1929         n = top - at;
1930         if (n <= 0) {
1931                 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1932                         intel_pmu_save_and_restart_reload(event, 0);
1933                 return;
1934         }
1935
1936         __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n,
1937                                setup_pebs_fixed_sample_data);
1938 }
1939
1940 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
1941 {
1942         struct perf_event *event;
1943         int bit;
1944
1945         /*
1946          * The drain_pebs() could be called twice in a short period
1947          * for auto-reload event in pmu::read(). There are no
1948          * overflows have happened in between.
1949          * It needs to call intel_pmu_save_and_restart_reload() to
1950          * update the event->count for this case.
1951          */
1952         for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
1953                 event = cpuc->events[bit];
1954                 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1955                         intel_pmu_save_and_restart_reload(event, 0);
1956         }
1957 }
1958
1959 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
1960 {
1961         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1962         struct debug_store *ds = cpuc->ds;
1963         struct perf_event *event;
1964         void *base, *at, *top;
1965         short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1966         short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
1967         int bit, i, size;
1968         u64 mask;
1969
1970         if (!x86_pmu.pebs_active)
1971                 return;
1972
1973         base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1974         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1975
1976         ds->pebs_index = ds->pebs_buffer_base;
1977
1978         mask = (1ULL << x86_pmu.max_pebs_events) - 1;
1979         size = x86_pmu.max_pebs_events;
1980         if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
1981                 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
1982                 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
1983         }
1984
1985         if (unlikely(base >= top)) {
1986                 intel_pmu_pebs_event_update_no_drain(cpuc, size);
1987                 return;
1988         }
1989
1990         for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1991                 struct pebs_record_nhm *p = at;
1992                 u64 pebs_status;
1993
1994                 pebs_status = p->status & cpuc->pebs_enabled;
1995                 pebs_status &= mask;
1996
1997                 /* PEBS v3 has more accurate status bits */
1998                 if (x86_pmu.intel_cap.pebs_format >= 3) {
1999                         for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2000                                 counts[bit]++;
2001
2002                         continue;
2003                 }
2004
2005                 /*
2006                  * On some CPUs the PEBS status can be zero when PEBS is
2007                  * racing with clearing of GLOBAL_STATUS.
2008                  *
2009                  * Normally we would drop that record, but in the
2010                  * case when there is only a single active PEBS event
2011                  * we can assume it's for that event.
2012                  */
2013                 if (!pebs_status && cpuc->pebs_enabled &&
2014                         !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
2015                         pebs_status = cpuc->pebs_enabled;
2016
2017                 bit = find_first_bit((unsigned long *)&pebs_status,
2018                                         x86_pmu.max_pebs_events);
2019                 if (bit >= x86_pmu.max_pebs_events)
2020                         continue;
2021
2022                 /*
2023                  * The PEBS hardware does not deal well with the situation
2024                  * when events happen near to each other and multiple bits
2025                  * are set. But it should happen rarely.
2026                  *
2027                  * If these events include one PEBS and multiple non-PEBS
2028                  * events, it doesn't impact PEBS record. The record will
2029                  * be handled normally. (slow path)
2030                  *
2031                  * If these events include two or more PEBS events, the
2032                  * records for the events can be collapsed into a single
2033                  * one, and it's not possible to reconstruct all events
2034                  * that caused the PEBS record. It's called collision.
2035                  * If collision happened, the record will be dropped.
2036                  */
2037                 if (pebs_status != (1ULL << bit)) {
2038                         for_each_set_bit(i, (unsigned long *)&pebs_status, size)
2039                                 error[i]++;
2040                         continue;
2041                 }
2042
2043                 counts[bit]++;
2044         }
2045
2046         for_each_set_bit(bit, (unsigned long *)&mask, size) {
2047                 if ((counts[bit] == 0) && (error[bit] == 0))
2048                         continue;
2049
2050                 event = cpuc->events[bit];
2051                 if (WARN_ON_ONCE(!event))
2052                         continue;
2053
2054                 if (WARN_ON_ONCE(!event->attr.precise_ip))
2055                         continue;
2056
2057                 /* log dropped samples number */
2058                 if (error[bit]) {
2059                         perf_log_lost_samples(event, error[bit]);
2060
2061                         if (iregs && perf_event_account_interrupt(event))
2062                                 x86_pmu_stop(event, 0);
2063                 }
2064
2065                 if (counts[bit]) {
2066                         __intel_pmu_pebs_event(event, iregs, data, base,
2067                                                top, bit, counts[bit],
2068                                                setup_pebs_fixed_sample_data);
2069                 }
2070         }
2071 }
2072
2073 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
2074 {
2075         short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2076         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2077         int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
2078         int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2079         struct debug_store *ds = cpuc->ds;
2080         struct perf_event *event;
2081         void *base, *at, *top;
2082         int bit, size;
2083         u64 mask;
2084
2085         if (!x86_pmu.pebs_active)
2086                 return;
2087
2088         base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
2089         top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
2090
2091         ds->pebs_index = ds->pebs_buffer_base;
2092
2093         mask = ((1ULL << max_pebs_events) - 1) |
2094                (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
2095         size = INTEL_PMC_IDX_FIXED + num_counters_fixed;
2096
2097         if (unlikely(base >= top)) {
2098                 intel_pmu_pebs_event_update_no_drain(cpuc, size);
2099                 return;
2100         }
2101
2102         for (at = base; at < top; at += cpuc->pebs_record_size) {
2103                 u64 pebs_status;
2104
2105                 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
2106                 pebs_status &= mask;
2107
2108                 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2109                         counts[bit]++;
2110         }
2111
2112         for_each_set_bit(bit, (unsigned long *)&mask, size) {
2113                 if (counts[bit] == 0)
2114                         continue;
2115
2116                 event = cpuc->events[bit];
2117                 if (WARN_ON_ONCE(!event))
2118                         continue;
2119
2120                 if (WARN_ON_ONCE(!event->attr.precise_ip))
2121                         continue;
2122
2123                 __intel_pmu_pebs_event(event, iregs, data, base,
2124                                        top, bit, counts[bit],
2125                                        setup_pebs_adaptive_sample_data);
2126         }
2127 }
2128
2129 /*
2130  * BTS, PEBS probe and setup
2131  */
2132
2133 void __init intel_ds_init(void)
2134 {
2135         /*
2136          * No support for 32bit formats
2137          */
2138         if (!boot_cpu_has(X86_FEATURE_DTES64))
2139                 return;
2140
2141         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
2142         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2143         x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2144         if (x86_pmu.version <= 4)
2145                 x86_pmu.pebs_no_isolation = 1;
2146
2147         if (x86_pmu.pebs) {
2148                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
2149                 char *pebs_qual = "";
2150                 int format = x86_pmu.intel_cap.pebs_format;
2151
2152                 if (format < 4)
2153                         x86_pmu.intel_cap.pebs_baseline = 0;
2154
2155                 switch (format) {
2156                 case 0:
2157                         pr_cont("PEBS fmt0%c, ", pebs_type);
2158                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2159                         /*
2160                          * Using >PAGE_SIZE buffers makes the WRMSR to
2161                          * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2162                          * mysteriously hang on Core2.
2163                          *
2164                          * As a workaround, we don't do this.
2165                          */
2166                         x86_pmu.pebs_buffer_size = PAGE_SIZE;
2167                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2168                         break;
2169
2170                 case 1:
2171                         pr_cont("PEBS fmt1%c, ", pebs_type);
2172                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2173                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2174                         break;
2175
2176                 case 2:
2177                         pr_cont("PEBS fmt2%c, ", pebs_type);
2178                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2179                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2180                         break;
2181
2182                 case 3:
2183                         pr_cont("PEBS fmt3%c, ", pebs_type);
2184                         x86_pmu.pebs_record_size =
2185                                                 sizeof(struct pebs_record_skl);
2186                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2187                         x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2188                         break;
2189
2190                 case 4:
2191                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2192                         x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2193                         if (x86_pmu.intel_cap.pebs_baseline) {
2194                                 x86_pmu.large_pebs_flags |=
2195                                         PERF_SAMPLE_BRANCH_STACK |
2196                                         PERF_SAMPLE_TIME;
2197                                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
2198                                 pebs_qual = "-baseline";
2199                                 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2200                         } else {
2201                                 /* Only basic record supported */
2202                                 x86_pmu.large_pebs_flags &=
2203                                         ~(PERF_SAMPLE_ADDR |
2204                                           PERF_SAMPLE_TIME |
2205                                           PERF_SAMPLE_DATA_SRC |
2206                                           PERF_SAMPLE_TRANSACTION |
2207                                           PERF_SAMPLE_REGS_USER |
2208                                           PERF_SAMPLE_REGS_INTR);
2209                         }
2210                         pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2211
2212                         if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) {
2213                                 pr_cont("PEBS-via-PT, ");
2214                                 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2215                         }
2216
2217                         break;
2218
2219                 default:
2220                         pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2221                         x86_pmu.pebs = 0;
2222                 }
2223         }
2224 }
2225
2226 void perf_restore_debug_store(void)
2227 {
2228         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2229
2230         if (!x86_pmu.bts && !x86_pmu.pebs)
2231                 return;
2232
2233         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2234 }