1 // SPDX-License-Identifier: GPL-2.0-only
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
18 #include <asm/cpufeature.h>
19 #include <asm/hardirq.h>
20 #include <asm/intel-family.h>
21 #include <asm/intel_pt.h>
23 #include <asm/cpu_device_id.h>
25 #include "../perf_event.h"
28 * Intel PerfMon, used on Core and later.
30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
123 * When HT is off these events can only run on the bottom 4 counters
124 * When HT is on, they are impacted by the HT bug and require EXCL access
126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
151 * When HT is off these events can only run on the bottom 4 counters
152 * When HT is on, they are impacted by the HT bug and require EXCL access
154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
192 static struct event_constraint intel_skl_event_constraints[] = {
193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
199 * when HT is off, these can only run on the bottom 4 counters
201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
237 * Note the low 8 bits eventsel code is not a continuous field, containing
238 * some #GPing bits. These are masked out.
240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
244 static struct event_constraint intel_icl_event_constraints[] = {
245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
250 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
254 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
255 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
256 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
257 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
258 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
259 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
260 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
261 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
262 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
263 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
264 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
265 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
266 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
270 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
271 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
272 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
273 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
274 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
278 static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
279 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
280 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
281 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
282 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
286 static struct event_constraint intel_spr_event_constraints[] = {
287 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
288 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
289 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
290 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
291 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
292 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
293 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
294 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
295 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
296 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
297 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
298 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
299 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
301 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
302 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
304 * Generally event codes < 0x90 are restricted to counters 0-3.
305 * The 0x2E and 0x3C are exception, which has no restriction.
307 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
309 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
310 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
311 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
312 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
313 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
314 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
315 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
316 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
318 * Generally event codes >= 0x90 are likely to have no restrictions.
319 * The exception are defined as above.
321 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
327 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
328 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
329 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
331 static struct attribute *nhm_mem_events_attrs[] = {
332 EVENT_PTR(mem_ld_nhm),
337 * topdown events for Intel Core CPUs.
339 * The events are all in slots, which is a free slot in a 4 wide
340 * pipeline. Some events are already reported in slots, for cycle
341 * events we multiply by the pipeline width (4).
343 * With Hyper Threading on, topdown metrics are either summed or averaged
344 * between the threads of a core: (count_t0 + count_t1).
346 * For the average case the metric is always scaled to pipeline width,
347 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
350 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
351 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
352 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
353 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
354 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
355 "event=0xe,umask=0x1"); /* uops_issued.any */
356 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
357 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
358 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
359 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
360 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
361 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
362 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
363 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
366 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
367 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
368 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
369 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
370 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
371 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
372 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
373 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
374 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
376 static struct attribute *snb_events_attrs[] = {
377 EVENT_PTR(td_slots_issued),
378 EVENT_PTR(td_slots_retired),
379 EVENT_PTR(td_fetch_bubbles),
380 EVENT_PTR(td_total_slots),
381 EVENT_PTR(td_total_slots_scale),
382 EVENT_PTR(td_recovery_bubbles),
383 EVENT_PTR(td_recovery_bubbles_scale),
387 static struct attribute *snb_mem_events_attrs[] = {
388 EVENT_PTR(mem_ld_snb),
389 EVENT_PTR(mem_st_snb),
393 static struct event_constraint intel_hsw_event_constraints[] = {
394 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
395 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
396 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
397 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
398 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
399 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
400 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
401 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
402 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
403 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
404 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
405 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
408 * When HT is off these events can only run on the bottom 4 counters
409 * When HT is on, they are impacted by the HT bug and require EXCL access
411 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
412 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
413 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
414 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
419 static struct event_constraint intel_bdw_event_constraints[] = {
420 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
421 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
422 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
423 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
424 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
426 * when HT is off, these can only run on the bottom 4 counters
428 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
429 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
430 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
431 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
435 static u64 intel_pmu_event_map(int hw_event)
437 return intel_perfmon_event_map[hw_event];
440 static __initconst const u64 spr_hw_cache_event_ids
441 [PERF_COUNT_HW_CACHE_MAX]
442 [PERF_COUNT_HW_CACHE_OP_MAX]
443 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
447 [ C(RESULT_ACCESS) ] = 0x81d0,
448 [ C(RESULT_MISS) ] = 0xe124,
451 [ C(RESULT_ACCESS) ] = 0x82d0,
456 [ C(RESULT_MISS) ] = 0xe424,
459 [ C(RESULT_ACCESS) ] = -1,
460 [ C(RESULT_MISS) ] = -1,
465 [ C(RESULT_ACCESS) ] = 0x12a,
466 [ C(RESULT_MISS) ] = 0x12a,
469 [ C(RESULT_ACCESS) ] = 0x12a,
470 [ C(RESULT_MISS) ] = 0x12a,
475 [ C(RESULT_ACCESS) ] = 0x81d0,
476 [ C(RESULT_MISS) ] = 0xe12,
479 [ C(RESULT_ACCESS) ] = 0x82d0,
480 [ C(RESULT_MISS) ] = 0xe13,
485 [ C(RESULT_ACCESS) ] = -1,
486 [ C(RESULT_MISS) ] = 0xe11,
489 [ C(RESULT_ACCESS) ] = -1,
490 [ C(RESULT_MISS) ] = -1,
492 [ C(OP_PREFETCH) ] = {
493 [ C(RESULT_ACCESS) ] = -1,
494 [ C(RESULT_MISS) ] = -1,
499 [ C(RESULT_ACCESS) ] = 0x4c4,
500 [ C(RESULT_MISS) ] = 0x4c5,
503 [ C(RESULT_ACCESS) ] = -1,
504 [ C(RESULT_MISS) ] = -1,
506 [ C(OP_PREFETCH) ] = {
507 [ C(RESULT_ACCESS) ] = -1,
508 [ C(RESULT_MISS) ] = -1,
513 [ C(RESULT_ACCESS) ] = 0x12a,
514 [ C(RESULT_MISS) ] = 0x12a,
519 static __initconst const u64 spr_hw_cache_extra_regs
520 [PERF_COUNT_HW_CACHE_MAX]
521 [PERF_COUNT_HW_CACHE_OP_MAX]
522 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
526 [ C(RESULT_ACCESS) ] = 0x10001,
527 [ C(RESULT_MISS) ] = 0x3fbfc00001,
530 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
531 [ C(RESULT_MISS) ] = 0x3f3fc00002,
536 [ C(RESULT_ACCESS) ] = 0x10c000001,
537 [ C(RESULT_MISS) ] = 0x3fb3000001,
543 * Notes on the events:
544 * - data reads do not include code reads (comparable to earlier tables)
545 * - data counts include speculative execution (except L1 write, dtlb, bpu)
546 * - remote node access includes remote memory, remote cache, remote mmio.
547 * - prefetches are not included in the counts.
548 * - icache miss does not include decoded icache
551 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
552 #define SKL_DEMAND_RFO BIT_ULL(1)
553 #define SKL_ANY_RESPONSE BIT_ULL(16)
554 #define SKL_SUPPLIER_NONE BIT_ULL(17)
555 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
556 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
557 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
558 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
559 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
560 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
561 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
562 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
563 #define SKL_SPL_HIT BIT_ULL(30)
564 #define SKL_SNOOP_NONE BIT_ULL(31)
565 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
566 #define SKL_SNOOP_MISS BIT_ULL(33)
567 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
568 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
569 #define SKL_SNOOP_HITM BIT_ULL(36)
570 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
571 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
572 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
573 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
574 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
575 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
576 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
577 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
578 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
579 SKL_SNOOP_HITM|SKL_SPL_HIT)
580 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
581 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
582 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
583 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
584 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
586 static __initconst const u64 skl_hw_cache_event_ids
587 [PERF_COUNT_HW_CACHE_MAX]
588 [PERF_COUNT_HW_CACHE_OP_MAX]
589 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
593 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
594 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
597 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
598 [ C(RESULT_MISS) ] = 0x0,
600 [ C(OP_PREFETCH) ] = {
601 [ C(RESULT_ACCESS) ] = 0x0,
602 [ C(RESULT_MISS) ] = 0x0,
607 [ C(RESULT_ACCESS) ] = 0x0,
608 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
611 [ C(RESULT_ACCESS) ] = -1,
612 [ C(RESULT_MISS) ] = -1,
614 [ C(OP_PREFETCH) ] = {
615 [ C(RESULT_ACCESS) ] = 0x0,
616 [ C(RESULT_MISS) ] = 0x0,
621 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
622 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
625 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
626 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
628 [ C(OP_PREFETCH) ] = {
629 [ C(RESULT_ACCESS) ] = 0x0,
630 [ C(RESULT_MISS) ] = 0x0,
635 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
636 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
639 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
640 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
642 [ C(OP_PREFETCH) ] = {
643 [ C(RESULT_ACCESS) ] = 0x0,
644 [ C(RESULT_MISS) ] = 0x0,
649 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
650 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
653 [ C(RESULT_ACCESS) ] = -1,
654 [ C(RESULT_MISS) ] = -1,
656 [ C(OP_PREFETCH) ] = {
657 [ C(RESULT_ACCESS) ] = -1,
658 [ C(RESULT_MISS) ] = -1,
663 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
664 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
667 [ C(RESULT_ACCESS) ] = -1,
668 [ C(RESULT_MISS) ] = -1,
670 [ C(OP_PREFETCH) ] = {
671 [ C(RESULT_ACCESS) ] = -1,
672 [ C(RESULT_MISS) ] = -1,
677 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
678 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
681 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
682 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
684 [ C(OP_PREFETCH) ] = {
685 [ C(RESULT_ACCESS) ] = 0x0,
686 [ C(RESULT_MISS) ] = 0x0,
691 static __initconst const u64 skl_hw_cache_extra_regs
692 [PERF_COUNT_HW_CACHE_MAX]
693 [PERF_COUNT_HW_CACHE_OP_MAX]
694 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
698 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
699 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
700 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
701 SKL_L3_MISS|SKL_ANY_SNOOP|
705 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
706 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
707 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
708 SKL_L3_MISS|SKL_ANY_SNOOP|
711 [ C(OP_PREFETCH) ] = {
712 [ C(RESULT_ACCESS) ] = 0x0,
713 [ C(RESULT_MISS) ] = 0x0,
718 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
719 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
720 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
721 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
724 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
725 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
726 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
727 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
729 [ C(OP_PREFETCH) ] = {
730 [ C(RESULT_ACCESS) ] = 0x0,
731 [ C(RESULT_MISS) ] = 0x0,
736 #define SNB_DMND_DATA_RD (1ULL << 0)
737 #define SNB_DMND_RFO (1ULL << 1)
738 #define SNB_DMND_IFETCH (1ULL << 2)
739 #define SNB_DMND_WB (1ULL << 3)
740 #define SNB_PF_DATA_RD (1ULL << 4)
741 #define SNB_PF_RFO (1ULL << 5)
742 #define SNB_PF_IFETCH (1ULL << 6)
743 #define SNB_LLC_DATA_RD (1ULL << 7)
744 #define SNB_LLC_RFO (1ULL << 8)
745 #define SNB_LLC_IFETCH (1ULL << 9)
746 #define SNB_BUS_LOCKS (1ULL << 10)
747 #define SNB_STRM_ST (1ULL << 11)
748 #define SNB_OTHER (1ULL << 15)
749 #define SNB_RESP_ANY (1ULL << 16)
750 #define SNB_NO_SUPP (1ULL << 17)
751 #define SNB_LLC_HITM (1ULL << 18)
752 #define SNB_LLC_HITE (1ULL << 19)
753 #define SNB_LLC_HITS (1ULL << 20)
754 #define SNB_LLC_HITF (1ULL << 21)
755 #define SNB_LOCAL (1ULL << 22)
756 #define SNB_REMOTE (0xffULL << 23)
757 #define SNB_SNP_NONE (1ULL << 31)
758 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
759 #define SNB_SNP_MISS (1ULL << 33)
760 #define SNB_NO_FWD (1ULL << 34)
761 #define SNB_SNP_FWD (1ULL << 35)
762 #define SNB_HITM (1ULL << 36)
763 #define SNB_NON_DRAM (1ULL << 37)
765 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
766 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
767 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
769 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
770 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
773 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
774 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
776 #define SNB_L3_ACCESS SNB_RESP_ANY
777 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
779 static __initconst const u64 snb_hw_cache_extra_regs
780 [PERF_COUNT_HW_CACHE_MAX]
781 [PERF_COUNT_HW_CACHE_OP_MAX]
782 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
786 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
787 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
790 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
791 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
793 [ C(OP_PREFETCH) ] = {
794 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
795 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
800 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
801 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
804 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
805 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
807 [ C(OP_PREFETCH) ] = {
808 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
809 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
814 static __initconst const u64 snb_hw_cache_event_ids
815 [PERF_COUNT_HW_CACHE_MAX]
816 [PERF_COUNT_HW_CACHE_OP_MAX]
817 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
821 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
822 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
825 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
826 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
828 [ C(OP_PREFETCH) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0,
830 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
835 [ C(RESULT_ACCESS) ] = 0x0,
836 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
842 [ C(OP_PREFETCH) ] = {
843 [ C(RESULT_ACCESS) ] = 0x0,
844 [ C(RESULT_MISS) ] = 0x0,
849 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
850 [ C(RESULT_ACCESS) ] = 0x01b7,
851 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
852 [ C(RESULT_MISS) ] = 0x01b7,
855 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
856 [ C(RESULT_ACCESS) ] = 0x01b7,
857 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
858 [ C(RESULT_MISS) ] = 0x01b7,
860 [ C(OP_PREFETCH) ] = {
861 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
862 [ C(RESULT_ACCESS) ] = 0x01b7,
863 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
864 [ C(RESULT_MISS) ] = 0x01b7,
869 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
870 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
873 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
874 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
876 [ C(OP_PREFETCH) ] = {
877 [ C(RESULT_ACCESS) ] = 0x0,
878 [ C(RESULT_MISS) ] = 0x0,
883 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
884 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
887 [ C(RESULT_ACCESS) ] = -1,
888 [ C(RESULT_MISS) ] = -1,
890 [ C(OP_PREFETCH) ] = {
891 [ C(RESULT_ACCESS) ] = -1,
892 [ C(RESULT_MISS) ] = -1,
897 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
898 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
901 [ C(RESULT_ACCESS) ] = -1,
902 [ C(RESULT_MISS) ] = -1,
904 [ C(OP_PREFETCH) ] = {
905 [ C(RESULT_ACCESS) ] = -1,
906 [ C(RESULT_MISS) ] = -1,
911 [ C(RESULT_ACCESS) ] = 0x01b7,
912 [ C(RESULT_MISS) ] = 0x01b7,
915 [ C(RESULT_ACCESS) ] = 0x01b7,
916 [ C(RESULT_MISS) ] = 0x01b7,
918 [ C(OP_PREFETCH) ] = {
919 [ C(RESULT_ACCESS) ] = 0x01b7,
920 [ C(RESULT_MISS) ] = 0x01b7,
927 * Notes on the events:
928 * - data reads do not include code reads (comparable to earlier tables)
929 * - data counts include speculative execution (except L1 write, dtlb, bpu)
930 * - remote node access includes remote memory, remote cache, remote mmio.
931 * - prefetches are not included in the counts because they are not
935 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
936 #define HSW_DEMAND_RFO BIT_ULL(1)
937 #define HSW_ANY_RESPONSE BIT_ULL(16)
938 #define HSW_SUPPLIER_NONE BIT_ULL(17)
939 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
940 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
941 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
942 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
943 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
944 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
945 HSW_L3_MISS_REMOTE_HOP2P)
946 #define HSW_SNOOP_NONE BIT_ULL(31)
947 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
948 #define HSW_SNOOP_MISS BIT_ULL(33)
949 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
950 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
951 #define HSW_SNOOP_HITM BIT_ULL(36)
952 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
953 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
954 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
955 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
956 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
957 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
958 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
959 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
960 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
961 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
962 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
964 #define BDW_L3_MISS_LOCAL BIT(26)
965 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
966 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
967 HSW_L3_MISS_REMOTE_HOP2P)
970 static __initconst const u64 hsw_hw_cache_event_ids
971 [PERF_COUNT_HW_CACHE_MAX]
972 [PERF_COUNT_HW_CACHE_OP_MAX]
973 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
977 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
978 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
981 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
982 [ C(RESULT_MISS) ] = 0x0,
984 [ C(OP_PREFETCH) ] = {
985 [ C(RESULT_ACCESS) ] = 0x0,
986 [ C(RESULT_MISS) ] = 0x0,
991 [ C(RESULT_ACCESS) ] = 0x0,
992 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
995 [ C(RESULT_ACCESS) ] = -1,
996 [ C(RESULT_MISS) ] = -1,
998 [ C(OP_PREFETCH) ] = {
999 [ C(RESULT_ACCESS) ] = 0x0,
1000 [ C(RESULT_MISS) ] = 0x0,
1005 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1006 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1009 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1010 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1012 [ C(OP_PREFETCH) ] = {
1013 [ C(RESULT_ACCESS) ] = 0x0,
1014 [ C(RESULT_MISS) ] = 0x0,
1019 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1020 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1023 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1024 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1026 [ C(OP_PREFETCH) ] = {
1027 [ C(RESULT_ACCESS) ] = 0x0,
1028 [ C(RESULT_MISS) ] = 0x0,
1033 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1034 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1037 [ C(RESULT_ACCESS) ] = -1,
1038 [ C(RESULT_MISS) ] = -1,
1040 [ C(OP_PREFETCH) ] = {
1041 [ C(RESULT_ACCESS) ] = -1,
1042 [ C(RESULT_MISS) ] = -1,
1047 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1048 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1051 [ C(RESULT_ACCESS) ] = -1,
1052 [ C(RESULT_MISS) ] = -1,
1054 [ C(OP_PREFETCH) ] = {
1055 [ C(RESULT_ACCESS) ] = -1,
1056 [ C(RESULT_MISS) ] = -1,
1061 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1062 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1065 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1066 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1068 [ C(OP_PREFETCH) ] = {
1069 [ C(RESULT_ACCESS) ] = 0x0,
1070 [ C(RESULT_MISS) ] = 0x0,
1075 static __initconst const u64 hsw_hw_cache_extra_regs
1076 [PERF_COUNT_HW_CACHE_MAX]
1077 [PERF_COUNT_HW_CACHE_OP_MAX]
1078 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1082 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1084 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1085 HSW_L3_MISS|HSW_ANY_SNOOP,
1088 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1090 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1091 HSW_L3_MISS|HSW_ANY_SNOOP,
1093 [ C(OP_PREFETCH) ] = {
1094 [ C(RESULT_ACCESS) ] = 0x0,
1095 [ C(RESULT_MISS) ] = 0x0,
1100 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1101 HSW_L3_MISS_LOCAL_DRAM|
1103 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1108 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1109 HSW_L3_MISS_LOCAL_DRAM|
1111 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1115 [ C(OP_PREFETCH) ] = {
1116 [ C(RESULT_ACCESS) ] = 0x0,
1117 [ C(RESULT_MISS) ] = 0x0,
1122 static __initconst const u64 westmere_hw_cache_event_ids
1123 [PERF_COUNT_HW_CACHE_MAX]
1124 [PERF_COUNT_HW_CACHE_OP_MAX]
1125 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1129 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1130 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1133 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1134 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1136 [ C(OP_PREFETCH) ] = {
1137 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1138 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1143 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1144 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1147 [ C(RESULT_ACCESS) ] = -1,
1148 [ C(RESULT_MISS) ] = -1,
1150 [ C(OP_PREFETCH) ] = {
1151 [ C(RESULT_ACCESS) ] = 0x0,
1152 [ C(RESULT_MISS) ] = 0x0,
1157 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1158 [ C(RESULT_ACCESS) ] = 0x01b7,
1159 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1160 [ C(RESULT_MISS) ] = 0x01b7,
1163 * Use RFO, not WRITEBACK, because a write miss would typically occur
1167 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1168 [ C(RESULT_ACCESS) ] = 0x01b7,
1169 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1170 [ C(RESULT_MISS) ] = 0x01b7,
1172 [ C(OP_PREFETCH) ] = {
1173 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1174 [ C(RESULT_ACCESS) ] = 0x01b7,
1175 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1176 [ C(RESULT_MISS) ] = 0x01b7,
1181 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1182 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1185 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1186 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1188 [ C(OP_PREFETCH) ] = {
1189 [ C(RESULT_ACCESS) ] = 0x0,
1190 [ C(RESULT_MISS) ] = 0x0,
1195 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1196 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1199 [ C(RESULT_ACCESS) ] = -1,
1200 [ C(RESULT_MISS) ] = -1,
1202 [ C(OP_PREFETCH) ] = {
1203 [ C(RESULT_ACCESS) ] = -1,
1204 [ C(RESULT_MISS) ] = -1,
1209 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1210 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1213 [ C(RESULT_ACCESS) ] = -1,
1214 [ C(RESULT_MISS) ] = -1,
1216 [ C(OP_PREFETCH) ] = {
1217 [ C(RESULT_ACCESS) ] = -1,
1218 [ C(RESULT_MISS) ] = -1,
1223 [ C(RESULT_ACCESS) ] = 0x01b7,
1224 [ C(RESULT_MISS) ] = 0x01b7,
1227 [ C(RESULT_ACCESS) ] = 0x01b7,
1228 [ C(RESULT_MISS) ] = 0x01b7,
1230 [ C(OP_PREFETCH) ] = {
1231 [ C(RESULT_ACCESS) ] = 0x01b7,
1232 [ C(RESULT_MISS) ] = 0x01b7,
1238 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1239 * See IA32 SDM Vol 3B 30.6.1.3
1242 #define NHM_DMND_DATA_RD (1 << 0)
1243 #define NHM_DMND_RFO (1 << 1)
1244 #define NHM_DMND_IFETCH (1 << 2)
1245 #define NHM_DMND_WB (1 << 3)
1246 #define NHM_PF_DATA_RD (1 << 4)
1247 #define NHM_PF_DATA_RFO (1 << 5)
1248 #define NHM_PF_IFETCH (1 << 6)
1249 #define NHM_OFFCORE_OTHER (1 << 7)
1250 #define NHM_UNCORE_HIT (1 << 8)
1251 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1252 #define NHM_OTHER_CORE_HITM (1 << 10)
1254 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1255 #define NHM_REMOTE_DRAM (1 << 13)
1256 #define NHM_LOCAL_DRAM (1 << 14)
1257 #define NHM_NON_DRAM (1 << 15)
1259 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1260 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1262 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1263 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1264 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1266 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1267 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1268 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1270 static __initconst const u64 nehalem_hw_cache_extra_regs
1271 [PERF_COUNT_HW_CACHE_MAX]
1272 [PERF_COUNT_HW_CACHE_OP_MAX]
1273 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1277 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1278 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1281 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1282 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1284 [ C(OP_PREFETCH) ] = {
1285 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1286 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1291 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1292 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1295 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1296 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1298 [ C(OP_PREFETCH) ] = {
1299 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1300 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1305 static __initconst const u64 nehalem_hw_cache_event_ids
1306 [PERF_COUNT_HW_CACHE_MAX]
1307 [PERF_COUNT_HW_CACHE_OP_MAX]
1308 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1312 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1313 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1316 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1317 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1319 [ C(OP_PREFETCH) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1321 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1326 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1327 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1330 [ C(RESULT_ACCESS) ] = -1,
1331 [ C(RESULT_MISS) ] = -1,
1333 [ C(OP_PREFETCH) ] = {
1334 [ C(RESULT_ACCESS) ] = 0x0,
1335 [ C(RESULT_MISS) ] = 0x0,
1340 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1341 [ C(RESULT_ACCESS) ] = 0x01b7,
1342 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1343 [ C(RESULT_MISS) ] = 0x01b7,
1346 * Use RFO, not WRITEBACK, because a write miss would typically occur
1350 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1351 [ C(RESULT_ACCESS) ] = 0x01b7,
1352 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1353 [ C(RESULT_MISS) ] = 0x01b7,
1355 [ C(OP_PREFETCH) ] = {
1356 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1357 [ C(RESULT_ACCESS) ] = 0x01b7,
1358 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1359 [ C(RESULT_MISS) ] = 0x01b7,
1364 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1365 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1368 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1369 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1371 [ C(OP_PREFETCH) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x0,
1373 [ C(RESULT_MISS) ] = 0x0,
1378 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1379 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1382 [ C(RESULT_ACCESS) ] = -1,
1383 [ C(RESULT_MISS) ] = -1,
1385 [ C(OP_PREFETCH) ] = {
1386 [ C(RESULT_ACCESS) ] = -1,
1387 [ C(RESULT_MISS) ] = -1,
1392 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1393 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1396 [ C(RESULT_ACCESS) ] = -1,
1397 [ C(RESULT_MISS) ] = -1,
1399 [ C(OP_PREFETCH) ] = {
1400 [ C(RESULT_ACCESS) ] = -1,
1401 [ C(RESULT_MISS) ] = -1,
1406 [ C(RESULT_ACCESS) ] = 0x01b7,
1407 [ C(RESULT_MISS) ] = 0x01b7,
1410 [ C(RESULT_ACCESS) ] = 0x01b7,
1411 [ C(RESULT_MISS) ] = 0x01b7,
1413 [ C(OP_PREFETCH) ] = {
1414 [ C(RESULT_ACCESS) ] = 0x01b7,
1415 [ C(RESULT_MISS) ] = 0x01b7,
1420 static __initconst const u64 core2_hw_cache_event_ids
1421 [PERF_COUNT_HW_CACHE_MAX]
1422 [PERF_COUNT_HW_CACHE_OP_MAX]
1423 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1427 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1428 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1431 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1432 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1434 [ C(OP_PREFETCH) ] = {
1435 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1436 [ C(RESULT_MISS) ] = 0,
1441 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1442 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1445 [ C(RESULT_ACCESS) ] = -1,
1446 [ C(RESULT_MISS) ] = -1,
1448 [ C(OP_PREFETCH) ] = {
1449 [ C(RESULT_ACCESS) ] = 0,
1450 [ C(RESULT_MISS) ] = 0,
1455 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1456 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1459 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1460 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1462 [ C(OP_PREFETCH) ] = {
1463 [ C(RESULT_ACCESS) ] = 0,
1464 [ C(RESULT_MISS) ] = 0,
1469 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1470 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1473 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1474 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1476 [ C(OP_PREFETCH) ] = {
1477 [ C(RESULT_ACCESS) ] = 0,
1478 [ C(RESULT_MISS) ] = 0,
1483 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1484 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1487 [ C(RESULT_ACCESS) ] = -1,
1488 [ C(RESULT_MISS) ] = -1,
1490 [ C(OP_PREFETCH) ] = {
1491 [ C(RESULT_ACCESS) ] = -1,
1492 [ C(RESULT_MISS) ] = -1,
1497 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1498 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1501 [ C(RESULT_ACCESS) ] = -1,
1502 [ C(RESULT_MISS) ] = -1,
1504 [ C(OP_PREFETCH) ] = {
1505 [ C(RESULT_ACCESS) ] = -1,
1506 [ C(RESULT_MISS) ] = -1,
1511 static __initconst const u64 atom_hw_cache_event_ids
1512 [PERF_COUNT_HW_CACHE_MAX]
1513 [PERF_COUNT_HW_CACHE_OP_MAX]
1514 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1518 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1519 [ C(RESULT_MISS) ] = 0,
1522 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1523 [ C(RESULT_MISS) ] = 0,
1525 [ C(OP_PREFETCH) ] = {
1526 [ C(RESULT_ACCESS) ] = 0x0,
1527 [ C(RESULT_MISS) ] = 0,
1532 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1533 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1539 [ C(OP_PREFETCH) ] = {
1540 [ C(RESULT_ACCESS) ] = 0,
1541 [ C(RESULT_MISS) ] = 0,
1546 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1547 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1550 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1551 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1553 [ C(OP_PREFETCH) ] = {
1554 [ C(RESULT_ACCESS) ] = 0,
1555 [ C(RESULT_MISS) ] = 0,
1560 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1561 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1564 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1565 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1567 [ C(OP_PREFETCH) ] = {
1568 [ C(RESULT_ACCESS) ] = 0,
1569 [ C(RESULT_MISS) ] = 0,
1574 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1575 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1578 [ C(RESULT_ACCESS) ] = -1,
1579 [ C(RESULT_MISS) ] = -1,
1581 [ C(OP_PREFETCH) ] = {
1582 [ C(RESULT_ACCESS) ] = -1,
1583 [ C(RESULT_MISS) ] = -1,
1588 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1589 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1592 [ C(RESULT_ACCESS) ] = -1,
1593 [ C(RESULT_MISS) ] = -1,
1595 [ C(OP_PREFETCH) ] = {
1596 [ C(RESULT_ACCESS) ] = -1,
1597 [ C(RESULT_MISS) ] = -1,
1602 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1603 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1604 /* no_alloc_cycles.not_delivered */
1605 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1606 "event=0xca,umask=0x50");
1607 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1608 /* uops_retired.all */
1609 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1610 "event=0xc2,umask=0x10");
1611 /* uops_retired.all */
1612 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1613 "event=0xc2,umask=0x10");
1615 static struct attribute *slm_events_attrs[] = {
1616 EVENT_PTR(td_total_slots_slm),
1617 EVENT_PTR(td_total_slots_scale_slm),
1618 EVENT_PTR(td_fetch_bubbles_slm),
1619 EVENT_PTR(td_fetch_bubbles_scale_slm),
1620 EVENT_PTR(td_slots_issued_slm),
1621 EVENT_PTR(td_slots_retired_slm),
1625 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1627 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1628 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1629 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1633 #define SLM_DMND_READ SNB_DMND_DATA_RD
1634 #define SLM_DMND_WRITE SNB_DMND_RFO
1635 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1637 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1638 #define SLM_LLC_ACCESS SNB_RESP_ANY
1639 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1641 static __initconst const u64 slm_hw_cache_extra_regs
1642 [PERF_COUNT_HW_CACHE_MAX]
1643 [PERF_COUNT_HW_CACHE_OP_MAX]
1644 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1648 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1649 [ C(RESULT_MISS) ] = 0,
1652 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1653 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1655 [ C(OP_PREFETCH) ] = {
1656 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1657 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1662 static __initconst const u64 slm_hw_cache_event_ids
1663 [PERF_COUNT_HW_CACHE_MAX]
1664 [PERF_COUNT_HW_CACHE_OP_MAX]
1665 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1669 [ C(RESULT_ACCESS) ] = 0,
1670 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1673 [ C(RESULT_ACCESS) ] = 0,
1674 [ C(RESULT_MISS) ] = 0,
1676 [ C(OP_PREFETCH) ] = {
1677 [ C(RESULT_ACCESS) ] = 0,
1678 [ C(RESULT_MISS) ] = 0,
1683 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1684 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1687 [ C(RESULT_ACCESS) ] = -1,
1688 [ C(RESULT_MISS) ] = -1,
1690 [ C(OP_PREFETCH) ] = {
1691 [ C(RESULT_ACCESS) ] = 0,
1692 [ C(RESULT_MISS) ] = 0,
1697 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1698 [ C(RESULT_ACCESS) ] = 0x01b7,
1699 [ C(RESULT_MISS) ] = 0,
1702 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1703 [ C(RESULT_ACCESS) ] = 0x01b7,
1704 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1705 [ C(RESULT_MISS) ] = 0x01b7,
1707 [ C(OP_PREFETCH) ] = {
1708 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1709 [ C(RESULT_ACCESS) ] = 0x01b7,
1710 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1711 [ C(RESULT_MISS) ] = 0x01b7,
1716 [ C(RESULT_ACCESS) ] = 0,
1717 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1720 [ C(RESULT_ACCESS) ] = 0,
1721 [ C(RESULT_MISS) ] = 0,
1723 [ C(OP_PREFETCH) ] = {
1724 [ C(RESULT_ACCESS) ] = 0,
1725 [ C(RESULT_MISS) ] = 0,
1730 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1731 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1734 [ C(RESULT_ACCESS) ] = -1,
1735 [ C(RESULT_MISS) ] = -1,
1737 [ C(OP_PREFETCH) ] = {
1738 [ C(RESULT_ACCESS) ] = -1,
1739 [ C(RESULT_MISS) ] = -1,
1744 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1745 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1748 [ C(RESULT_ACCESS) ] = -1,
1749 [ C(RESULT_MISS) ] = -1,
1751 [ C(OP_PREFETCH) ] = {
1752 [ C(RESULT_ACCESS) ] = -1,
1753 [ C(RESULT_MISS) ] = -1,
1758 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1759 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1760 /* UOPS_NOT_DELIVERED.ANY */
1761 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1762 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1763 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1764 /* UOPS_RETIRED.ANY */
1765 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1766 /* UOPS_ISSUED.ANY */
1767 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1769 static struct attribute *glm_events_attrs[] = {
1770 EVENT_PTR(td_total_slots_glm),
1771 EVENT_PTR(td_total_slots_scale_glm),
1772 EVENT_PTR(td_fetch_bubbles_glm),
1773 EVENT_PTR(td_recovery_bubbles_glm),
1774 EVENT_PTR(td_slots_issued_glm),
1775 EVENT_PTR(td_slots_retired_glm),
1779 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1780 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1781 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1782 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1786 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1787 #define GLM_DEMAND_RFO BIT_ULL(1)
1788 #define GLM_ANY_RESPONSE BIT_ULL(16)
1789 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1790 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1791 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1792 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1793 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1794 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1795 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1797 static __initconst const u64 glm_hw_cache_event_ids
1798 [PERF_COUNT_HW_CACHE_MAX]
1799 [PERF_COUNT_HW_CACHE_OP_MAX]
1800 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1803 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1804 [C(RESULT_MISS)] = 0x0,
1807 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1808 [C(RESULT_MISS)] = 0x0,
1810 [C(OP_PREFETCH)] = {
1811 [C(RESULT_ACCESS)] = 0x0,
1812 [C(RESULT_MISS)] = 0x0,
1817 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1818 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1821 [C(RESULT_ACCESS)] = -1,
1822 [C(RESULT_MISS)] = -1,
1824 [C(OP_PREFETCH)] = {
1825 [C(RESULT_ACCESS)] = 0x0,
1826 [C(RESULT_MISS)] = 0x0,
1831 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1832 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1835 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1836 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1838 [C(OP_PREFETCH)] = {
1839 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1840 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1845 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1846 [C(RESULT_MISS)] = 0x0,
1849 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1850 [C(RESULT_MISS)] = 0x0,
1852 [C(OP_PREFETCH)] = {
1853 [C(RESULT_ACCESS)] = 0x0,
1854 [C(RESULT_MISS)] = 0x0,
1859 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1860 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1863 [C(RESULT_ACCESS)] = -1,
1864 [C(RESULT_MISS)] = -1,
1866 [C(OP_PREFETCH)] = {
1867 [C(RESULT_ACCESS)] = -1,
1868 [C(RESULT_MISS)] = -1,
1873 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1874 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1877 [C(RESULT_ACCESS)] = -1,
1878 [C(RESULT_MISS)] = -1,
1880 [C(OP_PREFETCH)] = {
1881 [C(RESULT_ACCESS)] = -1,
1882 [C(RESULT_MISS)] = -1,
1887 static __initconst const u64 glm_hw_cache_extra_regs
1888 [PERF_COUNT_HW_CACHE_MAX]
1889 [PERF_COUNT_HW_CACHE_OP_MAX]
1890 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1893 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1895 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1899 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1901 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1904 [C(OP_PREFETCH)] = {
1905 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1907 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1913 static __initconst const u64 glp_hw_cache_event_ids
1914 [PERF_COUNT_HW_CACHE_MAX]
1915 [PERF_COUNT_HW_CACHE_OP_MAX]
1916 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1919 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1920 [C(RESULT_MISS)] = 0x0,
1923 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1924 [C(RESULT_MISS)] = 0x0,
1926 [C(OP_PREFETCH)] = {
1927 [C(RESULT_ACCESS)] = 0x0,
1928 [C(RESULT_MISS)] = 0x0,
1933 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1934 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1937 [C(RESULT_ACCESS)] = -1,
1938 [C(RESULT_MISS)] = -1,
1940 [C(OP_PREFETCH)] = {
1941 [C(RESULT_ACCESS)] = 0x0,
1942 [C(RESULT_MISS)] = 0x0,
1947 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1948 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1951 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1952 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1954 [C(OP_PREFETCH)] = {
1955 [C(RESULT_ACCESS)] = 0x0,
1956 [C(RESULT_MISS)] = 0x0,
1961 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1962 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1965 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1966 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1968 [C(OP_PREFETCH)] = {
1969 [C(RESULT_ACCESS)] = 0x0,
1970 [C(RESULT_MISS)] = 0x0,
1975 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1976 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1979 [C(RESULT_ACCESS)] = -1,
1980 [C(RESULT_MISS)] = -1,
1982 [C(OP_PREFETCH)] = {
1983 [C(RESULT_ACCESS)] = -1,
1984 [C(RESULT_MISS)] = -1,
1989 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1990 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1993 [C(RESULT_ACCESS)] = -1,
1994 [C(RESULT_MISS)] = -1,
1996 [C(OP_PREFETCH)] = {
1997 [C(RESULT_ACCESS)] = -1,
1998 [C(RESULT_MISS)] = -1,
2003 static __initconst const u64 glp_hw_cache_extra_regs
2004 [PERF_COUNT_HW_CACHE_MAX]
2005 [PERF_COUNT_HW_CACHE_OP_MAX]
2006 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2009 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2011 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2015 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2017 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2020 [C(OP_PREFETCH)] = {
2021 [C(RESULT_ACCESS)] = 0x0,
2022 [C(RESULT_MISS)] = 0x0,
2027 #define TNT_LOCAL_DRAM BIT_ULL(26)
2028 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2029 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2030 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2031 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2032 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2033 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2035 static __initconst const u64 tnt_hw_cache_extra_regs
2036 [PERF_COUNT_HW_CACHE_MAX]
2037 [PERF_COUNT_HW_CACHE_OP_MAX]
2038 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2041 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2043 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2047 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2049 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2052 [C(OP_PREFETCH)] = {
2053 [C(RESULT_ACCESS)] = 0x0,
2054 [C(RESULT_MISS)] = 0x0,
2059 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2060 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2061 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2062 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2064 static struct attribute *tnt_events_attrs[] = {
2065 EVENT_PTR(td_fe_bound_tnt),
2066 EVENT_PTR(td_retiring_tnt),
2067 EVENT_PTR(td_bad_spec_tnt),
2068 EVENT_PTR(td_be_bound_tnt),
2072 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2073 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2074 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2075 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2079 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2080 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2081 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2082 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2083 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2087 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2088 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2089 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2090 #define KNL_MCDRAM_FAR BIT_ULL(22)
2091 #define KNL_DDR_LOCAL BIT_ULL(23)
2092 #define KNL_DDR_FAR BIT_ULL(24)
2093 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2094 KNL_DDR_LOCAL | KNL_DDR_FAR)
2095 #define KNL_L2_READ SLM_DMND_READ
2096 #define KNL_L2_WRITE SLM_DMND_WRITE
2097 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2098 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2099 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2100 KNL_DRAM_ANY | SNB_SNP_ANY | \
2103 static __initconst const u64 knl_hw_cache_extra_regs
2104 [PERF_COUNT_HW_CACHE_MAX]
2105 [PERF_COUNT_HW_CACHE_OP_MAX]
2106 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2109 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2110 [C(RESULT_MISS)] = 0,
2113 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2114 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2116 [C(OP_PREFETCH)] = {
2117 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2118 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2124 * Used from PMIs where the LBRs are already disabled.
2126 * This function could be called consecutively. It is required to remain in
2127 * disabled state if called consecutively.
2129 * During consecutive calls, the same disable value will be written to related
2130 * registers, so the PMU state remains unchanged.
2132 * intel_bts events don't coexist with intel PMU's BTS events because of
2133 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2134 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2136 * Avoid PEBS_ENABLE MSR access in PMIs.
2137 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2138 * It doesn't matter if the PEBS is enabled or not.
2139 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2140 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2141 * However, there are some cases which may change PEBS status, e.g. PMI
2142 * throttle. The PEBS_ENABLE should be updated where the status changes.
2144 static void __intel_pmu_disable_all(void)
2146 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2148 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2150 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2151 intel_pmu_disable_bts();
2154 static void intel_pmu_disable_all(void)
2156 __intel_pmu_disable_all();
2157 intel_pmu_pebs_disable_all();
2158 intel_pmu_lbr_disable_all();
2161 static void __intel_pmu_enable_all(int added, bool pmi)
2163 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2164 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2166 intel_pmu_lbr_enable_all(pmi);
2167 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2168 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2170 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2171 struct perf_event *event =
2172 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2174 if (WARN_ON_ONCE(!event))
2177 intel_pmu_enable_bts(event->hw.config);
2181 static void intel_pmu_enable_all(int added)
2183 intel_pmu_pebs_enable_all();
2184 __intel_pmu_enable_all(added, false);
2189 * Intel Errata AAK100 (model 26)
2190 * Intel Errata AAP53 (model 30)
2191 * Intel Errata BD53 (model 44)
2193 * The official story:
2194 * These chips need to be 'reset' when adding counters by programming the
2195 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2196 * in sequence on the same PMC or on different PMCs.
2198 * In practice it appears some of these events do in fact count, and
2199 * we need to program all 4 events.
2201 static void intel_pmu_nhm_workaround(void)
2203 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2204 static const unsigned long nhm_magic[4] = {
2210 struct perf_event *event;
2214 * The Errata requires below steps:
2215 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2216 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2217 * the corresponding PMCx;
2218 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2219 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2220 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2224 * The real steps we choose are a little different from above.
2225 * A) To reduce MSR operations, we don't run step 1) as they
2226 * are already cleared before this function is called;
2227 * B) Call x86_perf_event_update to save PMCx before configuring
2228 * PERFEVTSELx with magic number;
2229 * C) With step 5), we do clear only when the PERFEVTSELx is
2230 * not used currently.
2231 * D) Call x86_perf_event_set_period to restore PMCx;
2234 /* We always operate 4 pairs of PERF Counters */
2235 for (i = 0; i < 4; i++) {
2236 event = cpuc->events[i];
2238 x86_perf_event_update(event);
2241 for (i = 0; i < 4; i++) {
2242 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2243 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2246 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2247 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2249 for (i = 0; i < 4; i++) {
2250 event = cpuc->events[i];
2253 x86_perf_event_set_period(event);
2254 __x86_pmu_enable_event(&event->hw,
2255 ARCH_PERFMON_EVENTSEL_ENABLE);
2257 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2261 static void intel_pmu_nhm_enable_all(int added)
2264 intel_pmu_nhm_workaround();
2265 intel_pmu_enable_all(added);
2268 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2270 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2272 if (cpuc->tfa_shadow != val) {
2273 cpuc->tfa_shadow = val;
2274 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2278 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2281 * We're going to use PMC3, make sure TFA is set before we touch it.
2284 intel_set_tfa(cpuc, true);
2287 static void intel_tfa_pmu_enable_all(int added)
2289 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2292 * If we find PMC3 is no longer used when we enable the PMU, we can
2295 if (!test_bit(3, cpuc->active_mask))
2296 intel_set_tfa(cpuc, false);
2298 intel_pmu_enable_all(added);
2301 static inline u64 intel_pmu_get_status(void)
2305 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2310 static inline void intel_pmu_ack_status(u64 ack)
2312 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2315 static inline bool event_is_checkpointed(struct perf_event *event)
2317 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2320 static inline void intel_set_masks(struct perf_event *event, int idx)
2322 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2324 if (event->attr.exclude_host)
2325 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2326 if (event->attr.exclude_guest)
2327 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2328 if (event_is_checkpointed(event))
2329 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2332 static inline void intel_clear_masks(struct perf_event *event, int idx)
2334 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2336 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2337 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2338 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2341 static void intel_pmu_disable_fixed(struct perf_event *event)
2343 struct hw_perf_event *hwc = &event->hw;
2347 if (is_topdown_idx(idx)) {
2348 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2351 * When there are other active TopDown events,
2352 * don't disable the fixed counter 3.
2354 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2356 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2359 intel_clear_masks(event, idx);
2361 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2362 rdmsrl(hwc->config_base, ctrl_val);
2364 wrmsrl(hwc->config_base, ctrl_val);
2367 static void intel_pmu_disable_event(struct perf_event *event)
2369 struct hw_perf_event *hwc = &event->hw;
2373 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2374 intel_clear_masks(event, idx);
2375 x86_pmu_disable_event(event);
2377 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2378 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2379 intel_pmu_disable_fixed(event);
2381 case INTEL_PMC_IDX_FIXED_BTS:
2382 intel_pmu_disable_bts();
2383 intel_pmu_drain_bts_buffer();
2385 case INTEL_PMC_IDX_FIXED_VLBR:
2386 intel_clear_masks(event, idx);
2389 intel_clear_masks(event, idx);
2390 pr_warn("Failed to disable the event with invalid index %d\n",
2396 * Needs to be called after x86_pmu_disable_event,
2397 * so we don't trigger the event without PEBS bit set.
2399 if (unlikely(event->attr.precise_ip))
2400 intel_pmu_pebs_disable(event);
2403 static void intel_pmu_del_event(struct perf_event *event)
2405 if (needs_branch_stack(event))
2406 intel_pmu_lbr_del(event);
2407 if (event->attr.precise_ip)
2408 intel_pmu_pebs_del(event);
2411 static int icl_set_topdown_event_period(struct perf_event *event)
2413 struct hw_perf_event *hwc = &event->hw;
2414 s64 left = local64_read(&hwc->period_left);
2417 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2418 * Software should start both registers, PERF_METRICS and fixed
2419 * counter 3, from zero.
2420 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2421 * After that, both MSRs will be cleared for each read.
2422 * Don't need to clear them again.
2424 if (left == x86_pmu.max_period) {
2425 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2426 wrmsrl(MSR_PERF_METRICS, 0);
2427 hwc->saved_slots = 0;
2428 hwc->saved_metric = 0;
2431 if ((hwc->saved_slots) && is_slots_event(event)) {
2432 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2433 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2436 perf_event_update_userpage(event);
2441 static int adl_set_topdown_event_period(struct perf_event *event)
2443 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2445 if (pmu->cpu_type != hybrid_big)
2448 return icl_set_topdown_event_period(event);
2451 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2456 * The metric is reported as an 8bit integer fraction
2457 * summing up to 0xff.
2458 * slots-in-metric = (Metric / 0xff) * slots
2460 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2461 return mul_u64_u32_div(slots, val, 0xff);
2464 static u64 icl_get_topdown_value(struct perf_event *event,
2465 u64 slots, u64 metrics)
2467 int idx = event->hw.idx;
2470 if (is_metric_idx(idx))
2471 delta = icl_get_metrics_event_value(metrics, slots, idx);
2478 static void __icl_update_topdown_event(struct perf_event *event,
2479 u64 slots, u64 metrics,
2480 u64 last_slots, u64 last_metrics)
2482 u64 delta, last = 0;
2484 delta = icl_get_topdown_value(event, slots, metrics);
2486 last = icl_get_topdown_value(event, last_slots, last_metrics);
2489 * The 8bit integer fraction of metric may be not accurate,
2490 * especially when the changes is very small.
2491 * For example, if only a few bad_spec happens, the fraction
2492 * may be reduced from 1 to 0. If so, the bad_spec event value
2493 * will be 0 which is definitely less than the last value.
2494 * Avoid update event->count for this case.
2498 local64_add(delta, &event->count);
2502 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2503 u64 metrics, int metric_end)
2505 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2506 struct perf_event *other;
2509 event->hw.saved_slots = slots;
2510 event->hw.saved_metric = metrics;
2512 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2513 if (!is_topdown_idx(idx))
2515 other = cpuc->events[idx];
2516 other->hw.saved_slots = slots;
2517 other->hw.saved_metric = metrics;
2522 * Update all active Topdown events.
2524 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2525 * modify by a NMI. PMU has to be disabled before calling this function.
2528 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2530 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2531 struct perf_event *other;
2536 /* read Fixed counter 3 */
2537 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2541 /* read PERF_METRICS */
2542 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2544 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2545 if (!is_topdown_idx(idx))
2547 other = cpuc->events[idx];
2548 __icl_update_topdown_event(other, slots, metrics,
2549 event ? event->hw.saved_slots : 0,
2550 event ? event->hw.saved_metric : 0);
2554 * Check and update this event, which may have been cleared
2555 * in active_mask e.g. x86_pmu_stop()
2557 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2558 __icl_update_topdown_event(event, slots, metrics,
2559 event->hw.saved_slots,
2560 event->hw.saved_metric);
2563 * In x86_pmu_stop(), the event is cleared in active_mask first,
2564 * then drain the delta, which indicates context switch for
2566 * Save metric and slots for context switch.
2567 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2568 * Because the values will be restored in next schedule in.
2570 update_saved_topdown_regs(event, slots, metrics, metric_end);
2575 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2576 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2577 wrmsrl(MSR_PERF_METRICS, 0);
2579 update_saved_topdown_regs(event, 0, 0, metric_end);
2585 static u64 icl_update_topdown_event(struct perf_event *event)
2587 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2588 x86_pmu.num_topdown_events - 1);
2591 static u64 adl_update_topdown_event(struct perf_event *event)
2593 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2595 if (pmu->cpu_type != hybrid_big)
2598 return icl_update_topdown_event(event);
2602 static void intel_pmu_read_topdown_event(struct perf_event *event)
2604 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2606 /* Only need to call update_topdown_event() once for group read. */
2607 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2608 !is_slots_event(event))
2611 perf_pmu_disable(event->pmu);
2612 x86_pmu.update_topdown_event(event);
2613 perf_pmu_enable(event->pmu);
2616 static void intel_pmu_read_event(struct perf_event *event)
2618 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2619 intel_pmu_auto_reload_read(event);
2620 else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2621 intel_pmu_read_topdown_event(event);
2623 x86_perf_event_update(event);
2626 static void intel_pmu_enable_fixed(struct perf_event *event)
2628 struct hw_perf_event *hwc = &event->hw;
2629 u64 ctrl_val, mask, bits = 0;
2632 if (is_topdown_idx(idx)) {
2633 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2635 * When there are other active TopDown events,
2636 * don't enable the fixed counter 3 again.
2638 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2641 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2644 intel_set_masks(event, idx);
2647 * Enable IRQ generation (0x8), if not PEBS,
2648 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2651 if (!event->attr.precise_ip)
2653 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2655 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2659 * ANY bit is supported in v3 and up
2661 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2664 idx -= INTEL_PMC_IDX_FIXED;
2666 mask = 0xfULL << (idx * 4);
2668 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2669 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2670 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2673 rdmsrl(hwc->config_base, ctrl_val);
2676 wrmsrl(hwc->config_base, ctrl_val);
2679 static void intel_pmu_enable_event(struct perf_event *event)
2681 struct hw_perf_event *hwc = &event->hw;
2684 if (unlikely(event->attr.precise_ip))
2685 intel_pmu_pebs_enable(event);
2688 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2689 intel_set_masks(event, idx);
2690 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2692 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2693 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2694 intel_pmu_enable_fixed(event);
2696 case INTEL_PMC_IDX_FIXED_BTS:
2697 if (!__this_cpu_read(cpu_hw_events.enabled))
2699 intel_pmu_enable_bts(hwc->config);
2701 case INTEL_PMC_IDX_FIXED_VLBR:
2702 intel_set_masks(event, idx);
2705 pr_warn("Failed to enable the event with invalid index %d\n",
2710 static void intel_pmu_add_event(struct perf_event *event)
2712 if (event->attr.precise_ip)
2713 intel_pmu_pebs_add(event);
2714 if (needs_branch_stack(event))
2715 intel_pmu_lbr_add(event);
2719 * Save and restart an expired event. Called by NMI contexts,
2720 * so it has to be careful about preempting normal event ops:
2722 int intel_pmu_save_and_restart(struct perf_event *event)
2724 x86_perf_event_update(event);
2726 * For a checkpointed counter always reset back to 0. This
2727 * avoids a situation where the counter overflows, aborts the
2728 * transaction and is then set back to shortly before the
2729 * overflow, and overflows and aborts again.
2731 if (unlikely(event_is_checkpointed(event))) {
2732 /* No race with NMIs because the counter should not be armed */
2733 wrmsrl(event->hw.event_base, 0);
2734 local64_set(&event->hw.prev_count, 0);
2736 return x86_perf_event_set_period(event);
2739 static void intel_pmu_reset(void)
2741 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2742 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2743 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2744 int num_counters = hybrid(cpuc->pmu, num_counters);
2745 unsigned long flags;
2751 local_irq_save(flags);
2753 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2755 for (idx = 0; idx < num_counters; idx++) {
2756 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2757 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2759 for (idx = 0; idx < num_counters_fixed; idx++) {
2760 if (fixed_counter_disabled(idx, cpuc->pmu))
2762 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2766 ds->bts_index = ds->bts_buffer_base;
2768 /* Ack all overflows and disable fixed counters */
2769 if (x86_pmu.version >= 2) {
2770 intel_pmu_ack_status(intel_pmu_get_status());
2771 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2774 /* Reset LBRs and LBR freezing */
2775 if (x86_pmu.lbr_nr) {
2776 update_debugctlmsr(get_debugctlmsr() &
2777 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2780 local_irq_restore(flags);
2783 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2785 struct perf_sample_data data;
2786 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2789 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2791 inc_irq_stat(apic_perf_irqs);
2794 * Ignore a range of extra bits in status that do not indicate
2795 * overflow by themselves.
2797 status &= ~(GLOBAL_STATUS_COND_CHG |
2798 GLOBAL_STATUS_ASIF |
2799 GLOBAL_STATUS_LBRS_FROZEN);
2803 * In case multiple PEBS events are sampled at the same time,
2804 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2805 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2806 * having their bits set in the status register. This is a sign
2807 * that there was at least one PEBS record pending at the time
2808 * of the PMU interrupt. PEBS counters must only be processed
2809 * via the drain_pebs() calls and not via the regular sample
2810 * processing loop coming after that the function, otherwise
2811 * phony regular samples may be generated in the sampling buffer
2812 * not marked with the EXACT tag. Another possibility is to have
2813 * one PEBS event and at least one non-PEBS event which overflows
2814 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2815 * not be set, yet the overflow status bit for the PEBS counter will
2818 * To avoid this problem, we systematically ignore the PEBS-enabled
2819 * counters from the GLOBAL_STATUS mask and we always process PEBS
2820 * events via drain_pebs().
2822 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2823 status &= ~cpuc->pebs_enabled;
2825 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2828 * PEBS overflow sets bit 62 in the global status register
2830 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2831 u64 pebs_enabled = cpuc->pebs_enabled;
2834 x86_pmu.drain_pebs(regs, &data);
2835 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2838 * PMI throttle may be triggered, which stops the PEBS event.
2839 * Although cpuc->pebs_enabled is updated accordingly, the
2840 * MSR_IA32_PEBS_ENABLE is not updated. Because the
2841 * cpuc->enabled has been forced to 0 in PMI.
2842 * Update the MSR if pebs_enabled is changed.
2844 if (pebs_enabled != cpuc->pebs_enabled)
2845 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2851 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2853 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2854 perf_guest_cbs->handle_intel_pt_intr))
2855 perf_guest_cbs->handle_intel_pt_intr();
2857 intel_pt_interrupt();
2861 * Intel Perf metrics
2863 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2865 if (x86_pmu.update_topdown_event)
2866 x86_pmu.update_topdown_event(NULL);
2870 * Checkpointed counters can lead to 'spurious' PMIs because the
2871 * rollback caused by the PMI will have cleared the overflow status
2872 * bit. Therefore always force probe these counters.
2874 status |= cpuc->intel_cp_status;
2876 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2877 struct perf_event *event = cpuc->events[bit];
2881 if (!test_bit(bit, cpuc->active_mask))
2884 if (!intel_pmu_save_and_restart(event))
2887 perf_sample_data_init(&data, 0, event->hw.last_period);
2889 if (has_branch_stack(event))
2890 data.br_stack = &cpuc->lbr_stack;
2892 if (perf_event_overflow(event, &data, regs))
2893 x86_pmu_stop(event, 0);
2900 * This handler is triggered by the local APIC, so the APIC IRQ handling
2903 static int intel_pmu_handle_irq(struct pt_regs *regs)
2905 struct cpu_hw_events *cpuc;
2911 cpuc = this_cpu_ptr(&cpu_hw_events);
2914 * Save the PMU state.
2915 * It needs to be restored when leaving the handler.
2917 pmu_enabled = cpuc->enabled;
2919 * No known reason to not always do late ACK,
2920 * but just in case do it opt-in.
2922 if (!x86_pmu.late_ack)
2923 apic_write(APIC_LVTPC, APIC_DM_NMI);
2924 intel_bts_disable_local();
2926 __intel_pmu_disable_all();
2927 handled = intel_pmu_drain_bts_buffer();
2928 handled += intel_bts_interrupt();
2929 status = intel_pmu_get_status();
2935 intel_pmu_lbr_read();
2936 intel_pmu_ack_status(status);
2937 if (++loops > 100) {
2941 WARN(1, "perfevents: irq loop stuck!\n");
2942 perf_event_print_debug();
2949 handled += handle_pmi_common(regs, status);
2952 * Repeat if there is more work to be done:
2954 status = intel_pmu_get_status();
2959 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2960 cpuc->enabled = pmu_enabled;
2962 __intel_pmu_enable_all(0, true);
2963 intel_bts_enable_local();
2966 * Only unmask the NMI after the overflow counters
2967 * have been reset. This avoids spurious NMIs on
2970 if (x86_pmu.late_ack)
2971 apic_write(APIC_LVTPC, APIC_DM_NMI);
2975 static struct event_constraint *
2976 intel_bts_constraints(struct perf_event *event)
2978 if (unlikely(intel_pmu_has_bts(event)))
2979 return &bts_constraint;
2985 * Note: matches a fake event, like Fixed2.
2987 static struct event_constraint *
2988 intel_vlbr_constraints(struct perf_event *event)
2990 struct event_constraint *c = &vlbr_constraint;
2992 if (unlikely(constraint_match(c, event->hw.config)))
2998 static int intel_alt_er(struct cpu_hw_events *cpuc,
2999 int idx, u64 config)
3001 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3004 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3007 if (idx == EXTRA_REG_RSP_0)
3008 alt_idx = EXTRA_REG_RSP_1;
3010 if (idx == EXTRA_REG_RSP_1)
3011 alt_idx = EXTRA_REG_RSP_0;
3013 if (config & ~extra_regs[alt_idx].valid_mask)
3019 static void intel_fixup_er(struct perf_event *event, int idx)
3021 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3022 event->hw.extra_reg.idx = idx;
3024 if (idx == EXTRA_REG_RSP_0) {
3025 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3026 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3027 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3028 } else if (idx == EXTRA_REG_RSP_1) {
3029 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3030 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3031 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3036 * manage allocation of shared extra msr for certain events
3039 * per-cpu: to be shared between the various events on a single PMU
3040 * per-core: per-cpu + shared by HT threads
3042 static struct event_constraint *
3043 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3044 struct perf_event *event,
3045 struct hw_perf_event_extra *reg)
3047 struct event_constraint *c = &emptyconstraint;
3048 struct er_account *era;
3049 unsigned long flags;
3053 * reg->alloc can be set due to existing state, so for fake cpuc we
3054 * need to ignore this, otherwise we might fail to allocate proper fake
3055 * state for this extra reg constraint. Also see the comment below.
3057 if (reg->alloc && !cpuc->is_fake)
3058 return NULL; /* call x86_get_event_constraint() */
3061 era = &cpuc->shared_regs->regs[idx];
3063 * we use spin_lock_irqsave() to avoid lockdep issues when
3064 * passing a fake cpuc
3066 raw_spin_lock_irqsave(&era->lock, flags);
3068 if (!atomic_read(&era->ref) || era->config == reg->config) {
3071 * If its a fake cpuc -- as per validate_{group,event}() we
3072 * shouldn't touch event state and we can avoid doing so
3073 * since both will only call get_event_constraints() once
3074 * on each event, this avoids the need for reg->alloc.
3076 * Not doing the ER fixup will only result in era->reg being
3077 * wrong, but since we won't actually try and program hardware
3078 * this isn't a problem either.
3080 if (!cpuc->is_fake) {
3081 if (idx != reg->idx)
3082 intel_fixup_er(event, idx);
3085 * x86_schedule_events() can call get_event_constraints()
3086 * multiple times on events in the case of incremental
3087 * scheduling(). reg->alloc ensures we only do the ER
3093 /* lock in msr value */
3094 era->config = reg->config;
3095 era->reg = reg->reg;
3098 atomic_inc(&era->ref);
3101 * need to call x86_get_event_constraint()
3102 * to check if associated event has constraints
3106 idx = intel_alt_er(cpuc, idx, reg->config);
3107 if (idx != reg->idx) {
3108 raw_spin_unlock_irqrestore(&era->lock, flags);
3112 raw_spin_unlock_irqrestore(&era->lock, flags);
3118 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3119 struct hw_perf_event_extra *reg)
3121 struct er_account *era;
3124 * Only put constraint if extra reg was actually allocated. Also takes
3125 * care of event which do not use an extra shared reg.
3127 * Also, if this is a fake cpuc we shouldn't touch any event state
3128 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3129 * either since it'll be thrown out.
3131 if (!reg->alloc || cpuc->is_fake)
3134 era = &cpuc->shared_regs->regs[reg->idx];
3136 /* one fewer user */
3137 atomic_dec(&era->ref);
3139 /* allocate again next time */
3143 static struct event_constraint *
3144 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3145 struct perf_event *event)
3147 struct event_constraint *c = NULL, *d;
3148 struct hw_perf_event_extra *xreg, *breg;
3150 xreg = &event->hw.extra_reg;
3151 if (xreg->idx != EXTRA_REG_NONE) {
3152 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3153 if (c == &emptyconstraint)
3156 breg = &event->hw.branch_reg;
3157 if (breg->idx != EXTRA_REG_NONE) {
3158 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3159 if (d == &emptyconstraint) {
3160 __intel_shared_reg_put_constraints(cpuc, xreg);
3167 struct event_constraint *
3168 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3169 struct perf_event *event)
3171 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3172 struct event_constraint *c;
3174 if (event_constraints) {
3175 for_each_event_constraint(c, event_constraints) {
3176 if (constraint_match(c, event->hw.config)) {
3177 event->hw.flags |= c->flags;
3183 return &hybrid_var(cpuc->pmu, unconstrained);
3186 static struct event_constraint *
3187 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3188 struct perf_event *event)
3190 struct event_constraint *c;
3192 c = intel_vlbr_constraints(event);
3196 c = intel_bts_constraints(event);
3200 c = intel_shared_regs_constraints(cpuc, event);
3204 c = intel_pebs_constraints(event);
3208 return x86_get_event_constraints(cpuc, idx, event);
3212 intel_start_scheduling(struct cpu_hw_events *cpuc)
3214 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3215 struct intel_excl_states *xl;
3216 int tid = cpuc->excl_thread_id;
3219 * nothing needed if in group validation mode
3221 if (cpuc->is_fake || !is_ht_workaround_enabled())
3225 * no exclusion needed
3227 if (WARN_ON_ONCE(!excl_cntrs))
3230 xl = &excl_cntrs->states[tid];
3232 xl->sched_started = true;
3234 * lock shared state until we are done scheduling
3235 * in stop_event_scheduling()
3236 * makes scheduling appear as a transaction
3238 raw_spin_lock(&excl_cntrs->lock);
3241 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3243 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3244 struct event_constraint *c = cpuc->event_constraint[idx];
3245 struct intel_excl_states *xl;
3246 int tid = cpuc->excl_thread_id;
3248 if (cpuc->is_fake || !is_ht_workaround_enabled())
3251 if (WARN_ON_ONCE(!excl_cntrs))
3254 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3257 xl = &excl_cntrs->states[tid];
3259 lockdep_assert_held(&excl_cntrs->lock);
3261 if (c->flags & PERF_X86_EVENT_EXCL)
3262 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3264 xl->state[cntr] = INTEL_EXCL_SHARED;
3268 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3270 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3271 struct intel_excl_states *xl;
3272 int tid = cpuc->excl_thread_id;
3275 * nothing needed if in group validation mode
3277 if (cpuc->is_fake || !is_ht_workaround_enabled())
3280 * no exclusion needed
3282 if (WARN_ON_ONCE(!excl_cntrs))
3285 xl = &excl_cntrs->states[tid];
3287 xl->sched_started = false;
3289 * release shared state lock (acquired in intel_start_scheduling())
3291 raw_spin_unlock(&excl_cntrs->lock);
3294 static struct event_constraint *
3295 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3297 WARN_ON_ONCE(!cpuc->constraint_list);
3299 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3300 struct event_constraint *cx;
3303 * grab pre-allocated constraint entry
3305 cx = &cpuc->constraint_list[idx];
3308 * initialize dynamic constraint
3309 * with static constraint
3314 * mark constraint as dynamic
3316 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3323 static struct event_constraint *
3324 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3325 int idx, struct event_constraint *c)
3327 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3328 struct intel_excl_states *xlo;
3329 int tid = cpuc->excl_thread_id;
3333 * validating a group does not require
3334 * enforcing cross-thread exclusion
3336 if (cpuc->is_fake || !is_ht_workaround_enabled())
3340 * no exclusion needed
3342 if (WARN_ON_ONCE(!excl_cntrs))
3346 * because we modify the constraint, we need
3347 * to make a copy. Static constraints come
3348 * from static const tables.
3350 * only needed when constraint has not yet
3351 * been cloned (marked dynamic)
3353 c = dyn_constraint(cpuc, c, idx);
3356 * From here on, the constraint is dynamic.
3357 * Either it was just allocated above, or it
3358 * was allocated during a earlier invocation
3363 * state of sibling HT
3365 xlo = &excl_cntrs->states[tid ^ 1];
3368 * event requires exclusive counter access
3371 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3372 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3373 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3374 if (!cpuc->n_excl++)
3375 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3379 * Modify static constraint with current dynamic
3382 * EXCLUSIVE: sibling counter measuring exclusive event
3383 * SHARED : sibling counter measuring non-exclusive event
3384 * UNUSED : sibling counter unused
3387 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3389 * exclusive event in sibling counter
3390 * our corresponding counter cannot be used
3391 * regardless of our event
3393 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3394 __clear_bit(i, c->idxmsk);
3399 * if measuring an exclusive event, sibling
3400 * measuring non-exclusive, then counter cannot
3403 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3404 __clear_bit(i, c->idxmsk);
3411 * if we return an empty mask, then switch
3412 * back to static empty constraint to avoid
3413 * the cost of freeing later on
3416 c = &emptyconstraint;
3423 static struct event_constraint *
3424 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3425 struct perf_event *event)
3427 struct event_constraint *c1, *c2;
3429 c1 = cpuc->event_constraint[idx];
3433 * - static constraint: no change across incremental scheduling calls
3434 * - dynamic constraint: handled by intel_get_excl_constraints()
3436 c2 = __intel_get_event_constraints(cpuc, idx, event);
3438 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3439 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3440 c1->weight = c2->weight;
3444 if (cpuc->excl_cntrs)
3445 return intel_get_excl_constraints(cpuc, event, idx, c2);
3450 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3451 struct perf_event *event)
3453 struct hw_perf_event *hwc = &event->hw;
3454 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3455 int tid = cpuc->excl_thread_id;
3456 struct intel_excl_states *xl;
3459 * nothing needed if in group validation mode
3464 if (WARN_ON_ONCE(!excl_cntrs))
3467 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3468 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3469 if (!--cpuc->n_excl)
3470 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3474 * If event was actually assigned, then mark the counter state as
3477 if (hwc->idx >= 0) {
3478 xl = &excl_cntrs->states[tid];
3481 * put_constraint may be called from x86_schedule_events()
3482 * which already has the lock held so here make locking
3485 if (!xl->sched_started)
3486 raw_spin_lock(&excl_cntrs->lock);
3488 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3490 if (!xl->sched_started)
3491 raw_spin_unlock(&excl_cntrs->lock);
3496 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3497 struct perf_event *event)
3499 struct hw_perf_event_extra *reg;
3501 reg = &event->hw.extra_reg;
3502 if (reg->idx != EXTRA_REG_NONE)
3503 __intel_shared_reg_put_constraints(cpuc, reg);
3505 reg = &event->hw.branch_reg;
3506 if (reg->idx != EXTRA_REG_NONE)
3507 __intel_shared_reg_put_constraints(cpuc, reg);
3510 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3511 struct perf_event *event)
3513 intel_put_shared_regs_event_constraints(cpuc, event);
3516 * is PMU has exclusive counter restrictions, then
3517 * all events are subject to and must call the
3518 * put_excl_constraints() routine
3520 if (cpuc->excl_cntrs)
3521 intel_put_excl_constraints(cpuc, event);
3524 static void intel_pebs_aliases_core2(struct perf_event *event)
3526 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3528 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3529 * (0x003c) so that we can use it with PEBS.
3531 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3532 * PEBS capable. However we can use INST_RETIRED.ANY_P
3533 * (0x00c0), which is a PEBS capable event, to get the same
3536 * INST_RETIRED.ANY_P counts the number of cycles that retires
3537 * CNTMASK instructions. By setting CNTMASK to a value (16)
3538 * larger than the maximum number of instructions that can be
3539 * retired per cycle (4) and then inverting the condition, we
3540 * count all cycles that retire 16 or less instructions, which
3543 * Thereby we gain a PEBS capable cycle counter.
3545 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3547 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3548 event->hw.config = alt_config;
3552 static void intel_pebs_aliases_snb(struct perf_event *event)
3554 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3556 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3557 * (0x003c) so that we can use it with PEBS.
3559 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3560 * PEBS capable. However we can use UOPS_RETIRED.ALL
3561 * (0x01c2), which is a PEBS capable event, to get the same
3564 * UOPS_RETIRED.ALL counts the number of cycles that retires
3565 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3566 * larger than the maximum number of micro-ops that can be
3567 * retired per cycle (4) and then inverting the condition, we
3568 * count all cycles that retire 16 or less micro-ops, which
3571 * Thereby we gain a PEBS capable cycle counter.
3573 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3575 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3576 event->hw.config = alt_config;
3580 static void intel_pebs_aliases_precdist(struct perf_event *event)
3582 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3584 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3585 * (0x003c) so that we can use it with PEBS.
3587 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3588 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3589 * (0x01c0), which is a PEBS capable event, to get the same
3592 * The PREC_DIST event has special support to minimize sample
3593 * shadowing effects. One drawback is that it can be
3594 * only programmed on counter 1, but that seems like an
3595 * acceptable trade off.
3597 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3599 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3600 event->hw.config = alt_config;
3604 static void intel_pebs_aliases_ivb(struct perf_event *event)
3606 if (event->attr.precise_ip < 3)
3607 return intel_pebs_aliases_snb(event);
3608 return intel_pebs_aliases_precdist(event);
3611 static void intel_pebs_aliases_skl(struct perf_event *event)
3613 if (event->attr.precise_ip < 3)
3614 return intel_pebs_aliases_core2(event);
3615 return intel_pebs_aliases_precdist(event);
3618 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3620 unsigned long flags = x86_pmu.large_pebs_flags;
3622 if (event->attr.use_clockid)
3623 flags &= ~PERF_SAMPLE_TIME;
3624 if (!event->attr.exclude_kernel)
3625 flags &= ~PERF_SAMPLE_REGS_USER;
3626 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3627 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3631 static int intel_pmu_bts_config(struct perf_event *event)
3633 struct perf_event_attr *attr = &event->attr;
3635 if (unlikely(intel_pmu_has_bts(event))) {
3636 /* BTS is not supported by this architecture. */
3637 if (!x86_pmu.bts_active)
3640 /* BTS is currently only allowed for user-mode. */
3641 if (!attr->exclude_kernel)
3644 /* BTS is not allowed for precise events. */
3645 if (attr->precise_ip)
3648 /* disallow bts if conflicting events are present */
3649 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3652 event->destroy = hw_perf_lbr_event_destroy;
3658 static int core_pmu_hw_config(struct perf_event *event)
3660 int ret = x86_pmu_hw_config(event);
3665 return intel_pmu_bts_config(event);
3668 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
3669 ((x86_pmu.num_topdown_events - 1) << 8))
3671 static bool is_available_metric_event(struct perf_event *event)
3673 return is_metric_event(event) &&
3674 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3677 static inline bool is_mem_loads_event(struct perf_event *event)
3679 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3682 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3684 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3687 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3689 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3693 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big;
3698 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3700 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3702 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3705 static int intel_pmu_hw_config(struct perf_event *event)
3707 int ret = x86_pmu_hw_config(event);
3712 ret = intel_pmu_bts_config(event);
3716 if (event->attr.precise_ip) {
3717 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3720 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3721 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3722 if (!(event->attr.sample_type &
3723 ~intel_pmu_large_pebs_flags(event))) {
3724 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3725 event->attach_state |= PERF_ATTACH_SCHED_CB;
3728 if (x86_pmu.pebs_aliases)
3729 x86_pmu.pebs_aliases(event);
3731 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3732 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3735 if (needs_branch_stack(event)) {
3736 ret = intel_pmu_setup_lbr_filter(event);
3739 event->attach_state |= PERF_ATTACH_SCHED_CB;
3742 * BTS is set up earlier in this path, so don't account twice
3744 if (!unlikely(intel_pmu_has_bts(event))) {
3745 /* disallow lbr if conflicting events are present */
3746 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3749 event->destroy = hw_perf_lbr_event_destroy;
3753 if (event->attr.aux_output) {
3754 if (!event->attr.precise_ip)
3757 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3760 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
3761 (event->attr.type == PERF_TYPE_HW_CACHE))
3765 * Config Topdown slots and metric events
3767 * The slots event on Fixed Counter 3 can support sampling,
3768 * which will be handled normally in x86_perf_event_update().
3770 * Metric events don't support sampling and require being paired
3771 * with a slots event as group leader. When the slots event
3772 * is used in a metrics group, it too cannot support sampling.
3774 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
3775 if (event->attr.config1 || event->attr.config2)
3779 * The TopDown metrics events and slots event don't
3780 * support any filters.
3782 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3785 if (is_available_metric_event(event)) {
3786 struct perf_event *leader = event->group_leader;
3788 /* The metric events don't support sampling. */
3789 if (is_sampling_event(event))
3792 /* The metric events require a slots group leader. */
3793 if (!is_slots_event(leader))
3797 * The leader/SLOTS must not be a sampling event for
3798 * metric use; hardware requires it starts at 0 when used
3799 * in conjunction with MSR_PERF_METRICS.
3801 if (is_sampling_event(leader))
3804 event->event_caps |= PERF_EV_CAP_SIBLING;
3806 * Only once we have a METRICs sibling do we
3807 * need TopDown magic.
3809 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3810 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3815 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3816 * doesn't function quite right. As a work-around it needs to always be
3817 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3818 * The actual count of this second event is irrelevant it just needs
3819 * to be active to make the first event function correctly.
3821 * In a group, the auxiliary event must be in front of the load latency
3822 * event. The rule is to simplify the implementation of the check.
3823 * That's because perf cannot have a complete group at the moment.
3825 if (require_mem_loads_aux_event(event) &&
3826 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3827 is_mem_loads_event(event)) {
3828 struct perf_event *leader = event->group_leader;
3829 struct perf_event *sibling = NULL;
3831 if (!is_mem_loads_aux_event(leader)) {
3832 for_each_sibling_event(sibling, leader) {
3833 if (is_mem_loads_aux_event(sibling))
3836 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
3841 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3844 if (x86_pmu.version < 3)
3847 ret = perf_allow_cpu(&event->attr);
3851 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3856 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3858 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3859 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3860 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
3862 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3863 arr[0].host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3864 arr[0].guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3865 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3866 arr[0].guest &= ~cpuc->pebs_enabled;
3868 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3871 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3873 * If PMU counter has PEBS enabled it is not enough to
3874 * disable counter on a guest entry since PEBS memory
3875 * write can overshoot guest entry and corrupt guest
3876 * memory. Disabling PEBS solves the problem.
3878 * Don't do this if the CPU already enforces it.
3880 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3881 arr[1].host = cpuc->pebs_enabled;
3889 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3891 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3892 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3895 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3896 struct perf_event *event = cpuc->events[idx];
3898 arr[idx].msr = x86_pmu_config_addr(idx);
3899 arr[idx].host = arr[idx].guest = 0;
3901 if (!test_bit(idx, cpuc->active_mask))
3904 arr[idx].host = arr[idx].guest =
3905 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3907 if (event->attr.exclude_host)
3908 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3909 else if (event->attr.exclude_guest)
3910 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3913 *nr = x86_pmu.num_counters;
3917 static void core_pmu_enable_event(struct perf_event *event)
3919 if (!event->attr.exclude_host)
3920 x86_pmu_enable_event(event);
3923 static void core_pmu_enable_all(int added)
3925 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3928 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3929 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3931 if (!test_bit(idx, cpuc->active_mask) ||
3932 cpuc->events[idx]->attr.exclude_host)
3935 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3939 static int hsw_hw_config(struct perf_event *event)
3941 int ret = intel_pmu_hw_config(event);
3945 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3947 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3950 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3951 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3954 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3955 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3956 event->attr.precise_ip > 0))
3959 if (event_is_checkpointed(event)) {
3961 * Sampling of checkpointed events can cause situations where
3962 * the CPU constantly aborts because of a overflow, which is
3963 * then checkpointed back and ignored. Forbid checkpointing
3966 * But still allow a long sampling period, so that perf stat
3969 if (event->attr.sample_period > 0 &&
3970 event->attr.sample_period < 0x7fffffff)
3976 static struct event_constraint counter0_constraint =
3977 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3979 static struct event_constraint counter2_constraint =
3980 EVENT_CONSTRAINT(0, 0x4, 0);
3982 static struct event_constraint fixed0_constraint =
3983 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3985 static struct event_constraint fixed0_counter0_constraint =
3986 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3988 static struct event_constraint *
3989 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3990 struct perf_event *event)
3992 struct event_constraint *c;
3994 c = intel_get_event_constraints(cpuc, idx, event);
3996 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3997 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3998 if (c->idxmsk64 & (1U << 2))
3999 return &counter2_constraint;
4000 return &emptyconstraint;
4006 static struct event_constraint *
4007 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4008 struct perf_event *event)
4011 * Fixed counter 0 has less skid.
4012 * Force instruction:ppp in Fixed counter 0
4014 if ((event->attr.precise_ip == 3) &&
4015 constraint_match(&fixed0_constraint, event->hw.config))
4016 return &fixed0_constraint;
4018 return hsw_get_event_constraints(cpuc, idx, event);
4021 static struct event_constraint *
4022 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4023 struct perf_event *event)
4025 struct event_constraint *c;
4027 c = icl_get_event_constraints(cpuc, idx, event);
4030 * The :ppp indicates the Precise Distribution (PDist) facility, which
4031 * is only supported on the GP counter 0. If a :ppp event which is not
4032 * available on the GP counter 0, error out.
4034 if (event->attr.precise_ip == 3) {
4035 if (c->idxmsk64 & BIT_ULL(0))
4036 return &counter0_constraint;
4038 return &emptyconstraint;
4044 static struct event_constraint *
4045 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4046 struct perf_event *event)
4048 struct event_constraint *c;
4050 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4051 if (event->attr.precise_ip == 3)
4052 return &counter0_constraint;
4054 c = intel_get_event_constraints(cpuc, idx, event);
4059 static struct event_constraint *
4060 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4061 struct perf_event *event)
4063 struct event_constraint *c;
4066 * :ppp means to do reduced skid PEBS,
4067 * which is available on PMC0 and fixed counter 0.
4069 if (event->attr.precise_ip == 3) {
4070 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4071 if (constraint_match(&fixed0_constraint, event->hw.config))
4072 return &fixed0_counter0_constraint;
4074 return &counter0_constraint;
4077 c = intel_get_event_constraints(cpuc, idx, event);
4082 static bool allow_tsx_force_abort = true;
4084 static struct event_constraint *
4085 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4086 struct perf_event *event)
4088 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4091 * Without TFA we must not use PMC3.
4093 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4094 c = dyn_constraint(cpuc, c, idx);
4095 c->idxmsk64 &= ~(1ULL << 3);
4102 static struct event_constraint *
4103 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4104 struct perf_event *event)
4106 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4108 if (pmu->cpu_type == hybrid_big)
4109 return spr_get_event_constraints(cpuc, idx, event);
4110 else if (pmu->cpu_type == hybrid_small)
4111 return tnt_get_event_constraints(cpuc, idx, event);
4114 return &emptyconstraint;
4117 static int adl_hw_config(struct perf_event *event)
4119 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4121 if (pmu->cpu_type == hybrid_big)
4122 return hsw_hw_config(event);
4123 else if (pmu->cpu_type == hybrid_small)
4124 return intel_pmu_hw_config(event);
4130 static u8 adl_get_hybrid_cpu_type(void)
4138 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4139 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4140 * the two to enforce a minimum period of 128 (the smallest value that has bits
4141 * 0-5 cleared and >= 100).
4143 * Because of how the code in x86_perf_event_set_period() works, the truncation
4144 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4145 * to make up for the 'lost' events due to carrying the 'error' in period_left.
4147 * Therefore the effective (average) period matches the requested period,
4148 * despite coarser hardware granularity.
4150 static u64 bdw_limit_period(struct perf_event *event, u64 left)
4152 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4153 X86_CONFIG(.event=0xc0, .umask=0x01)) {
4161 static u64 nhm_limit_period(struct perf_event *event, u64 left)
4163 return max(left, 32ULL);
4166 static u64 spr_limit_period(struct perf_event *event, u64 left)
4168 if (event->attr.precise_ip == 3)
4169 return max(left, 128ULL);
4174 PMU_FORMAT_ATTR(event, "config:0-7" );
4175 PMU_FORMAT_ATTR(umask, "config:8-15" );
4176 PMU_FORMAT_ATTR(edge, "config:18" );
4177 PMU_FORMAT_ATTR(pc, "config:19" );
4178 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
4179 PMU_FORMAT_ATTR(inv, "config:23" );
4180 PMU_FORMAT_ATTR(cmask, "config:24-31" );
4181 PMU_FORMAT_ATTR(in_tx, "config:32");
4182 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4184 static struct attribute *intel_arch_formats_attr[] = {
4185 &format_attr_event.attr,
4186 &format_attr_umask.attr,
4187 &format_attr_edge.attr,
4188 &format_attr_pc.attr,
4189 &format_attr_inv.attr,
4190 &format_attr_cmask.attr,
4194 ssize_t intel_event_sysfs_show(char *page, u64 config)
4196 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4198 return x86_event_sysfs_show(page, config, event);
4201 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4203 struct intel_shared_regs *regs;
4206 regs = kzalloc_node(sizeof(struct intel_shared_regs),
4207 GFP_KERNEL, cpu_to_node(cpu));
4210 * initialize the locks to keep lockdep happy
4212 for (i = 0; i < EXTRA_REG_MAX; i++)
4213 raw_spin_lock_init(®s->regs[i].lock);
4220 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4222 struct intel_excl_cntrs *c;
4224 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4225 GFP_KERNEL, cpu_to_node(cpu));
4227 raw_spin_lock_init(&c->lock);
4234 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4236 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4238 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4239 cpuc->shared_regs = allocate_shared_regs(cpu);
4240 if (!cpuc->shared_regs)
4244 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4245 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4247 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4248 if (!cpuc->constraint_list)
4249 goto err_shared_regs;
4252 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4253 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4254 if (!cpuc->excl_cntrs)
4255 goto err_constraint_list;
4257 cpuc->excl_thread_id = 0;
4262 err_constraint_list:
4263 kfree(cpuc->constraint_list);
4264 cpuc->constraint_list = NULL;
4267 kfree(cpuc->shared_regs);
4268 cpuc->shared_regs = NULL;
4274 static int intel_pmu_cpu_prepare(int cpu)
4276 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4279 static void flip_smm_bit(void *data)
4281 unsigned long set = *(unsigned long *)data;
4284 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4285 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4287 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4288 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4292 static bool init_hybrid_pmu(int cpu)
4294 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4295 u8 cpu_type = get_this_hybrid_cpu_type();
4296 struct x86_hybrid_pmu *pmu = NULL;
4299 if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
4300 cpu_type = x86_pmu.get_hybrid_cpu_type();
4302 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
4303 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) {
4304 pmu = &x86_pmu.hybrid_pmu[i];
4308 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
4313 /* Only check and dump the PMU information for the first CPU */
4314 if (!cpumask_empty(&pmu->supported_cpus))
4317 if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed))
4320 pr_info("%s PMU driver: ", pmu->name);
4322 if (pmu->intel_cap.pebs_output_pt_available)
4323 pr_cont("PEBS-via-PT ");
4327 x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed,
4331 cpumask_set_cpu(cpu, &pmu->supported_cpus);
4332 cpuc->pmu = &pmu->pmu;
4334 x86_pmu_update_cpu_context(&pmu->pmu, cpu);
4339 static void intel_pmu_cpu_starting(int cpu)
4341 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4342 int core_id = topology_core_id(cpu);
4345 if (is_hybrid() && !init_hybrid_pmu(cpu))
4348 init_debug_store_on_cpu(cpu);
4350 * Deal with CPUs that don't clear their LBRs on power-up.
4352 intel_pmu_lbr_reset();
4354 cpuc->lbr_sel = NULL;
4356 if (x86_pmu.flags & PMU_FL_TFA) {
4357 WARN_ON_ONCE(cpuc->tfa_shadow);
4358 cpuc->tfa_shadow = ~0ULL;
4359 intel_set_tfa(cpuc, false);
4362 if (x86_pmu.version > 1)
4363 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4366 * Disable perf metrics if any added CPU doesn't support it.
4368 * Turn off the check for a hybrid architecture, because the
4369 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
4370 * the architecture features. The perf metrics is a model-specific
4371 * feature for now. The corresponding bit should always be 0 on
4372 * a hybrid platform, e.g., Alder Lake.
4374 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
4375 union perf_capabilities perf_cap;
4377 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4378 if (!perf_cap.perf_metrics) {
4379 x86_pmu.intel_cap.perf_metrics = 0;
4380 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4384 if (!cpuc->shared_regs)
4387 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4388 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4389 struct intel_shared_regs *pc;
4391 pc = per_cpu(cpu_hw_events, i).shared_regs;
4392 if (pc && pc->core_id == core_id) {
4393 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4394 cpuc->shared_regs = pc;
4398 cpuc->shared_regs->core_id = core_id;
4399 cpuc->shared_regs->refcnt++;
4402 if (x86_pmu.lbr_sel_map)
4403 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4405 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4406 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4407 struct cpu_hw_events *sibling;
4408 struct intel_excl_cntrs *c;
4410 sibling = &per_cpu(cpu_hw_events, i);
4411 c = sibling->excl_cntrs;
4412 if (c && c->core_id == core_id) {
4413 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4414 cpuc->excl_cntrs = c;
4415 if (!sibling->excl_thread_id)
4416 cpuc->excl_thread_id = 1;
4420 cpuc->excl_cntrs->core_id = core_id;
4421 cpuc->excl_cntrs->refcnt++;
4425 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4427 struct intel_excl_cntrs *c;
4429 c = cpuc->excl_cntrs;
4431 if (c->core_id == -1 || --c->refcnt == 0)
4433 cpuc->excl_cntrs = NULL;
4436 kfree(cpuc->constraint_list);
4437 cpuc->constraint_list = NULL;
4440 static void intel_pmu_cpu_dying(int cpu)
4442 fini_debug_store_on_cpu(cpu);
4445 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4447 struct intel_shared_regs *pc;
4449 pc = cpuc->shared_regs;
4451 if (pc->core_id == -1 || --pc->refcnt == 0)
4453 cpuc->shared_regs = NULL;
4456 free_excl_cntrs(cpuc);
4459 static void intel_pmu_cpu_dead(int cpu)
4461 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4463 intel_cpuc_finish(cpuc);
4465 if (is_hybrid() && cpuc->pmu)
4466 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
4469 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4472 intel_pmu_pebs_sched_task(ctx, sched_in);
4473 intel_pmu_lbr_sched_task(ctx, sched_in);
4476 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4477 struct perf_event_context *next)
4479 intel_pmu_lbr_swap_task_ctx(prev, next);
4482 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4484 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4487 static int intel_pmu_aux_output_match(struct perf_event *event)
4489 if (!x86_pmu.intel_cap.pebs_output_pt_available)
4492 return is_intel_pt_event(event);
4495 static int intel_pmu_filter_match(struct perf_event *event)
4497 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4498 unsigned int cpu = smp_processor_id();
4500 return cpumask_test_cpu(cpu, &pmu->supported_cpus);
4503 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4505 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4507 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4509 static struct attribute *intel_arch3_formats_attr[] = {
4510 &format_attr_event.attr,
4511 &format_attr_umask.attr,
4512 &format_attr_edge.attr,
4513 &format_attr_pc.attr,
4514 &format_attr_any.attr,
4515 &format_attr_inv.attr,
4516 &format_attr_cmask.attr,
4520 static struct attribute *hsw_format_attr[] = {
4521 &format_attr_in_tx.attr,
4522 &format_attr_in_tx_cp.attr,
4523 &format_attr_offcore_rsp.attr,
4524 &format_attr_ldlat.attr,
4528 static struct attribute *nhm_format_attr[] = {
4529 &format_attr_offcore_rsp.attr,
4530 &format_attr_ldlat.attr,
4534 static struct attribute *slm_format_attr[] = {
4535 &format_attr_offcore_rsp.attr,
4539 static struct attribute *skl_format_attr[] = {
4540 &format_attr_frontend.attr,
4544 static __initconst const struct x86_pmu core_pmu = {
4546 .handle_irq = x86_pmu_handle_irq,
4547 .disable_all = x86_pmu_disable_all,
4548 .enable_all = core_pmu_enable_all,
4549 .enable = core_pmu_enable_event,
4550 .disable = x86_pmu_disable_event,
4551 .hw_config = core_pmu_hw_config,
4552 .schedule_events = x86_schedule_events,
4553 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4554 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4555 .event_map = intel_pmu_event_map,
4556 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4558 .large_pebs_flags = LARGE_PEBS_FLAGS,
4561 * Intel PMCs cannot be accessed sanely above 32-bit width,
4562 * so we install an artificial 1<<31 period regardless of
4563 * the generic event period:
4565 .max_period = (1ULL<<31) - 1,
4566 .get_event_constraints = intel_get_event_constraints,
4567 .put_event_constraints = intel_put_event_constraints,
4568 .event_constraints = intel_core_event_constraints,
4569 .guest_get_msrs = core_guest_get_msrs,
4570 .format_attrs = intel_arch_formats_attr,
4571 .events_sysfs_show = intel_event_sysfs_show,
4574 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4575 * together with PMU version 1 and thus be using core_pmu with
4576 * shared_regs. We need following callbacks here to allocate
4579 .cpu_prepare = intel_pmu_cpu_prepare,
4580 .cpu_starting = intel_pmu_cpu_starting,
4581 .cpu_dying = intel_pmu_cpu_dying,
4582 .cpu_dead = intel_pmu_cpu_dead,
4584 .check_period = intel_pmu_check_period,
4586 .lbr_reset = intel_pmu_lbr_reset_64,
4587 .lbr_read = intel_pmu_lbr_read_64,
4588 .lbr_save = intel_pmu_lbr_save,
4589 .lbr_restore = intel_pmu_lbr_restore,
4592 static __initconst const struct x86_pmu intel_pmu = {
4594 .handle_irq = intel_pmu_handle_irq,
4595 .disable_all = intel_pmu_disable_all,
4596 .enable_all = intel_pmu_enable_all,
4597 .enable = intel_pmu_enable_event,
4598 .disable = intel_pmu_disable_event,
4599 .add = intel_pmu_add_event,
4600 .del = intel_pmu_del_event,
4601 .read = intel_pmu_read_event,
4602 .hw_config = intel_pmu_hw_config,
4603 .schedule_events = x86_schedule_events,
4604 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4605 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4606 .event_map = intel_pmu_event_map,
4607 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4609 .large_pebs_flags = LARGE_PEBS_FLAGS,
4611 * Intel PMCs cannot be accessed sanely above 32 bit width,
4612 * so we install an artificial 1<<31 period regardless of
4613 * the generic event period:
4615 .max_period = (1ULL << 31) - 1,
4616 .get_event_constraints = intel_get_event_constraints,
4617 .put_event_constraints = intel_put_event_constraints,
4618 .pebs_aliases = intel_pebs_aliases_core2,
4620 .format_attrs = intel_arch3_formats_attr,
4621 .events_sysfs_show = intel_event_sysfs_show,
4623 .cpu_prepare = intel_pmu_cpu_prepare,
4624 .cpu_starting = intel_pmu_cpu_starting,
4625 .cpu_dying = intel_pmu_cpu_dying,
4626 .cpu_dead = intel_pmu_cpu_dead,
4628 .guest_get_msrs = intel_guest_get_msrs,
4629 .sched_task = intel_pmu_sched_task,
4630 .swap_task_ctx = intel_pmu_swap_task_ctx,
4632 .check_period = intel_pmu_check_period,
4634 .aux_output_match = intel_pmu_aux_output_match,
4636 .lbr_reset = intel_pmu_lbr_reset_64,
4637 .lbr_read = intel_pmu_lbr_read_64,
4638 .lbr_save = intel_pmu_lbr_save,
4639 .lbr_restore = intel_pmu_lbr_restore,
4642 static __init void intel_clovertown_quirk(void)
4645 * PEBS is unreliable due to:
4647 * AJ67 - PEBS may experience CPL leaks
4648 * AJ68 - PEBS PMI may be delayed by one event
4649 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4650 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4652 * AJ67 could be worked around by restricting the OS/USR flags.
4653 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4655 * AJ106 could possibly be worked around by not allowing LBR
4656 * usage from PEBS, including the fixup.
4657 * AJ68 could possibly be worked around by always programming
4658 * a pebs_event_reset[0] value and coping with the lost events.
4660 * But taken together it might just make sense to not enable PEBS on
4663 pr_warn("PEBS disabled due to CPU errata\n");
4665 x86_pmu.pebs_constraints = NULL;
4668 static const struct x86_cpu_desc isolation_ucodes[] = {
4669 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
4670 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4671 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4672 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
4673 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
4674 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
4675 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4676 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
4677 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
4678 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
4679 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
4680 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 1, 0x0b000014),
4681 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
4682 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
4683 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 5, 0x00000000),
4684 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 6, 0x00000000),
4685 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 7, 0x00000000),
4686 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
4687 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
4688 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
4689 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
4690 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
4691 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
4692 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
4693 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
4694 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
4695 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
4696 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
4700 static void intel_check_pebs_isolation(void)
4702 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4705 static __init void intel_pebs_isolation_quirk(void)
4707 WARN_ON_ONCE(x86_pmu.check_microcode);
4708 x86_pmu.check_microcode = intel_check_pebs_isolation;
4709 intel_check_pebs_isolation();
4712 static const struct x86_cpu_desc pebs_ucodes[] = {
4713 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4714 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4715 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4719 static bool intel_snb_pebs_broken(void)
4721 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4724 static void intel_snb_check_microcode(void)
4726 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4730 * Serialized by the microcode lock..
4732 if (x86_pmu.pebs_broken) {
4733 pr_info("PEBS enabled due to microcode update\n");
4734 x86_pmu.pebs_broken = 0;
4736 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4737 x86_pmu.pebs_broken = 1;
4741 static bool is_lbr_from(unsigned long msr)
4743 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4745 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4749 * Under certain circumstances, access certain MSR may cause #GP.
4750 * The function tests if the input MSR can be safely accessed.
4752 static bool check_msr(unsigned long msr, u64 mask)
4754 u64 val_old, val_new, val_tmp;
4757 * Disable the check for real HW, so we don't
4758 * mess with potentially enabled registers:
4760 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4764 * Read the current value, change it and read it back to see if it
4765 * matches, this is needed to detect certain hardware emulators
4766 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4768 if (rdmsrl_safe(msr, &val_old))
4772 * Only change the bits which can be updated by wrmsrl.
4774 val_tmp = val_old ^ mask;
4776 if (is_lbr_from(msr))
4777 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4779 if (wrmsrl_safe(msr, val_tmp) ||
4780 rdmsrl_safe(msr, &val_new))
4784 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4785 * should equal rdmsrl()'s even with the quirk.
4787 if (val_new != val_tmp)
4790 if (is_lbr_from(msr))
4791 val_old = lbr_from_signext_quirk_wr(val_old);
4793 /* Here it's sure that the MSR can be safely accessed.
4794 * Restore the old value and return.
4796 wrmsrl(msr, val_old);
4801 static __init void intel_sandybridge_quirk(void)
4803 x86_pmu.check_microcode = intel_snb_check_microcode;
4805 intel_snb_check_microcode();
4809 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4810 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4811 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4812 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4813 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4814 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4815 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4816 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4819 static __init void intel_arch_events_quirk(void)
4823 /* disable event that reported as not present by cpuid */
4824 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4825 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4826 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4827 intel_arch_events_map[bit].name);
4831 static __init void intel_nehalem_quirk(void)
4833 union cpuid10_ebx ebx;
4835 ebx.full = x86_pmu.events_maskl;
4836 if (ebx.split.no_branch_misses_retired) {
4838 * Erratum AAJ80 detected, we work it around by using
4839 * the BR_MISP_EXEC.ANY event. This will over-count
4840 * branch-misses, but it's still much better than the
4841 * architectural event which is often completely bogus:
4843 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4844 ebx.split.no_branch_misses_retired = 0;
4845 x86_pmu.events_maskl = ebx.full;
4846 pr_info("CPU erratum AAJ80 worked around\n");
4851 * enable software workaround for errata:
4856 * Only needed when HT is enabled. However detecting
4857 * if HT is enabled is difficult (model specific). So instead,
4858 * we enable the workaround in the early boot, and verify if
4859 * it is needed in a later initcall phase once we have valid
4860 * topology information to check if HT is actually enabled
4862 static __init void intel_ht_bug(void)
4864 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4866 x86_pmu.start_scheduling = intel_start_scheduling;
4867 x86_pmu.commit_scheduling = intel_commit_scheduling;
4868 x86_pmu.stop_scheduling = intel_stop_scheduling;
4871 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4872 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4874 /* Haswell special events */
4875 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4876 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4877 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4878 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4879 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4880 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4881 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4882 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4883 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4884 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4885 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4886 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4888 static struct attribute *hsw_events_attrs[] = {
4889 EVENT_PTR(td_slots_issued),
4890 EVENT_PTR(td_slots_retired),
4891 EVENT_PTR(td_fetch_bubbles),
4892 EVENT_PTR(td_total_slots),
4893 EVENT_PTR(td_total_slots_scale),
4894 EVENT_PTR(td_recovery_bubbles),
4895 EVENT_PTR(td_recovery_bubbles_scale),
4899 static struct attribute *hsw_mem_events_attrs[] = {
4900 EVENT_PTR(mem_ld_hsw),
4901 EVENT_PTR(mem_st_hsw),
4905 static struct attribute *hsw_tsx_events_attrs[] = {
4906 EVENT_PTR(tx_start),
4907 EVENT_PTR(tx_commit),
4908 EVENT_PTR(tx_abort),
4909 EVENT_PTR(tx_capacity),
4910 EVENT_PTR(tx_conflict),
4911 EVENT_PTR(el_start),
4912 EVENT_PTR(el_commit),
4913 EVENT_PTR(el_abort),
4914 EVENT_PTR(el_capacity),
4915 EVENT_PTR(el_conflict),
4916 EVENT_PTR(cycles_t),
4917 EVENT_PTR(cycles_ct),
4921 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
4922 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4923 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
4924 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4926 static struct attribute *icl_events_attrs[] = {
4927 EVENT_PTR(mem_ld_hsw),
4928 EVENT_PTR(mem_st_hsw),
4932 static struct attribute *icl_td_events_attrs[] = {
4934 EVENT_PTR(td_retiring),
4935 EVENT_PTR(td_bad_spec),
4936 EVENT_PTR(td_fe_bound),
4937 EVENT_PTR(td_be_bound),
4941 static struct attribute *icl_tsx_events_attrs[] = {
4942 EVENT_PTR(tx_start),
4943 EVENT_PTR(tx_abort),
4944 EVENT_PTR(tx_commit),
4945 EVENT_PTR(tx_capacity_read),
4946 EVENT_PTR(tx_capacity_write),
4947 EVENT_PTR(tx_conflict),
4948 EVENT_PTR(el_start),
4949 EVENT_PTR(el_abort),
4950 EVENT_PTR(el_commit),
4951 EVENT_PTR(el_capacity_read),
4952 EVENT_PTR(el_capacity_write),
4953 EVENT_PTR(el_conflict),
4954 EVENT_PTR(cycles_t),
4955 EVENT_PTR(cycles_ct),
4960 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
4961 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
4963 static struct attribute *spr_events_attrs[] = {
4964 EVENT_PTR(mem_ld_hsw),
4965 EVENT_PTR(mem_st_spr),
4966 EVENT_PTR(mem_ld_aux),
4970 static struct attribute *spr_td_events_attrs[] = {
4972 EVENT_PTR(td_retiring),
4973 EVENT_PTR(td_bad_spec),
4974 EVENT_PTR(td_fe_bound),
4975 EVENT_PTR(td_be_bound),
4976 EVENT_PTR(td_heavy_ops),
4977 EVENT_PTR(td_br_mispredict),
4978 EVENT_PTR(td_fetch_lat),
4979 EVENT_PTR(td_mem_bound),
4983 static struct attribute *spr_tsx_events_attrs[] = {
4984 EVENT_PTR(tx_start),
4985 EVENT_PTR(tx_abort),
4986 EVENT_PTR(tx_commit),
4987 EVENT_PTR(tx_capacity_read),
4988 EVENT_PTR(tx_capacity_write),
4989 EVENT_PTR(tx_conflict),
4990 EVENT_PTR(cycles_t),
4991 EVENT_PTR(cycles_ct),
4995 static ssize_t freeze_on_smi_show(struct device *cdev,
4996 struct device_attribute *attr,
4999 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5002 static DEFINE_MUTEX(freeze_on_smi_mutex);
5004 static ssize_t freeze_on_smi_store(struct device *cdev,
5005 struct device_attribute *attr,
5006 const char *buf, size_t count)
5011 ret = kstrtoul(buf, 0, &val);
5018 mutex_lock(&freeze_on_smi_mutex);
5020 if (x86_pmu.attr_freeze_on_smi == val)
5023 x86_pmu.attr_freeze_on_smi = val;
5026 on_each_cpu(flip_smm_bit, &val, 1);
5029 mutex_unlock(&freeze_on_smi_mutex);
5034 static void update_tfa_sched(void *ignored)
5036 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5039 * check if PMC3 is used
5040 * and if so force schedule out for all event types all contexts
5042 if (test_bit(3, cpuc->active_mask))
5043 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5046 static ssize_t show_sysctl_tfa(struct device *cdev,
5047 struct device_attribute *attr,
5050 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5053 static ssize_t set_sysctl_tfa(struct device *cdev,
5054 struct device_attribute *attr,
5055 const char *buf, size_t count)
5060 ret = kstrtobool(buf, &val);
5065 if (val == allow_tsx_force_abort)
5068 allow_tsx_force_abort = val;
5071 on_each_cpu(update_tfa_sched, NULL, 1);
5078 static DEVICE_ATTR_RW(freeze_on_smi);
5080 static ssize_t branches_show(struct device *cdev,
5081 struct device_attribute *attr,
5084 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5087 static DEVICE_ATTR_RO(branches);
5089 static struct attribute *lbr_attrs[] = {
5090 &dev_attr_branches.attr,
5094 static char pmu_name_str[30];
5096 static ssize_t pmu_name_show(struct device *cdev,
5097 struct device_attribute *attr,
5100 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
5103 static DEVICE_ATTR_RO(pmu_name);
5105 static struct attribute *intel_pmu_caps_attrs[] = {
5106 &dev_attr_pmu_name.attr,
5110 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5114 static struct attribute *intel_pmu_attrs[] = {
5115 &dev_attr_freeze_on_smi.attr,
5116 &dev_attr_allow_tsx_force_abort.attr,
5121 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5123 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5127 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5129 return x86_pmu.pebs ? attr->mode : 0;
5133 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5135 return x86_pmu.lbr_nr ? attr->mode : 0;
5139 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5141 return x86_pmu.version >= 2 ? attr->mode : 0;
5145 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5147 if (attr == &dev_attr_allow_tsx_force_abort.attr)
5148 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5153 static struct attribute_group group_events_td = {
5157 static struct attribute_group group_events_mem = {
5159 .is_visible = pebs_is_visible,
5162 static struct attribute_group group_events_tsx = {
5164 .is_visible = tsx_is_visible,
5167 static struct attribute_group group_caps_gen = {
5169 .attrs = intel_pmu_caps_attrs,
5172 static struct attribute_group group_caps_lbr = {
5175 .is_visible = lbr_is_visible,
5178 static struct attribute_group group_format_extra = {
5180 .is_visible = exra_is_visible,
5183 static struct attribute_group group_format_extra_skl = {
5185 .is_visible = exra_is_visible,
5188 static struct attribute_group group_default = {
5189 .attrs = intel_pmu_attrs,
5190 .is_visible = default_is_visible,
5193 static const struct attribute_group *attr_update[] = {
5199 &group_format_extra,
5200 &group_format_extra_skl,
5205 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
5206 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
5207 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
5208 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
5209 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
5210 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
5211 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
5212 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
5213 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
5215 static struct attribute *adl_hybrid_events_attrs[] = {
5216 EVENT_PTR(slots_adl),
5217 EVENT_PTR(td_retiring_adl),
5218 EVENT_PTR(td_bad_spec_adl),
5219 EVENT_PTR(td_fe_bound_adl),
5220 EVENT_PTR(td_be_bound_adl),
5221 EVENT_PTR(td_heavy_ops_adl),
5222 EVENT_PTR(td_br_mis_adl),
5223 EVENT_PTR(td_fetch_lat_adl),
5224 EVENT_PTR(td_mem_bound_adl),
5228 /* Must be in IDX order */
5229 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
5230 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
5231 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
5233 static struct attribute *adl_hybrid_mem_attrs[] = {
5234 EVENT_PTR(mem_ld_adl),
5235 EVENT_PTR(mem_st_adl),
5236 EVENT_PTR(mem_ld_aux_adl),
5240 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
5241 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
5242 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
5243 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
5244 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
5245 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
5246 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
5247 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
5249 static struct attribute *adl_hybrid_tsx_attrs[] = {
5250 EVENT_PTR(tx_start_adl),
5251 EVENT_PTR(tx_abort_adl),
5252 EVENT_PTR(tx_commit_adl),
5253 EVENT_PTR(tx_capacity_read_adl),
5254 EVENT_PTR(tx_capacity_write_adl),
5255 EVENT_PTR(tx_conflict_adl),
5256 EVENT_PTR(cycles_t_adl),
5257 EVENT_PTR(cycles_ct_adl),
5261 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
5262 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
5263 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
5264 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small);
5265 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
5267 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
5268 FORMAT_HYBRID_PTR(in_tx),
5269 FORMAT_HYBRID_PTR(in_tx_cp),
5270 FORMAT_HYBRID_PTR(offcore_rsp),
5271 FORMAT_HYBRID_PTR(ldlat),
5272 FORMAT_HYBRID_PTR(frontend),
5276 static struct attribute *adl_hybrid_extra_attr[] = {
5277 FORMAT_HYBRID_PTR(offcore_rsp),
5278 FORMAT_HYBRID_PTR(ldlat),
5279 FORMAT_HYBRID_PTR(frontend),
5283 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
5285 struct device *dev = kobj_to_dev(kobj);
5286 struct x86_hybrid_pmu *pmu =
5287 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5288 struct perf_pmu_events_hybrid_attr *pmu_attr =
5289 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
5291 return pmu->cpu_type & pmu_attr->pmu_type;
5294 static umode_t hybrid_events_is_visible(struct kobject *kobj,
5295 struct attribute *attr, int i)
5297 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
5300 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
5302 int cpu = cpumask_first(&pmu->supported_cpus);
5304 return (cpu >= nr_cpu_ids) ? -1 : cpu;
5307 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
5308 struct attribute *attr, int i)
5310 struct device *dev = kobj_to_dev(kobj);
5311 struct x86_hybrid_pmu *pmu =
5312 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5313 int cpu = hybrid_find_supported_cpu(pmu);
5315 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
5318 static umode_t hybrid_format_is_visible(struct kobject *kobj,
5319 struct attribute *attr, int i)
5321 struct device *dev = kobj_to_dev(kobj);
5322 struct x86_hybrid_pmu *pmu =
5323 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5324 struct perf_pmu_format_hybrid_attr *pmu_attr =
5325 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
5326 int cpu = hybrid_find_supported_cpu(pmu);
5328 return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0;
5331 static struct attribute_group hybrid_group_events_td = {
5333 .is_visible = hybrid_events_is_visible,
5336 static struct attribute_group hybrid_group_events_mem = {
5338 .is_visible = hybrid_events_is_visible,
5341 static struct attribute_group hybrid_group_events_tsx = {
5343 .is_visible = hybrid_tsx_is_visible,
5346 static struct attribute_group hybrid_group_format_extra = {
5348 .is_visible = hybrid_format_is_visible,
5351 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
5352 struct device_attribute *attr,
5355 struct x86_hybrid_pmu *pmu =
5356 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5358 return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
5361 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
5362 static struct attribute *intel_hybrid_cpus_attrs[] = {
5363 &dev_attr_cpus.attr,
5367 static struct attribute_group hybrid_group_cpus = {
5368 .attrs = intel_hybrid_cpus_attrs,
5371 static const struct attribute_group *hybrid_attr_update[] = {
5372 &hybrid_group_events_td,
5373 &hybrid_group_events_mem,
5374 &hybrid_group_events_tsx,
5377 &hybrid_group_format_extra,
5383 static struct attribute *empty_attrs;
5385 static void intel_pmu_check_num_counters(int *num_counters,
5386 int *num_counters_fixed,
5387 u64 *intel_ctrl, u64 fixed_mask)
5389 if (*num_counters > INTEL_PMC_MAX_GENERIC) {
5390 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5391 *num_counters, INTEL_PMC_MAX_GENERIC);
5392 *num_counters = INTEL_PMC_MAX_GENERIC;
5394 *intel_ctrl = (1ULL << *num_counters) - 1;
5396 if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5397 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5398 *num_counters_fixed, INTEL_PMC_MAX_FIXED);
5399 *num_counters_fixed = INTEL_PMC_MAX_FIXED;
5402 *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED;
5405 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5407 int num_counters_fixed,
5410 struct event_constraint *c;
5412 if (!event_constraints)
5416 * event on fixed counter2 (REF_CYCLES) only works on this
5417 * counter, so do not extend mask to generic counters
5419 for_each_event_constraint(c, event_constraints) {
5421 * Don't extend the topdown slots and metrics
5422 * events to the generic counters.
5424 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5426 * Disable topdown slots and metrics events,
5427 * if slots event is not in CPUID.
5429 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
5431 c->weight = hweight64(c->idxmsk64);
5435 if (c->cmask == FIXED_EVENT_FLAGS) {
5436 /* Disabled fixed counters which are not in CPUID */
5437 c->idxmsk64 &= intel_ctrl;
5439 if (c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES)
5440 c->idxmsk64 |= (1ULL << num_counters) - 1;
5443 ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed));
5444 c->weight = hweight64(c->idxmsk64);
5448 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
5450 struct extra_reg *er;
5453 * Access extra MSR may cause #GP under certain circumstances.
5454 * E.g. KVM doesn't support offcore event
5455 * Check all extra_regs here.
5460 for (er = extra_regs; er->msr; er++) {
5461 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5462 /* Disable LBR select mapping */
5463 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5464 x86_pmu.lbr_sel_map = NULL;
5468 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask)
5470 struct x86_hybrid_pmu *pmu;
5473 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5474 pmu = &x86_pmu.hybrid_pmu[i];
5476 intel_pmu_check_num_counters(&pmu->num_counters,
5477 &pmu->num_counters_fixed,
5481 if (pmu->intel_cap.perf_metrics) {
5482 pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5483 pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS;
5486 if (pmu->intel_cap.pebs_output_pt_available)
5487 pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
5489 intel_pmu_check_event_constraints(pmu->event_constraints,
5491 pmu->num_counters_fixed,
5494 intel_pmu_check_extra_regs(pmu->extra_regs);
5498 __init int intel_pmu_init(void)
5500 struct attribute **extra_skl_attr = &empty_attrs;
5501 struct attribute **extra_attr = &empty_attrs;
5502 struct attribute **td_attr = &empty_attrs;
5503 struct attribute **mem_attr = &empty_attrs;
5504 struct attribute **tsx_attr = &empty_attrs;
5505 union cpuid10_edx edx;
5506 union cpuid10_eax eax;
5507 union cpuid10_ebx ebx;
5508 unsigned int fixed_mask;
5512 struct x86_hybrid_pmu *pmu;
5514 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
5515 switch (boot_cpu_data.x86) {
5517 return p6_pmu_init();
5519 return knc_pmu_init();
5521 return p4_pmu_init();
5527 * Check whether the Architectural PerfMon supports
5528 * Branch Misses Retired hw_event or not.
5530 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
5531 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
5534 version = eax.split.version_id;
5538 x86_pmu = intel_pmu;
5540 x86_pmu.version = version;
5541 x86_pmu.num_counters = eax.split.num_counters;
5542 x86_pmu.cntval_bits = eax.split.bit_width;
5543 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
5545 x86_pmu.events_maskl = ebx.full;
5546 x86_pmu.events_mask_len = eax.split.mask_length;
5548 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
5551 * Quirk: v2 perfmon does not report fixed-purpose events, so
5552 * assume at least 3 events, when not running in a hypervisor:
5554 if (version > 1 && version < 5) {
5555 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
5557 x86_pmu.num_counters_fixed =
5558 max((int)edx.split.num_counters_fixed, assume);
5560 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
5561 } else if (version >= 5)
5562 x86_pmu.num_counters_fixed = fls(fixed_mask);
5564 if (boot_cpu_has(X86_FEATURE_PDCM)) {
5567 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
5568 x86_pmu.intel_cap.capabilities = capabilities;
5571 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
5572 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
5573 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
5576 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
5577 intel_pmu_arch_lbr_init();
5581 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5584 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5585 if (x86_pmu.intel_cap.anythread_deprecated)
5586 pr_cont(" AnyThread deprecated, ");
5590 * Install the hw-cache-events table:
5592 switch (boot_cpu_data.x86_model) {
5593 case INTEL_FAM6_CORE_YONAH:
5594 pr_cont("Core events, ");
5598 case INTEL_FAM6_CORE2_MEROM:
5599 x86_add_quirk(intel_clovertown_quirk);
5602 case INTEL_FAM6_CORE2_MEROM_L:
5603 case INTEL_FAM6_CORE2_PENRYN:
5604 case INTEL_FAM6_CORE2_DUNNINGTON:
5605 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5606 sizeof(hw_cache_event_ids));
5608 intel_pmu_lbr_init_core();
5610 x86_pmu.event_constraints = intel_core2_event_constraints;
5611 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5612 pr_cont("Core2 events, ");
5616 case INTEL_FAM6_NEHALEM:
5617 case INTEL_FAM6_NEHALEM_EP:
5618 case INTEL_FAM6_NEHALEM_EX:
5619 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5620 sizeof(hw_cache_event_ids));
5621 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5622 sizeof(hw_cache_extra_regs));
5624 intel_pmu_lbr_init_nhm();
5626 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5627 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5628 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5629 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5630 x86_pmu.limit_period = nhm_limit_period;
5632 mem_attr = nhm_mem_events_attrs;
5634 /* UOPS_ISSUED.STALLED_CYCLES */
5635 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5636 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5637 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5638 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5639 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5641 intel_pmu_pebs_data_source_nhm();
5642 x86_add_quirk(intel_nehalem_quirk);
5643 x86_pmu.pebs_no_tlb = 1;
5644 extra_attr = nhm_format_attr;
5646 pr_cont("Nehalem events, ");
5650 case INTEL_FAM6_ATOM_BONNELL:
5651 case INTEL_FAM6_ATOM_BONNELL_MID:
5652 case INTEL_FAM6_ATOM_SALTWELL:
5653 case INTEL_FAM6_ATOM_SALTWELL_MID:
5654 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5655 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5656 sizeof(hw_cache_event_ids));
5658 intel_pmu_lbr_init_atom();
5660 x86_pmu.event_constraints = intel_gen_event_constraints;
5661 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5662 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5663 pr_cont("Atom events, ");
5667 case INTEL_FAM6_ATOM_SILVERMONT:
5668 case INTEL_FAM6_ATOM_SILVERMONT_D:
5669 case INTEL_FAM6_ATOM_SILVERMONT_MID:
5670 case INTEL_FAM6_ATOM_AIRMONT:
5671 case INTEL_FAM6_ATOM_AIRMONT_MID:
5672 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5673 sizeof(hw_cache_event_ids));
5674 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5675 sizeof(hw_cache_extra_regs));
5677 intel_pmu_lbr_init_slm();
5679 x86_pmu.event_constraints = intel_slm_event_constraints;
5680 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5681 x86_pmu.extra_regs = intel_slm_extra_regs;
5682 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5683 td_attr = slm_events_attrs;
5684 extra_attr = slm_format_attr;
5685 pr_cont("Silvermont events, ");
5686 name = "silvermont";
5689 case INTEL_FAM6_ATOM_GOLDMONT:
5690 case INTEL_FAM6_ATOM_GOLDMONT_D:
5691 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5692 sizeof(hw_cache_event_ids));
5693 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5694 sizeof(hw_cache_extra_regs));
5696 intel_pmu_lbr_init_skl();
5698 x86_pmu.event_constraints = intel_slm_event_constraints;
5699 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5700 x86_pmu.extra_regs = intel_glm_extra_regs;
5702 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5703 * for precise cycles.
5704 * :pp is identical to :ppp
5706 x86_pmu.pebs_aliases = NULL;
5707 x86_pmu.pebs_prec_dist = true;
5708 x86_pmu.lbr_pt_coexist = true;
5709 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5710 td_attr = glm_events_attrs;
5711 extra_attr = slm_format_attr;
5712 pr_cont("Goldmont events, ");
5716 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5717 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5718 sizeof(hw_cache_event_ids));
5719 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5720 sizeof(hw_cache_extra_regs));
5722 intel_pmu_lbr_init_skl();
5724 x86_pmu.event_constraints = intel_slm_event_constraints;
5725 x86_pmu.extra_regs = intel_glm_extra_regs;
5727 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5728 * for precise cycles.
5730 x86_pmu.pebs_aliases = NULL;
5731 x86_pmu.pebs_prec_dist = true;
5732 x86_pmu.lbr_pt_coexist = true;
5733 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5734 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5735 x86_pmu.get_event_constraints = glp_get_event_constraints;
5736 td_attr = glm_events_attrs;
5737 /* Goldmont Plus has 4-wide pipeline */
5738 event_attr_td_total_slots_scale_glm.event_str = "4";
5739 extra_attr = slm_format_attr;
5740 pr_cont("Goldmont plus events, ");
5741 name = "goldmont_plus";
5744 case INTEL_FAM6_ATOM_TREMONT_D:
5745 case INTEL_FAM6_ATOM_TREMONT:
5746 case INTEL_FAM6_ATOM_TREMONT_L:
5747 x86_pmu.late_ack = true;
5748 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5749 sizeof(hw_cache_event_ids));
5750 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5751 sizeof(hw_cache_extra_regs));
5752 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5754 intel_pmu_lbr_init_skl();
5756 x86_pmu.event_constraints = intel_slm_event_constraints;
5757 x86_pmu.extra_regs = intel_tnt_extra_regs;
5759 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5760 * for precise cycles.
5762 x86_pmu.pebs_aliases = NULL;
5763 x86_pmu.pebs_prec_dist = true;
5764 x86_pmu.lbr_pt_coexist = true;
5765 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5766 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5767 td_attr = tnt_events_attrs;
5768 extra_attr = slm_format_attr;
5769 pr_cont("Tremont events, ");
5773 case INTEL_FAM6_WESTMERE:
5774 case INTEL_FAM6_WESTMERE_EP:
5775 case INTEL_FAM6_WESTMERE_EX:
5776 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5777 sizeof(hw_cache_event_ids));
5778 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5779 sizeof(hw_cache_extra_regs));
5781 intel_pmu_lbr_init_nhm();
5783 x86_pmu.event_constraints = intel_westmere_event_constraints;
5784 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5785 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5786 x86_pmu.extra_regs = intel_westmere_extra_regs;
5787 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5789 mem_attr = nhm_mem_events_attrs;
5791 /* UOPS_ISSUED.STALLED_CYCLES */
5792 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5793 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5794 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5795 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5796 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5798 intel_pmu_pebs_data_source_nhm();
5799 extra_attr = nhm_format_attr;
5800 pr_cont("Westmere events, ");
5804 case INTEL_FAM6_SANDYBRIDGE:
5805 case INTEL_FAM6_SANDYBRIDGE_X:
5806 x86_add_quirk(intel_sandybridge_quirk);
5807 x86_add_quirk(intel_ht_bug);
5808 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5809 sizeof(hw_cache_event_ids));
5810 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5811 sizeof(hw_cache_extra_regs));
5813 intel_pmu_lbr_init_snb();
5815 x86_pmu.event_constraints = intel_snb_event_constraints;
5816 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5817 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5818 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5819 x86_pmu.extra_regs = intel_snbep_extra_regs;
5821 x86_pmu.extra_regs = intel_snb_extra_regs;
5824 /* all extra regs are per-cpu when HT is on */
5825 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5826 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5828 td_attr = snb_events_attrs;
5829 mem_attr = snb_mem_events_attrs;
5831 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5832 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5833 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5834 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5835 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5836 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5838 extra_attr = nhm_format_attr;
5840 pr_cont("SandyBridge events, ");
5841 name = "sandybridge";
5844 case INTEL_FAM6_IVYBRIDGE:
5845 case INTEL_FAM6_IVYBRIDGE_X:
5846 x86_add_quirk(intel_ht_bug);
5847 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5848 sizeof(hw_cache_event_ids));
5849 /* dTLB-load-misses on IVB is different than SNB */
5850 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5852 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5853 sizeof(hw_cache_extra_regs));
5855 intel_pmu_lbr_init_snb();
5857 x86_pmu.event_constraints = intel_ivb_event_constraints;
5858 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5859 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5860 x86_pmu.pebs_prec_dist = true;
5861 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5862 x86_pmu.extra_regs = intel_snbep_extra_regs;
5864 x86_pmu.extra_regs = intel_snb_extra_regs;
5865 /* all extra regs are per-cpu when HT is on */
5866 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5867 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5869 td_attr = snb_events_attrs;
5870 mem_attr = snb_mem_events_attrs;
5872 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5873 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5874 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5876 extra_attr = nhm_format_attr;
5878 pr_cont("IvyBridge events, ");
5883 case INTEL_FAM6_HASWELL:
5884 case INTEL_FAM6_HASWELL_X:
5885 case INTEL_FAM6_HASWELL_L:
5886 case INTEL_FAM6_HASWELL_G:
5887 x86_add_quirk(intel_ht_bug);
5888 x86_add_quirk(intel_pebs_isolation_quirk);
5889 x86_pmu.late_ack = true;
5890 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5891 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5893 intel_pmu_lbr_init_hsw();
5895 x86_pmu.event_constraints = intel_hsw_event_constraints;
5896 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
5897 x86_pmu.extra_regs = intel_snbep_extra_regs;
5898 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5899 x86_pmu.pebs_prec_dist = true;
5900 /* all extra regs are per-cpu when HT is on */
5901 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5902 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5904 x86_pmu.hw_config = hsw_hw_config;
5905 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5906 x86_pmu.lbr_double_abort = true;
5907 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5908 hsw_format_attr : nhm_format_attr;
5909 td_attr = hsw_events_attrs;
5910 mem_attr = hsw_mem_events_attrs;
5911 tsx_attr = hsw_tsx_events_attrs;
5912 pr_cont("Haswell events, ");
5916 case INTEL_FAM6_BROADWELL:
5917 case INTEL_FAM6_BROADWELL_D:
5918 case INTEL_FAM6_BROADWELL_G:
5919 case INTEL_FAM6_BROADWELL_X:
5920 x86_add_quirk(intel_pebs_isolation_quirk);
5921 x86_pmu.late_ack = true;
5922 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5923 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5925 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
5926 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
5927 BDW_L3_MISS|HSW_SNOOP_DRAM;
5928 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
5930 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
5931 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5932 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
5933 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5935 intel_pmu_lbr_init_hsw();
5937 x86_pmu.event_constraints = intel_bdw_event_constraints;
5938 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
5939 x86_pmu.extra_regs = intel_snbep_extra_regs;
5940 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5941 x86_pmu.pebs_prec_dist = true;
5942 /* all extra regs are per-cpu when HT is on */
5943 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5944 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5946 x86_pmu.hw_config = hsw_hw_config;
5947 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5948 x86_pmu.limit_period = bdw_limit_period;
5949 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5950 hsw_format_attr : nhm_format_attr;
5951 td_attr = hsw_events_attrs;
5952 mem_attr = hsw_mem_events_attrs;
5953 tsx_attr = hsw_tsx_events_attrs;
5954 pr_cont("Broadwell events, ");
5958 case INTEL_FAM6_XEON_PHI_KNL:
5959 case INTEL_FAM6_XEON_PHI_KNM:
5960 memcpy(hw_cache_event_ids,
5961 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5962 memcpy(hw_cache_extra_regs,
5963 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5964 intel_pmu_lbr_init_knl();
5966 x86_pmu.event_constraints = intel_slm_event_constraints;
5967 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5968 x86_pmu.extra_regs = intel_knl_extra_regs;
5970 /* all extra regs are per-cpu when HT is on */
5971 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5972 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5973 extra_attr = slm_format_attr;
5974 pr_cont("Knights Landing/Mill events, ");
5975 name = "knights-landing";
5978 case INTEL_FAM6_SKYLAKE_X:
5981 case INTEL_FAM6_SKYLAKE_L:
5982 case INTEL_FAM6_SKYLAKE:
5983 case INTEL_FAM6_KABYLAKE_L:
5984 case INTEL_FAM6_KABYLAKE:
5985 case INTEL_FAM6_COMETLAKE_L:
5986 case INTEL_FAM6_COMETLAKE:
5987 x86_add_quirk(intel_pebs_isolation_quirk);
5988 x86_pmu.late_ack = true;
5989 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5990 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5991 intel_pmu_lbr_init_skl();
5993 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5994 event_attr_td_recovery_bubbles.event_str_noht =
5995 "event=0xd,umask=0x1,cmask=1";
5996 event_attr_td_recovery_bubbles.event_str_ht =
5997 "event=0xd,umask=0x1,cmask=1,any=1";
5999 x86_pmu.event_constraints = intel_skl_event_constraints;
6000 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6001 x86_pmu.extra_regs = intel_skl_extra_regs;
6002 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6003 x86_pmu.pebs_prec_dist = true;
6004 /* all extra regs are per-cpu when HT is on */
6005 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6006 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6008 x86_pmu.hw_config = hsw_hw_config;
6009 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6010 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6011 hsw_format_attr : nhm_format_attr;
6012 extra_skl_attr = skl_format_attr;
6013 td_attr = hsw_events_attrs;
6014 mem_attr = hsw_mem_events_attrs;
6015 tsx_attr = hsw_tsx_events_attrs;
6016 intel_pmu_pebs_data_source_skl(pmem);
6018 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
6019 x86_pmu.flags |= PMU_FL_TFA;
6020 x86_pmu.get_event_constraints = tfa_get_event_constraints;
6021 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
6022 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
6025 pr_cont("Skylake events, ");
6029 case INTEL_FAM6_ICELAKE_X:
6030 case INTEL_FAM6_ICELAKE_D:
6033 case INTEL_FAM6_ICELAKE_L:
6034 case INTEL_FAM6_ICELAKE:
6035 case INTEL_FAM6_TIGERLAKE_L:
6036 case INTEL_FAM6_TIGERLAKE:
6037 case INTEL_FAM6_ROCKETLAKE:
6038 x86_pmu.late_ack = true;
6039 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6040 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6041 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6042 intel_pmu_lbr_init_skl();
6044 x86_pmu.event_constraints = intel_icl_event_constraints;
6045 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
6046 x86_pmu.extra_regs = intel_icl_extra_regs;
6047 x86_pmu.pebs_aliases = NULL;
6048 x86_pmu.pebs_prec_dist = true;
6049 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6050 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6052 x86_pmu.hw_config = hsw_hw_config;
6053 x86_pmu.get_event_constraints = icl_get_event_constraints;
6054 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6055 hsw_format_attr : nhm_format_attr;
6056 extra_skl_attr = skl_format_attr;
6057 mem_attr = icl_events_attrs;
6058 td_attr = icl_td_events_attrs;
6059 tsx_attr = icl_tsx_events_attrs;
6060 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6061 x86_pmu.lbr_pt_coexist = true;
6062 intel_pmu_pebs_data_source_skl(pmem);
6063 x86_pmu.num_topdown_events = 4;
6064 x86_pmu.update_topdown_event = icl_update_topdown_event;
6065 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
6066 pr_cont("Icelake events, ");
6070 case INTEL_FAM6_SAPPHIRERAPIDS_X:
6072 x86_pmu.late_ack = true;
6073 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6074 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6076 x86_pmu.event_constraints = intel_spr_event_constraints;
6077 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
6078 x86_pmu.extra_regs = intel_spr_extra_regs;
6079 x86_pmu.limit_period = spr_limit_period;
6080 x86_pmu.pebs_aliases = NULL;
6081 x86_pmu.pebs_prec_dist = true;
6082 x86_pmu.pebs_block = true;
6083 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6084 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6085 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6086 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6087 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6089 x86_pmu.hw_config = hsw_hw_config;
6090 x86_pmu.get_event_constraints = spr_get_event_constraints;
6091 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6092 hsw_format_attr : nhm_format_attr;
6093 extra_skl_attr = skl_format_attr;
6094 mem_attr = spr_events_attrs;
6095 td_attr = spr_td_events_attrs;
6096 tsx_attr = spr_tsx_events_attrs;
6097 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6098 x86_pmu.lbr_pt_coexist = true;
6099 intel_pmu_pebs_data_source_skl(pmem);
6100 x86_pmu.num_topdown_events = 8;
6101 x86_pmu.update_topdown_event = icl_update_topdown_event;
6102 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
6103 pr_cont("Sapphire Rapids events, ");
6104 name = "sapphire_rapids";
6107 case INTEL_FAM6_ALDERLAKE:
6108 case INTEL_FAM6_ALDERLAKE_L:
6110 * Alder Lake has 2 types of CPU, core and atom.
6112 * Initialize the common PerfMon capabilities here.
6114 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS,
6115 sizeof(struct x86_hybrid_pmu),
6117 if (!x86_pmu.hybrid_pmu)
6119 static_branch_enable(&perf_is_hybrid);
6120 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS;
6122 x86_pmu.late_ack = true;
6123 x86_pmu.pebs_aliases = NULL;
6124 x86_pmu.pebs_prec_dist = true;
6125 x86_pmu.pebs_block = true;
6126 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6127 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6128 x86_pmu.flags |= PMU_FL_PEBS_ALL;
6129 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6130 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6131 x86_pmu.lbr_pt_coexist = true;
6132 intel_pmu_pebs_data_source_skl(false);
6133 x86_pmu.num_topdown_events = 8;
6134 x86_pmu.update_topdown_event = adl_update_topdown_event;
6135 x86_pmu.set_topdown_event_period = adl_set_topdown_event_period;
6137 x86_pmu.filter_match = intel_pmu_filter_match;
6138 x86_pmu.get_event_constraints = adl_get_event_constraints;
6139 x86_pmu.hw_config = adl_hw_config;
6140 x86_pmu.limit_period = spr_limit_period;
6141 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
6143 * The rtm_abort_event is used to check whether to enable GPRs
6144 * for the RTM abort event. Atom doesn't have the RTM abort
6145 * event. There is no harmful to set it in the common
6146 * x86_pmu.rtm_abort_event.
6148 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6150 td_attr = adl_hybrid_events_attrs;
6151 mem_attr = adl_hybrid_mem_attrs;
6152 tsx_attr = adl_hybrid_tsx_attrs;
6153 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6154 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
6156 /* Initialize big core specific PerfMon capabilities.*/
6157 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
6158 pmu->name = "cpu_core";
6159 pmu->cpu_type = hybrid_big;
6160 pmu->num_counters = x86_pmu.num_counters + 2;
6161 pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1;
6162 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
6163 pmu->unconstrained = (struct event_constraint)
6164 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6165 0, pmu->num_counters, 0, 0);
6166 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6167 pmu->intel_cap.perf_metrics = 1;
6168 pmu->intel_cap.pebs_output_pt_available = 0;
6170 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6171 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6172 pmu->event_constraints = intel_spr_event_constraints;
6173 pmu->pebs_constraints = intel_spr_pebs_event_constraints;
6174 pmu->extra_regs = intel_spr_extra_regs;
6176 /* Initialize Atom core specific PerfMon capabilities.*/
6177 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
6178 pmu->name = "cpu_atom";
6179 pmu->cpu_type = hybrid_small;
6180 pmu->num_counters = x86_pmu.num_counters;
6181 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6182 pmu->max_pebs_events = x86_pmu.max_pebs_events;
6183 pmu->unconstrained = (struct event_constraint)
6184 __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6185 0, pmu->num_counters, 0, 0);
6186 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6187 pmu->intel_cap.perf_metrics = 0;
6188 pmu->intel_cap.pebs_output_pt_available = 1;
6190 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6191 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6192 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6193 pmu->event_constraints = intel_slm_event_constraints;
6194 pmu->pebs_constraints = intel_grt_pebs_event_constraints;
6195 pmu->extra_regs = intel_grt_extra_regs;
6196 pr_cont("Alderlake Hybrid events, ");
6197 name = "alderlake_hybrid";
6201 switch (x86_pmu.version) {
6203 x86_pmu.event_constraints = intel_v1_event_constraints;
6204 pr_cont("generic architected perfmon v1, ");
6205 name = "generic_arch_v1";
6209 * default constraints for v2 and up
6211 x86_pmu.event_constraints = intel_gen_event_constraints;
6212 pr_cont("generic architected perfmon, ");
6213 name = "generic_arch_v2+";
6218 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
6221 group_events_td.attrs = td_attr;
6222 group_events_mem.attrs = mem_attr;
6223 group_events_tsx.attrs = tsx_attr;
6224 group_format_extra.attrs = extra_attr;
6225 group_format_extra_skl.attrs = extra_skl_attr;
6227 x86_pmu.attr_update = attr_update;
6229 hybrid_group_events_td.attrs = td_attr;
6230 hybrid_group_events_mem.attrs = mem_attr;
6231 hybrid_group_events_tsx.attrs = tsx_attr;
6232 hybrid_group_format_extra.attrs = extra_attr;
6234 x86_pmu.attr_update = hybrid_attr_update;
6237 intel_pmu_check_num_counters(&x86_pmu.num_counters,
6238 &x86_pmu.num_counters_fixed,
6239 &x86_pmu.intel_ctrl,
6242 /* AnyThread may be deprecated on arch perfmon v5 or later */
6243 if (x86_pmu.intel_cap.anythread_deprecated)
6244 x86_pmu.format_attrs = intel_arch_formats_attr;
6246 intel_pmu_check_event_constraints(x86_pmu.event_constraints,
6247 x86_pmu.num_counters,
6248 x86_pmu.num_counters_fixed,
6249 x86_pmu.intel_ctrl);
6251 * Access LBR MSR may cause #GP under certain circumstances.
6252 * E.g. KVM doesn't support LBR MSR
6253 * Check all LBT MSR here.
6254 * Disable LBR access if any LBR MSRs can not be accessed.
6256 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
6258 for (i = 0; i < x86_pmu.lbr_nr; i++) {
6259 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
6260 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
6265 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
6267 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
6269 /* Support full width counters using alternative MSR range */
6270 if (x86_pmu.intel_cap.full_width_write) {
6271 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
6272 x86_pmu.perfctr = MSR_IA32_PMC0;
6273 pr_cont("full-width counters, ");
6276 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
6277 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
6280 intel_pmu_check_hybrid_pmus((u64)fixed_mask);
6286 * HT bug: phase 2 init
6287 * Called once we have valid topology information to check
6288 * whether or not HT is enabled
6289 * If HT is off, then we disable the workaround
6291 static __init int fixup_ht_bug(void)
6295 * problem not present on this CPU model, nothing to do
6297 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
6300 if (topology_max_smt_threads() > 1) {
6301 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
6307 hardlockup_detector_perf_stop();
6309 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
6311 x86_pmu.start_scheduling = NULL;
6312 x86_pmu.commit_scheduling = NULL;
6313 x86_pmu.stop_scheduling = NULL;
6315 hardlockup_detector_perf_restart();
6317 for_each_online_cpu(c)
6318 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
6321 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
6324 subsys_initcall(fixup_ht_bug)