arch/x86/events/intel/core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Per core/cpu state
   4  *
   5  * Used to coordinate shared registers between HT threads or
   6  * among events on a single PMU.
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/stddef.h>
  12 #include <linux/types.h>
  13 #include <linux/init.h>
  14 #include <linux/slab.h>
  15 #include <linux/export.h>
  16 #include <linux/nmi.h>
  17 #include <linux/kvm_host.h>
  18
  19 #include <asm/cpufeature.h>
  20 #include <asm/hardirq.h>
  21 #include <asm/intel-family.h>
  22 #include <asm/intel_pt.h>
  23 #include <asm/apic.h>
  24 #include <asm/cpu_device_id.h>
  25
  26 #include "../perf_event.h"
  27
  28 /*
  29  * Intel PerfMon, used on Core and later.
  30  */
  31 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
  32 {
  33         [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
  34         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
  35         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
  36         [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
  37         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
  38         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
  39         [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
  40         [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
  41 };
  42
  43 static struct event_constraint intel_core_event_constraints[] __read_mostly =
  44 {
  45         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  46         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  47         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  48         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  49         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  50         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  51         EVENT_CONSTRAINT_END
  52 };
  53
  54 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
  55 {
  56         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  57         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  58         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  59         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  60         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  61         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  62         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  63         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  64         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  65         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  66         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  67         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  68         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  69         EVENT_CONSTRAINT_END
  70 };
  71
  72 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
  73 {
  74         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  75         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  76         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
  77         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  78         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  79         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  80         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  81         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  82         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  83         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  84         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  85         EVENT_CONSTRAINT_END
  86 };
  87
  88 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
  89 {
  90         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
  91         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
  92         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
  93         EVENT_EXTRA_END
  94 };
  95
  96 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
  97 {
  98         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  99         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 100         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 101         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
 102         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
 103         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
 104         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
 105         EVENT_CONSTRAINT_END
 106 };
 107
 108 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 109 {
 110         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 111         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 112         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 113         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 114         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 115         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 116         INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 117         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 118         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 119         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 120         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
 121         INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 122
 123         /*
 124          * When HT is off these events can only run on the bottom 4 counters
 125          * When HT is on, they are impacted by the HT bug and require EXCL access
 126          */
 127         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 128         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 129         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 130         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 131
 132         EVENT_CONSTRAINT_END
 133 };
 134
 135 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
 136 {
 137         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 138         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 139         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 140         INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
 141         INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
 142         INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
 143         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
 144         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 145         INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
 146         INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
 147         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 148         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 149         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 150
 151         /*
 152          * When HT is off these events can only run on the bottom 4 counters
 153          * When HT is on, they are impacted by the HT bug and require EXCL access
 154          */
 155         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 156         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 157         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 158         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 159
 160         EVENT_CONSTRAINT_END
 161 };
 162
 163 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 164 {
 165         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 166         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
 167         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
 168         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
 169         EVENT_EXTRA_END
 170 };
 171
 172 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
 173 {
 174         EVENT_CONSTRAINT_END
 175 };
 176
 177 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 178 {
 179         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 180         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 181         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 182         EVENT_CONSTRAINT_END
 183 };
 184
 185 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
 186 {
 187         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 188         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 189         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 190         FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
 191         FIXED_EVENT_CONSTRAINT(0x0500, 4),
 192         FIXED_EVENT_CONSTRAINT(0x0600, 5),
 193         FIXED_EVENT_CONSTRAINT(0x0700, 6),
 194         FIXED_EVENT_CONSTRAINT(0x0800, 7),
 195         FIXED_EVENT_CONSTRAINT(0x0900, 8),
 196         FIXED_EVENT_CONSTRAINT(0x0a00, 9),
 197         FIXED_EVENT_CONSTRAINT(0x0b00, 10),
 198         FIXED_EVENT_CONSTRAINT(0x0c00, 11),
 199         FIXED_EVENT_CONSTRAINT(0x0d00, 12),
 200         FIXED_EVENT_CONSTRAINT(0x0e00, 13),
 201         FIXED_EVENT_CONSTRAINT(0x0f00, 14),
 202         FIXED_EVENT_CONSTRAINT(0x1000, 15),
 203         EVENT_CONSTRAINT_END
 204 };
 205
 206 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
 207 {
 208         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 209         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 210         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
 211         EVENT_CONSTRAINT_END
 212 };
 213
 214 static struct event_constraint intel_skl_event_constraints[] = {
 215         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 216         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 217         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 218         INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),    /* INST_RETIRED.PREC_DIST */
 219
 220         /*
 221          * when HT is off, these can only run on the bottom 4 counters
 222          */
 223         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 224         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 225         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 226         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 227         INTEL_EVENT_CONSTRAINT(0xc6, 0xf),      /* FRONTEND_RETIRED.* */
 228
 229         EVENT_CONSTRAINT_END
 230 };
 231
 232 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
 233         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
 234         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 235         EVENT_EXTRA_END
 236 };
 237
 238 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
 239         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 240         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
 241         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
 242         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 243         EVENT_EXTRA_END
 244 };
 245
 246 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
 247         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
 248         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 249         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 250         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 251         EVENT_EXTRA_END
 252 };
 253
 254 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
 255         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
 256         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
 257         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 258         /*
 259          * Note the low 8 bits eventsel code is not a continuous field, containing
 260          * some #GPing bits. These are masked out.
 261          */
 262         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 263         EVENT_EXTRA_END
 264 };
 265
 266 static struct event_constraint intel_icl_event_constraints[] = {
 267         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 268         FIXED_EVENT_CONSTRAINT(0x01c0, 0),      /* old INST_RETIRED.PREC_DIST */
 269         FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* INST_RETIRED.PREC_DIST */
 270         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 271         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 272         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 273         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 274         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 275         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 276         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 277         INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
 278         INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
 279         INTEL_EVENT_CONSTRAINT(0x32, 0xf),      /* SW_PREFETCH_ACCESS.* */
 280         INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
 281         INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
 282         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_TOTAL */
 283         INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff),  /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
 284         INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff),  /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
 285         INTEL_EVENT_CONSTRAINT(0xa3, 0xf),      /* CYCLE_ACTIVITY.* */
 286         INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
 287         INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
 288         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
 289         INTEL_EVENT_CONSTRAINT(0xef, 0xf),
 290         INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
 291         EVENT_CONSTRAINT_END
 292 };
 293
 294 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
 295         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
 296         INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 297         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 298         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 299         EVENT_EXTRA_END
 300 };
 301
 302 static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
 303         INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
 304         INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
 305         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 306         INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
 307         INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
 308         INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
 309         EVENT_EXTRA_END
 310 };
 311
 312 static struct event_constraint intel_spr_event_constraints[] = {
 313         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 314         FIXED_EVENT_CONSTRAINT(0x0100, 0),      /* INST_RETIRED.PREC_DIST */
 315         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 316         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 317         FIXED_EVENT_CONSTRAINT(0x0400, 3),      /* SLOTS */
 318         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
 319         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
 320         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
 321         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
 322         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
 323         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
 324         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
 325         METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
 326
 327         INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
 328         INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
 329         /*
 330          * Generally event codes < 0x90 are restricted to counters 0-3.
 331          * The 0x2E and 0x3C are exception, which has no restriction.
 332          */
 333         INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
 334
 335         INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
 336         INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
 337         INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
 338         INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
 339         INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
 340         INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
 341         INTEL_EVENT_CONSTRAINT(0xce, 0x1),
 342         INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
 343         /*
 344          * Generally event codes >= 0x90 are likely to have no restrictions.
 345          * The exception are defined as above.
 346          */
 347         INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
 348
 349         EVENT_CONSTRAINT_END
 350 };
 351
 352
 353 EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
 354 EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
 355 EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 356
 357 static struct attribute *nhm_mem_events_attrs[] = {
 358         EVENT_PTR(mem_ld_nhm),
 359         NULL,
 360 };
 361
 362 /*
 363  * topdown events for Intel Core CPUs.
 364  *
 365  * The events are all in slots, which is a free slot in a 4 wide
 366  * pipeline. Some events are already reported in slots, for cycle
 367  * events we multiply by the pipeline width (4).
 368  *
 369  * With Hyper Threading on, topdown metrics are either summed or averaged
 370  * between the threads of a core: (count_t0 + count_t1).
 371  *
 372  * For the average case the metric is always scaled to pipeline width,
 373  * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
 374  */
 375
 376 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
 377         "event=0x3c,umask=0x0",                 /* cpu_clk_unhalted.thread */
 378         "event=0x3c,umask=0x0,any=1");          /* cpu_clk_unhalted.thread_any */
 379 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
 380 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
 381         "event=0xe,umask=0x1");                 /* uops_issued.any */
 382 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
 383         "event=0xc2,umask=0x2");                /* uops_retired.retire_slots */
 384 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
 385         "event=0x9c,umask=0x1");                /* idq_uops_not_delivered_core */
 386 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
 387         "event=0xd,umask=0x3,cmask=1",          /* int_misc.recovery_cycles */
 388         "event=0xd,umask=0x3,cmask=1,any=1");   /* int_misc.recovery_cycles_any */
 389 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
 390         "4", "2");
 391
 392 EVENT_ATTR_STR(slots,                   slots,                  "event=0x00,umask=0x4");
 393 EVENT_ATTR_STR(topdown-retiring,        td_retiring,            "event=0x00,umask=0x80");
 394 EVENT_ATTR_STR(topdown-bad-spec,        td_bad_spec,            "event=0x00,umask=0x81");
 395 EVENT_ATTR_STR(topdown-fe-bound,        td_fe_bound,            "event=0x00,umask=0x82");
 396 EVENT_ATTR_STR(topdown-be-bound,        td_be_bound,            "event=0x00,umask=0x83");
 397 EVENT_ATTR_STR(topdown-heavy-ops,       td_heavy_ops,           "event=0x00,umask=0x84");
 398 EVENT_ATTR_STR(topdown-br-mispredict,   td_br_mispredict,       "event=0x00,umask=0x85");
 399 EVENT_ATTR_STR(topdown-fetch-lat,       td_fetch_lat,           "event=0x00,umask=0x86");
 400 EVENT_ATTR_STR(topdown-mem-bound,       td_mem_bound,           "event=0x00,umask=0x87");
 401
 402 static struct attribute *snb_events_attrs[] = {
 403         EVENT_PTR(td_slots_issued),
 404         EVENT_PTR(td_slots_retired),
 405         EVENT_PTR(td_fetch_bubbles),
 406         EVENT_PTR(td_total_slots),
 407         EVENT_PTR(td_total_slots_scale),
 408         EVENT_PTR(td_recovery_bubbles),
 409         EVENT_PTR(td_recovery_bubbles_scale),
 410         NULL,
 411 };
 412
 413 static struct attribute *snb_mem_events_attrs[] = {
 414         EVENT_PTR(mem_ld_snb),
 415         EVENT_PTR(mem_st_snb),
 416         NULL,
 417 };
 418
 419 static struct event_constraint intel_hsw_event_constraints[] = {
 420         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
 421         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
 422         FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
 423         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 424         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 425         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
 426         /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 427         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
 428         /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
 429         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
 430         /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
 431         INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
 432
 433         /*
 434          * When HT is off these events can only run on the bottom 4 counters
 435          * When HT is on, they are impacted by the HT bug and require EXCL access
 436          */
 437         INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
 438         INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
 439         INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 440         INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
 441
 442         EVENT_CONSTRAINT_END
 443 };
 444
 445 static struct event_constraint intel_bdw_event_constraints[] = {
 446         FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
 447         FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
 448         FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
 449         INTEL_UEVENT_CONSTRAINT(0x148, 0x4),    /* L1D_PEND_MISS.PENDING */
 450         INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),        /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
 451         /*
 452          * when HT is off, these can only run on the bottom 4 counters
 453          */
 454         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),      /* MEM_INST_RETIRED.* */
 455         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),      /* MEM_LOAD_RETIRED.* */
 456         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),      /* MEM_LOAD_L3_HIT_RETIRED.* */
 457         INTEL_EVENT_CONSTRAINT(0xcd, 0xf),      /* MEM_TRANS_RETIRED.* */
 458         EVENT_CONSTRAINT_END
 459 };
 460
 461 static u64 intel_pmu_event_map(int hw_event)
 462 {
 463         return intel_perfmon_event_map[hw_event];
 464 }
 465
 466 static __initconst const u64 spr_hw_cache_event_ids
 467                                 [PERF_COUNT_HW_CACHE_MAX]
 468                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 469                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 470 {
 471  [ C(L1D ) ] = {
 472         [ C(OP_READ) ] = {
 473                 [ C(RESULT_ACCESS) ] = 0x81d0,
 474                 [ C(RESULT_MISS)   ] = 0xe124,
 475         },
 476         [ C(OP_WRITE) ] = {
 477                 [ C(RESULT_ACCESS) ] = 0x82d0,
 478         },
 479  },
 480  [ C(L1I ) ] = {
 481         [ C(OP_READ) ] = {
 482                 [ C(RESULT_MISS)   ] = 0xe424,
 483         },
 484         [ C(OP_WRITE) ] = {
 485                 [ C(RESULT_ACCESS) ] = -1,
 486                 [ C(RESULT_MISS)   ] = -1,
 487         },
 488  },
 489  [ C(LL  ) ] = {
 490         [ C(OP_READ) ] = {
 491                 [ C(RESULT_ACCESS) ] = 0x12a,
 492                 [ C(RESULT_MISS)   ] = 0x12a,
 493         },
 494         [ C(OP_WRITE) ] = {
 495                 [ C(RESULT_ACCESS) ] = 0x12a,
 496                 [ C(RESULT_MISS)   ] = 0x12a,
 497         },
 498  },
 499  [ C(DTLB) ] = {
 500         [ C(OP_READ) ] = {
 501                 [ C(RESULT_ACCESS) ] = 0x81d0,
 502                 [ C(RESULT_MISS)   ] = 0xe12,
 503         },
 504         [ C(OP_WRITE) ] = {
 505                 [ C(RESULT_ACCESS) ] = 0x82d0,
 506                 [ C(RESULT_MISS)   ] = 0xe13,
 507         },
 508  },
 509  [ C(ITLB) ] = {
 510         [ C(OP_READ) ] = {
 511                 [ C(RESULT_ACCESS) ] = -1,
 512                 [ C(RESULT_MISS)   ] = 0xe11,
 513         },
 514         [ C(OP_WRITE) ] = {
 515                 [ C(RESULT_ACCESS) ] = -1,
 516                 [ C(RESULT_MISS)   ] = -1,
 517         },
 518         [ C(OP_PREFETCH) ] = {
 519                 [ C(RESULT_ACCESS) ] = -1,
 520                 [ C(RESULT_MISS)   ] = -1,
 521         },
 522  },
 523  [ C(BPU ) ] = {
 524         [ C(OP_READ) ] = {
 525                 [ C(RESULT_ACCESS) ] = 0x4c4,
 526                 [ C(RESULT_MISS)   ] = 0x4c5,
 527         },
 528         [ C(OP_WRITE) ] = {
 529                 [ C(RESULT_ACCESS) ] = -1,
 530                 [ C(RESULT_MISS)   ] = -1,
 531         },
 532         [ C(OP_PREFETCH) ] = {
 533                 [ C(RESULT_ACCESS) ] = -1,
 534                 [ C(RESULT_MISS)   ] = -1,
 535         },
 536  },
 537  [ C(NODE) ] = {
 538         [ C(OP_READ) ] = {
 539                 [ C(RESULT_ACCESS) ] = 0x12a,
 540                 [ C(RESULT_MISS)   ] = 0x12a,
 541         },
 542  },
 543 };
 544
 545 static __initconst const u64 spr_hw_cache_extra_regs
 546                                 [PERF_COUNT_HW_CACHE_MAX]
 547                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 548                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 549 {
 550  [ C(LL  ) ] = {
 551         [ C(OP_READ) ] = {
 552                 [ C(RESULT_ACCESS) ] = 0x10001,
 553                 [ C(RESULT_MISS)   ] = 0x3fbfc00001,
 554         },
 555         [ C(OP_WRITE) ] = {
 556                 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
 557                 [ C(RESULT_MISS)   ] = 0x3f3fc00002,
 558         },
 559  },
 560  [ C(NODE) ] = {
 561         [ C(OP_READ) ] = {
 562                 [ C(RESULT_ACCESS) ] = 0x10c000001,
 563                 [ C(RESULT_MISS)   ] = 0x3fb3000001,
 564         },
 565  },
 566 };
 567
 568 /*
 569  * Notes on the events:
 570  * - data reads do not include code reads (comparable to earlier tables)
 571  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 572  * - remote node access includes remote memory, remote cache, remote mmio.
 573  * - prefetches are not included in the counts.
 574  * - icache miss does not include decoded icache
 575  */
 576
 577 #define SKL_DEMAND_DATA_RD              BIT_ULL(0)
 578 #define SKL_DEMAND_RFO                  BIT_ULL(1)
 579 #define SKL_ANY_RESPONSE                BIT_ULL(16)
 580 #define SKL_SUPPLIER_NONE               BIT_ULL(17)
 581 #define SKL_L3_MISS_LOCAL_DRAM          BIT_ULL(26)
 582 #define SKL_L3_MISS_REMOTE_HOP0_DRAM    BIT_ULL(27)
 583 #define SKL_L3_MISS_REMOTE_HOP1_DRAM    BIT_ULL(28)
 584 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM   BIT_ULL(29)
 585 #define SKL_L3_MISS                     (SKL_L3_MISS_LOCAL_DRAM| \
 586                                          SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 587                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 588                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 589 #define SKL_SPL_HIT                     BIT_ULL(30)
 590 #define SKL_SNOOP_NONE                  BIT_ULL(31)
 591 #define SKL_SNOOP_NOT_NEEDED            BIT_ULL(32)
 592 #define SKL_SNOOP_MISS                  BIT_ULL(33)
 593 #define SKL_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 594 #define SKL_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 595 #define SKL_SNOOP_HITM                  BIT_ULL(36)
 596 #define SKL_SNOOP_NON_DRAM              BIT_ULL(37)
 597 #define SKL_ANY_SNOOP                   (SKL_SPL_HIT|SKL_SNOOP_NONE| \
 598                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 599                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 600                                          SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
 601 #define SKL_DEMAND_READ                 SKL_DEMAND_DATA_RD
 602 #define SKL_SNOOP_DRAM                  (SKL_SNOOP_NONE| \
 603                                          SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
 604                                          SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
 605                                          SKL_SNOOP_HITM|SKL_SPL_HIT)
 606 #define SKL_DEMAND_WRITE                SKL_DEMAND_RFO
 607 #define SKL_LLC_ACCESS                  SKL_ANY_RESPONSE
 608 #define SKL_L3_MISS_REMOTE              (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
 609                                          SKL_L3_MISS_REMOTE_HOP1_DRAM| \
 610                                          SKL_L3_MISS_REMOTE_HOP2P_DRAM)
 611
 612 static __initconst const u64 skl_hw_cache_event_ids
 613                                 [PERF_COUNT_HW_CACHE_MAX]
 614                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 615                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 616 {
 617  [ C(L1D ) ] = {
 618         [ C(OP_READ) ] = {
 619                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 620                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
 621         },
 622         [ C(OP_WRITE) ] = {
 623                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 624                 [ C(RESULT_MISS)   ] = 0x0,
 625         },
 626         [ C(OP_PREFETCH) ] = {
 627                 [ C(RESULT_ACCESS) ] = 0x0,
 628                 [ C(RESULT_MISS)   ] = 0x0,
 629         },
 630  },
 631  [ C(L1I ) ] = {
 632         [ C(OP_READ) ] = {
 633                 [ C(RESULT_ACCESS) ] = 0x0,
 634                 [ C(RESULT_MISS)   ] = 0x283,   /* ICACHE_64B.MISS */
 635         },
 636         [ C(OP_WRITE) ] = {
 637                 [ C(RESULT_ACCESS) ] = -1,
 638                 [ C(RESULT_MISS)   ] = -1,
 639         },
 640         [ C(OP_PREFETCH) ] = {
 641                 [ C(RESULT_ACCESS) ] = 0x0,
 642                 [ C(RESULT_MISS)   ] = 0x0,
 643         },
 644  },
 645  [ C(LL  ) ] = {
 646         [ C(OP_READ) ] = {
 647                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 648                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 649         },
 650         [ C(OP_WRITE) ] = {
 651                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 652                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 653         },
 654         [ C(OP_PREFETCH) ] = {
 655                 [ C(RESULT_ACCESS) ] = 0x0,
 656                 [ C(RESULT_MISS)   ] = 0x0,
 657         },
 658  },
 659  [ C(DTLB) ] = {
 660         [ C(OP_READ) ] = {
 661                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_INST_RETIRED.ALL_LOADS */
 662                 [ C(RESULT_MISS)   ] = 0xe08,   /* DTLB_LOAD_MISSES.WALK_COMPLETED */
 663         },
 664         [ C(OP_WRITE) ] = {
 665                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_INST_RETIRED.ALL_STORES */
 666                 [ C(RESULT_MISS)   ] = 0xe49,   /* DTLB_STORE_MISSES.WALK_COMPLETED */
 667         },
 668         [ C(OP_PREFETCH) ] = {
 669                 [ C(RESULT_ACCESS) ] = 0x0,
 670                 [ C(RESULT_MISS)   ] = 0x0,
 671         },
 672  },
 673  [ C(ITLB) ] = {
 674         [ C(OP_READ) ] = {
 675                 [ C(RESULT_ACCESS) ] = 0x2085,  /* ITLB_MISSES.STLB_HIT */
 676                 [ C(RESULT_MISS)   ] = 0xe85,   /* ITLB_MISSES.WALK_COMPLETED */
 677         },
 678         [ C(OP_WRITE) ] = {
 679                 [ C(RESULT_ACCESS) ] = -1,
 680                 [ C(RESULT_MISS)   ] = -1,
 681         },
 682         [ C(OP_PREFETCH) ] = {
 683                 [ C(RESULT_ACCESS) ] = -1,
 684                 [ C(RESULT_MISS)   ] = -1,
 685         },
 686  },
 687  [ C(BPU ) ] = {
 688         [ C(OP_READ) ] = {
 689                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
 690                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
 691         },
 692         [ C(OP_WRITE) ] = {
 693                 [ C(RESULT_ACCESS) ] = -1,
 694                 [ C(RESULT_MISS)   ] = -1,
 695         },
 696         [ C(OP_PREFETCH) ] = {
 697                 [ C(RESULT_ACCESS) ] = -1,
 698                 [ C(RESULT_MISS)   ] = -1,
 699         },
 700  },
 701  [ C(NODE) ] = {
 702         [ C(OP_READ) ] = {
 703                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 704                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 705         },
 706         [ C(OP_WRITE) ] = {
 707                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
 708                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
 709         },
 710         [ C(OP_PREFETCH) ] = {
 711                 [ C(RESULT_ACCESS) ] = 0x0,
 712                 [ C(RESULT_MISS)   ] = 0x0,
 713         },
 714  },
 715 };
 716
 717 static __initconst const u64 skl_hw_cache_extra_regs
 718                                 [PERF_COUNT_HW_CACHE_MAX]
 719                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 720                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 721 {
 722  [ C(LL  ) ] = {
 723         [ C(OP_READ) ] = {
 724                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 725                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 726                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 727                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 728                                        SKL_SUPPLIER_NONE,
 729         },
 730         [ C(OP_WRITE) ] = {
 731                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 732                                        SKL_LLC_ACCESS|SKL_ANY_SNOOP,
 733                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 734                                        SKL_L3_MISS|SKL_ANY_SNOOP|
 735                                        SKL_SUPPLIER_NONE,
 736         },
 737         [ C(OP_PREFETCH) ] = {
 738                 [ C(RESULT_ACCESS) ] = 0x0,
 739                 [ C(RESULT_MISS)   ] = 0x0,
 740         },
 741  },
 742  [ C(NODE) ] = {
 743         [ C(OP_READ) ] = {
 744                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
 745                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 746                 [ C(RESULT_MISS)   ] = SKL_DEMAND_READ|
 747                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 748         },
 749         [ C(OP_WRITE) ] = {
 750                 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
 751                                        SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
 752                 [ C(RESULT_MISS)   ] = SKL_DEMAND_WRITE|
 753                                        SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
 754         },
 755         [ C(OP_PREFETCH) ] = {
 756                 [ C(RESULT_ACCESS) ] = 0x0,
 757                 [ C(RESULT_MISS)   ] = 0x0,
 758         },
 759  },
 760 };
 761
 762 #define SNB_DMND_DATA_RD        (1ULL << 0)
 763 #define SNB_DMND_RFO            (1ULL << 1)
 764 #define SNB_DMND_IFETCH         (1ULL << 2)
 765 #define SNB_DMND_WB             (1ULL << 3)
 766 #define SNB_PF_DATA_RD          (1ULL << 4)
 767 #define SNB_PF_RFO              (1ULL << 5)
 768 #define SNB_PF_IFETCH           (1ULL << 6)
 769 #define SNB_LLC_DATA_RD         (1ULL << 7)
 770 #define SNB_LLC_RFO             (1ULL << 8)
 771 #define SNB_LLC_IFETCH          (1ULL << 9)
 772 #define SNB_BUS_LOCKS           (1ULL << 10)
 773 #define SNB_STRM_ST             (1ULL << 11)
 774 #define SNB_OTHER               (1ULL << 15)
 775 #define SNB_RESP_ANY            (1ULL << 16)
 776 #define SNB_NO_SUPP             (1ULL << 17)
 777 #define SNB_LLC_HITM            (1ULL << 18)
 778 #define SNB_LLC_HITE            (1ULL << 19)
 779 #define SNB_LLC_HITS            (1ULL << 20)
 780 #define SNB_LLC_HITF            (1ULL << 21)
 781 #define SNB_LOCAL               (1ULL << 22)
 782 #define SNB_REMOTE              (0xffULL << 23)
 783 #define SNB_SNP_NONE            (1ULL << 31)
 784 #define SNB_SNP_NOT_NEEDED      (1ULL << 32)
 785 #define SNB_SNP_MISS            (1ULL << 33)
 786 #define SNB_NO_FWD              (1ULL << 34)
 787 #define SNB_SNP_FWD             (1ULL << 35)
 788 #define SNB_HITM                (1ULL << 36)
 789 #define SNB_NON_DRAM            (1ULL << 37)
 790
 791 #define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
 792 #define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
 793 #define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
 794
 795 #define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
 796                                  SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
 797                                  SNB_HITM)
 798
 799 #define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
 800 #define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
 801
 802 #define SNB_L3_ACCESS           SNB_RESP_ANY
 803 #define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
 804
 805 static __initconst const u64 snb_hw_cache_extra_regs
 806                                 [PERF_COUNT_HW_CACHE_MAX]
 807                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 808                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 809 {
 810  [ C(LL  ) ] = {
 811         [ C(OP_READ) ] = {
 812                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
 813                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
 814         },
 815         [ C(OP_WRITE) ] = {
 816                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
 817                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
 818         },
 819         [ C(OP_PREFETCH) ] = {
 820                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
 821                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
 822         },
 823  },
 824  [ C(NODE) ] = {
 825         [ C(OP_READ) ] = {
 826                 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
 827                 [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
 828         },
 829         [ C(OP_WRITE) ] = {
 830                 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
 831                 [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
 832         },
 833         [ C(OP_PREFETCH) ] = {
 834                 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
 835                 [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
 836         },
 837  },
 838 };
 839
 840 static __initconst const u64 snb_hw_cache_event_ids
 841                                 [PERF_COUNT_HW_CACHE_MAX]
 842                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 843                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 844 {
 845  [ C(L1D) ] = {
 846         [ C(OP_READ) ] = {
 847                 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS        */
 848                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPLACEMENT              */
 849         },
 850         [ C(OP_WRITE) ] = {
 851                 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES       */
 852                 [ C(RESULT_MISS)   ] = 0x0851, /* L1D.ALL_M_REPLACEMENT        */
 853         },
 854         [ C(OP_PREFETCH) ] = {
 855                 [ C(RESULT_ACCESS) ] = 0x0,
 856                 [ C(RESULT_MISS)   ] = 0x024e, /* HW_PRE_REQ.DL1_MISS          */
 857         },
 858  },
 859  [ C(L1I ) ] = {
 860         [ C(OP_READ) ] = {
 861                 [ C(RESULT_ACCESS) ] = 0x0,
 862                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACHE.MISSES */
 863         },
 864         [ C(OP_WRITE) ] = {
 865                 [ C(RESULT_ACCESS) ] = -1,
 866                 [ C(RESULT_MISS)   ] = -1,
 867         },
 868         [ C(OP_PREFETCH) ] = {
 869                 [ C(RESULT_ACCESS) ] = 0x0,
 870                 [ C(RESULT_MISS)   ] = 0x0,
 871         },
 872  },
 873  [ C(LL  ) ] = {
 874         [ C(OP_READ) ] = {
 875                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
 876                 [ C(RESULT_ACCESS) ] = 0x01b7,
 877                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
 878                 [ C(RESULT_MISS)   ] = 0x01b7,
 879         },
 880         [ C(OP_WRITE) ] = {
 881                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
 882                 [ C(RESULT_ACCESS) ] = 0x01b7,
 883                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
 884                 [ C(RESULT_MISS)   ] = 0x01b7,
 885         },
 886         [ C(OP_PREFETCH) ] = {
 887                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
 888                 [ C(RESULT_ACCESS) ] = 0x01b7,
 889                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
 890                 [ C(RESULT_MISS)   ] = 0x01b7,
 891         },
 892  },
 893  [ C(DTLB) ] = {
 894         [ C(OP_READ) ] = {
 895                 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
 896                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
 897         },
 898         [ C(OP_WRITE) ] = {
 899                 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
 900                 [ C(RESULT_MISS)   ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
 901         },
 902         [ C(OP_PREFETCH) ] = {
 903                 [ C(RESULT_ACCESS) ] = 0x0,
 904                 [ C(RESULT_MISS)   ] = 0x0,
 905         },
 906  },
 907  [ C(ITLB) ] = {
 908         [ C(OP_READ) ] = {
 909                 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT         */
 910                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK    */
 911         },
 912         [ C(OP_WRITE) ] = {
 913                 [ C(RESULT_ACCESS) ] = -1,
 914                 [ C(RESULT_MISS)   ] = -1,
 915         },
 916         [ C(OP_PREFETCH) ] = {
 917                 [ C(RESULT_ACCESS) ] = -1,
 918                 [ C(RESULT_MISS)   ] = -1,
 919         },
 920  },
 921  [ C(BPU ) ] = {
 922         [ C(OP_READ) ] = {
 923                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 924                 [ C(RESULT_MISS)   ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
 925         },
 926         [ C(OP_WRITE) ] = {
 927                 [ C(RESULT_ACCESS) ] = -1,
 928                 [ C(RESULT_MISS)   ] = -1,
 929         },
 930         [ C(OP_PREFETCH) ] = {
 931                 [ C(RESULT_ACCESS) ] = -1,
 932                 [ C(RESULT_MISS)   ] = -1,
 933         },
 934  },
 935  [ C(NODE) ] = {
 936         [ C(OP_READ) ] = {
 937                 [ C(RESULT_ACCESS) ] = 0x01b7,
 938                 [ C(RESULT_MISS)   ] = 0x01b7,
 939         },
 940         [ C(OP_WRITE) ] = {
 941                 [ C(RESULT_ACCESS) ] = 0x01b7,
 942                 [ C(RESULT_MISS)   ] = 0x01b7,
 943         },
 944         [ C(OP_PREFETCH) ] = {
 945                 [ C(RESULT_ACCESS) ] = 0x01b7,
 946                 [ C(RESULT_MISS)   ] = 0x01b7,
 947         },
 948  },
 949
 950 };
 951
 952 /*
 953  * Notes on the events:
 954  * - data reads do not include code reads (comparable to earlier tables)
 955  * - data counts include speculative execution (except L1 write, dtlb, bpu)
 956  * - remote node access includes remote memory, remote cache, remote mmio.
 957  * - prefetches are not included in the counts because they are not
 958  *   reliably counted.
 959  */
 960
 961 #define HSW_DEMAND_DATA_RD              BIT_ULL(0)
 962 #define HSW_DEMAND_RFO                  BIT_ULL(1)
 963 #define HSW_ANY_RESPONSE                BIT_ULL(16)
 964 #define HSW_SUPPLIER_NONE               BIT_ULL(17)
 965 #define HSW_L3_MISS_LOCAL_DRAM          BIT_ULL(22)
 966 #define HSW_L3_MISS_REMOTE_HOP0         BIT_ULL(27)
 967 #define HSW_L3_MISS_REMOTE_HOP1         BIT_ULL(28)
 968 #define HSW_L3_MISS_REMOTE_HOP2P        BIT_ULL(29)
 969 #define HSW_L3_MISS                     (HSW_L3_MISS_LOCAL_DRAM| \
 970                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 971                                          HSW_L3_MISS_REMOTE_HOP2P)
 972 #define HSW_SNOOP_NONE                  BIT_ULL(31)
 973 #define HSW_SNOOP_NOT_NEEDED            BIT_ULL(32)
 974 #define HSW_SNOOP_MISS                  BIT_ULL(33)
 975 #define HSW_SNOOP_HIT_NO_FWD            BIT_ULL(34)
 976 #define HSW_SNOOP_HIT_WITH_FWD          BIT_ULL(35)
 977 #define HSW_SNOOP_HITM                  BIT_ULL(36)
 978 #define HSW_SNOOP_NON_DRAM              BIT_ULL(37)
 979 #define HSW_ANY_SNOOP                   (HSW_SNOOP_NONE| \
 980                                          HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
 981                                          HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
 982                                          HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
 983 #define HSW_SNOOP_DRAM                  (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
 984 #define HSW_DEMAND_READ                 HSW_DEMAND_DATA_RD
 985 #define HSW_DEMAND_WRITE                HSW_DEMAND_RFO
 986 #define HSW_L3_MISS_REMOTE              (HSW_L3_MISS_REMOTE_HOP0|\
 987                                          HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
 988 #define HSW_LLC_ACCESS                  HSW_ANY_RESPONSE
 989
 990 #define BDW_L3_MISS_LOCAL               BIT(26)
 991 #define BDW_L3_MISS                     (BDW_L3_MISS_LOCAL| \
 992                                          HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
 993                                          HSW_L3_MISS_REMOTE_HOP2P)
 994
 995
 996 static __initconst const u64 hsw_hw_cache_event_ids
 997                                 [PERF_COUNT_HW_CACHE_MAX]
 998                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 999                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1000 {
1001  [ C(L1D ) ] = {
1002         [ C(OP_READ) ] = {
1003                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
1004                 [ C(RESULT_MISS)   ] = 0x151,   /* L1D.REPLACEMENT */
1005         },
1006         [ C(OP_WRITE) ] = {
1007                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
1008                 [ C(RESULT_MISS)   ] = 0x0,
1009         },
1010         [ C(OP_PREFETCH) ] = {
1011                 [ C(RESULT_ACCESS) ] = 0x0,
1012                 [ C(RESULT_MISS)   ] = 0x0,
1013         },
1014  },
1015  [ C(L1I ) ] = {
1016         [ C(OP_READ) ] = {
1017                 [ C(RESULT_ACCESS) ] = 0x0,
1018                 [ C(RESULT_MISS)   ] = 0x280,   /* ICACHE.MISSES */
1019         },
1020         [ C(OP_WRITE) ] = {
1021                 [ C(RESULT_ACCESS) ] = -1,
1022                 [ C(RESULT_MISS)   ] = -1,
1023         },
1024         [ C(OP_PREFETCH) ] = {
1025                 [ C(RESULT_ACCESS) ] = 0x0,
1026                 [ C(RESULT_MISS)   ] = 0x0,
1027         },
1028  },
1029  [ C(LL  ) ] = {
1030         [ C(OP_READ) ] = {
1031                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1032                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1033         },
1034         [ C(OP_WRITE) ] = {
1035                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1036                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1037         },
1038         [ C(OP_PREFETCH) ] = {
1039                 [ C(RESULT_ACCESS) ] = 0x0,
1040                 [ C(RESULT_MISS)   ] = 0x0,
1041         },
1042  },
1043  [ C(DTLB) ] = {
1044         [ C(OP_READ) ] = {
1045                 [ C(RESULT_ACCESS) ] = 0x81d0,  /* MEM_UOPS_RETIRED.ALL_LOADS */
1046                 [ C(RESULT_MISS)   ] = 0x108,   /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1047         },
1048         [ C(OP_WRITE) ] = {
1049                 [ C(RESULT_ACCESS) ] = 0x82d0,  /* MEM_UOPS_RETIRED.ALL_STORES */
1050                 [ C(RESULT_MISS)   ] = 0x149,   /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1051         },
1052         [ C(OP_PREFETCH) ] = {
1053                 [ C(RESULT_ACCESS) ] = 0x0,
1054                 [ C(RESULT_MISS)   ] = 0x0,
1055         },
1056  },
1057  [ C(ITLB) ] = {
1058         [ C(OP_READ) ] = {
1059                 [ C(RESULT_ACCESS) ] = 0x6085,  /* ITLB_MISSES.STLB_HIT */
1060                 [ C(RESULT_MISS)   ] = 0x185,   /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1061         },
1062         [ C(OP_WRITE) ] = {
1063                 [ C(RESULT_ACCESS) ] = -1,
1064                 [ C(RESULT_MISS)   ] = -1,
1065         },
1066         [ C(OP_PREFETCH) ] = {
1067                 [ C(RESULT_ACCESS) ] = -1,
1068                 [ C(RESULT_MISS)   ] = -1,
1069         },
1070  },
1071  [ C(BPU ) ] = {
1072         [ C(OP_READ) ] = {
1073                 [ C(RESULT_ACCESS) ] = 0xc4,    /* BR_INST_RETIRED.ALL_BRANCHES */
1074                 [ C(RESULT_MISS)   ] = 0xc5,    /* BR_MISP_RETIRED.ALL_BRANCHES */
1075         },
1076         [ C(OP_WRITE) ] = {
1077                 [ C(RESULT_ACCESS) ] = -1,
1078                 [ C(RESULT_MISS)   ] = -1,
1079         },
1080         [ C(OP_PREFETCH) ] = {
1081                 [ C(RESULT_ACCESS) ] = -1,
1082                 [ C(RESULT_MISS)   ] = -1,
1083         },
1084  },
1085  [ C(NODE) ] = {
1086         [ C(OP_READ) ] = {
1087                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1088                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1089         },
1090         [ C(OP_WRITE) ] = {
1091                 [ C(RESULT_ACCESS) ] = 0x1b7,   /* OFFCORE_RESPONSE */
1092                 [ C(RESULT_MISS)   ] = 0x1b7,   /* OFFCORE_RESPONSE */
1093         },
1094         [ C(OP_PREFETCH) ] = {
1095                 [ C(RESULT_ACCESS) ] = 0x0,
1096                 [ C(RESULT_MISS)   ] = 0x0,
1097         },
1098  },
1099 };
1100
1101 static __initconst const u64 hsw_hw_cache_extra_regs
1102                                 [PERF_COUNT_HW_CACHE_MAX]
1103                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1104                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1105 {
1106  [ C(LL  ) ] = {
1107         [ C(OP_READ) ] = {
1108                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1109                                        HSW_LLC_ACCESS,
1110                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1111                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1112         },
1113         [ C(OP_WRITE) ] = {
1114                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1115                                        HSW_LLC_ACCESS,
1116                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1117                                        HSW_L3_MISS|HSW_ANY_SNOOP,
1118         },
1119         [ C(OP_PREFETCH) ] = {
1120                 [ C(RESULT_ACCESS) ] = 0x0,
1121                 [ C(RESULT_MISS)   ] = 0x0,
1122         },
1123  },
1124  [ C(NODE) ] = {
1125         [ C(OP_READ) ] = {
1126                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1127                                        HSW_L3_MISS_LOCAL_DRAM|
1128                                        HSW_SNOOP_DRAM,
1129                 [ C(RESULT_MISS)   ] = HSW_DEMAND_READ|
1130                                        HSW_L3_MISS_REMOTE|
1131                                        HSW_SNOOP_DRAM,
1132         },
1133         [ C(OP_WRITE) ] = {
1134                 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1135                                        HSW_L3_MISS_LOCAL_DRAM|
1136                                        HSW_SNOOP_DRAM,
1137                 [ C(RESULT_MISS)   ] = HSW_DEMAND_WRITE|
1138                                        HSW_L3_MISS_REMOTE|
1139                                        HSW_SNOOP_DRAM,
1140         },
1141         [ C(OP_PREFETCH) ] = {
1142                 [ C(RESULT_ACCESS) ] = 0x0,
1143                 [ C(RESULT_MISS)   ] = 0x0,
1144         },
1145  },
1146 };
1147
1148 static __initconst const u64 westmere_hw_cache_event_ids
1149                                 [PERF_COUNT_HW_CACHE_MAX]
1150                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1151                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1152 {
1153  [ C(L1D) ] = {
1154         [ C(OP_READ) ] = {
1155                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1156                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1157         },
1158         [ C(OP_WRITE) ] = {
1159                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1160                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1161         },
1162         [ C(OP_PREFETCH) ] = {
1163                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1164                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1165         },
1166  },
1167  [ C(L1I ) ] = {
1168         [ C(OP_READ) ] = {
1169                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1170                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1171         },
1172         [ C(OP_WRITE) ] = {
1173                 [ C(RESULT_ACCESS) ] = -1,
1174                 [ C(RESULT_MISS)   ] = -1,
1175         },
1176         [ C(OP_PREFETCH) ] = {
1177                 [ C(RESULT_ACCESS) ] = 0x0,
1178                 [ C(RESULT_MISS)   ] = 0x0,
1179         },
1180  },
1181  [ C(LL  ) ] = {
1182         [ C(OP_READ) ] = {
1183                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1184                 [ C(RESULT_ACCESS) ] = 0x01b7,
1185                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1186                 [ C(RESULT_MISS)   ] = 0x01b7,
1187         },
1188         /*
1189          * Use RFO, not WRITEBACK, because a write miss would typically occur
1190          * on RFO.
1191          */
1192         [ C(OP_WRITE) ] = {
1193                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1194                 [ C(RESULT_ACCESS) ] = 0x01b7,
1195                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1196                 [ C(RESULT_MISS)   ] = 0x01b7,
1197         },
1198         [ C(OP_PREFETCH) ] = {
1199                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1200                 [ C(RESULT_ACCESS) ] = 0x01b7,
1201                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1202                 [ C(RESULT_MISS)   ] = 0x01b7,
1203         },
1204  },
1205  [ C(DTLB) ] = {
1206         [ C(OP_READ) ] = {
1207                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1208                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1209         },
1210         [ C(OP_WRITE) ] = {
1211                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1212                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1213         },
1214         [ C(OP_PREFETCH) ] = {
1215                 [ C(RESULT_ACCESS) ] = 0x0,
1216                 [ C(RESULT_MISS)   ] = 0x0,
1217         },
1218  },
1219  [ C(ITLB) ] = {
1220         [ C(OP_READ) ] = {
1221                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1222                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
1223         },
1224         [ C(OP_WRITE) ] = {
1225                 [ C(RESULT_ACCESS) ] = -1,
1226                 [ C(RESULT_MISS)   ] = -1,
1227         },
1228         [ C(OP_PREFETCH) ] = {
1229                 [ C(RESULT_ACCESS) ] = -1,
1230                 [ C(RESULT_MISS)   ] = -1,
1231         },
1232  },
1233  [ C(BPU ) ] = {
1234         [ C(OP_READ) ] = {
1235                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1236                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1237         },
1238         [ C(OP_WRITE) ] = {
1239                 [ C(RESULT_ACCESS) ] = -1,
1240                 [ C(RESULT_MISS)   ] = -1,
1241         },
1242         [ C(OP_PREFETCH) ] = {
1243                 [ C(RESULT_ACCESS) ] = -1,
1244                 [ C(RESULT_MISS)   ] = -1,
1245         },
1246  },
1247  [ C(NODE) ] = {
1248         [ C(OP_READ) ] = {
1249                 [ C(RESULT_ACCESS) ] = 0x01b7,
1250                 [ C(RESULT_MISS)   ] = 0x01b7,
1251         },
1252         [ C(OP_WRITE) ] = {
1253                 [ C(RESULT_ACCESS) ] = 0x01b7,
1254                 [ C(RESULT_MISS)   ] = 0x01b7,
1255         },
1256         [ C(OP_PREFETCH) ] = {
1257                 [ C(RESULT_ACCESS) ] = 0x01b7,
1258                 [ C(RESULT_MISS)   ] = 0x01b7,
1259         },
1260  },
1261 };
1262
1263 /*
1264  * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1265  * See IA32 SDM Vol 3B 30.6.1.3
1266  */
1267
1268 #define NHM_DMND_DATA_RD        (1 << 0)
1269 #define NHM_DMND_RFO            (1 << 1)
1270 #define NHM_DMND_IFETCH         (1 << 2)
1271 #define NHM_DMND_WB             (1 << 3)
1272 #define NHM_PF_DATA_RD          (1 << 4)
1273 #define NHM_PF_DATA_RFO         (1 << 5)
1274 #define NHM_PF_IFETCH           (1 << 6)
1275 #define NHM_OFFCORE_OTHER       (1 << 7)
1276 #define NHM_UNCORE_HIT          (1 << 8)
1277 #define NHM_OTHER_CORE_HIT_SNP  (1 << 9)
1278 #define NHM_OTHER_CORE_HITM     (1 << 10)
1279                                 /* reserved */
1280 #define NHM_REMOTE_CACHE_FWD    (1 << 12)
1281 #define NHM_REMOTE_DRAM         (1 << 13)
1282 #define NHM_LOCAL_DRAM          (1 << 14)
1283 #define NHM_NON_DRAM            (1 << 15)
1284
1285 #define NHM_LOCAL               (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1286 #define NHM_REMOTE              (NHM_REMOTE_DRAM)
1287
1288 #define NHM_DMND_READ           (NHM_DMND_DATA_RD)
1289 #define NHM_DMND_WRITE          (NHM_DMND_RFO|NHM_DMND_WB)
1290 #define NHM_DMND_PREFETCH       (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1291
1292 #define NHM_L3_HIT      (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1293 #define NHM_L3_MISS     (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1294 #define NHM_L3_ACCESS   (NHM_L3_HIT|NHM_L3_MISS)
1295
1296 static __initconst const u64 nehalem_hw_cache_extra_regs
1297                                 [PERF_COUNT_HW_CACHE_MAX]
1298                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1299                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1300 {
1301  [ C(LL  ) ] = {
1302         [ C(OP_READ) ] = {
1303                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1304                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_L3_MISS,
1305         },
1306         [ C(OP_WRITE) ] = {
1307                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1308                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_L3_MISS,
1309         },
1310         [ C(OP_PREFETCH) ] = {
1311                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1312                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1313         },
1314  },
1315  [ C(NODE) ] = {
1316         [ C(OP_READ) ] = {
1317                 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1318                 [ C(RESULT_MISS)   ] = NHM_DMND_READ|NHM_REMOTE,
1319         },
1320         [ C(OP_WRITE) ] = {
1321                 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1322                 [ C(RESULT_MISS)   ] = NHM_DMND_WRITE|NHM_REMOTE,
1323         },
1324         [ C(OP_PREFETCH) ] = {
1325                 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1326                 [ C(RESULT_MISS)   ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1327         },
1328  },
1329 };
1330
1331 static __initconst const u64 nehalem_hw_cache_event_ids
1332                                 [PERF_COUNT_HW_CACHE_MAX]
1333                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1334                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1335 {
1336  [ C(L1D) ] = {
1337         [ C(OP_READ) ] = {
1338                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
1339                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
1340         },
1341         [ C(OP_WRITE) ] = {
1342                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
1343                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
1344         },
1345         [ C(OP_PREFETCH) ] = {
1346                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
1347                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
1348         },
1349  },
1350  [ C(L1I ) ] = {
1351         [ C(OP_READ) ] = {
1352                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
1353                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
1354         },
1355         [ C(OP_WRITE) ] = {
1356                 [ C(RESULT_ACCESS) ] = -1,
1357                 [ C(RESULT_MISS)   ] = -1,
1358         },
1359         [ C(OP_PREFETCH) ] = {
1360                 [ C(RESULT_ACCESS) ] = 0x0,
1361                 [ C(RESULT_MISS)   ] = 0x0,
1362         },
1363  },
1364  [ C(LL  ) ] = {
1365         [ C(OP_READ) ] = {
1366                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1367                 [ C(RESULT_ACCESS) ] = 0x01b7,
1368                 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1369                 [ C(RESULT_MISS)   ] = 0x01b7,
1370         },
1371         /*
1372          * Use RFO, not WRITEBACK, because a write miss would typically occur
1373          * on RFO.
1374          */
1375         [ C(OP_WRITE) ] = {
1376                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1377                 [ C(RESULT_ACCESS) ] = 0x01b7,
1378                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1379                 [ C(RESULT_MISS)   ] = 0x01b7,
1380         },
1381         [ C(OP_PREFETCH) ] = {
1382                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1383                 [ C(RESULT_ACCESS) ] = 0x01b7,
1384                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1385                 [ C(RESULT_MISS)   ] = 0x01b7,
1386         },
1387  },
1388  [ C(DTLB) ] = {
1389         [ C(OP_READ) ] = {
1390                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
1391                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
1392         },
1393         [ C(OP_WRITE) ] = {
1394                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
1395                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
1396         },
1397         [ C(OP_PREFETCH) ] = {
1398                 [ C(RESULT_ACCESS) ] = 0x0,
1399                 [ C(RESULT_MISS)   ] = 0x0,
1400         },
1401  },
1402  [ C(ITLB) ] = {
1403         [ C(OP_READ) ] = {
1404                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
1405                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
1406         },
1407         [ C(OP_WRITE) ] = {
1408                 [ C(RESULT_ACCESS) ] = -1,
1409                 [ C(RESULT_MISS)   ] = -1,
1410         },
1411         [ C(OP_PREFETCH) ] = {
1412                 [ C(RESULT_ACCESS) ] = -1,
1413                 [ C(RESULT_MISS)   ] = -1,
1414         },
1415  },
1416  [ C(BPU ) ] = {
1417         [ C(OP_READ) ] = {
1418                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1419                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
1420         },
1421         [ C(OP_WRITE) ] = {
1422                 [ C(RESULT_ACCESS) ] = -1,
1423                 [ C(RESULT_MISS)   ] = -1,
1424         },
1425         [ C(OP_PREFETCH) ] = {
1426                 [ C(RESULT_ACCESS) ] = -1,
1427                 [ C(RESULT_MISS)   ] = -1,
1428         },
1429  },
1430  [ C(NODE) ] = {
1431         [ C(OP_READ) ] = {
1432                 [ C(RESULT_ACCESS) ] = 0x01b7,
1433                 [ C(RESULT_MISS)   ] = 0x01b7,
1434         },
1435         [ C(OP_WRITE) ] = {
1436                 [ C(RESULT_ACCESS) ] = 0x01b7,
1437                 [ C(RESULT_MISS)   ] = 0x01b7,
1438         },
1439         [ C(OP_PREFETCH) ] = {
1440                 [ C(RESULT_ACCESS) ] = 0x01b7,
1441                 [ C(RESULT_MISS)   ] = 0x01b7,
1442         },
1443  },
1444 };
1445
1446 static __initconst const u64 core2_hw_cache_event_ids
1447                                 [PERF_COUNT_HW_CACHE_MAX]
1448                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1449                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1450 {
1451  [ C(L1D) ] = {
1452         [ C(OP_READ) ] = {
1453                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
1454                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
1455         },
1456         [ C(OP_WRITE) ] = {
1457                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
1458                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
1459         },
1460         [ C(OP_PREFETCH) ] = {
1461                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
1462                 [ C(RESULT_MISS)   ] = 0,
1463         },
1464  },
1465  [ C(L1I ) ] = {
1466         [ C(OP_READ) ] = {
1467                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
1468                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
1469         },
1470         [ C(OP_WRITE) ] = {
1471                 [ C(RESULT_ACCESS) ] = -1,
1472                 [ C(RESULT_MISS)   ] = -1,
1473         },
1474         [ C(OP_PREFETCH) ] = {
1475                 [ C(RESULT_ACCESS) ] = 0,
1476                 [ C(RESULT_MISS)   ] = 0,
1477         },
1478  },
1479  [ C(LL  ) ] = {
1480         [ C(OP_READ) ] = {
1481                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1482                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1483         },
1484         [ C(OP_WRITE) ] = {
1485                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1486                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1487         },
1488         [ C(OP_PREFETCH) ] = {
1489                 [ C(RESULT_ACCESS) ] = 0,
1490                 [ C(RESULT_MISS)   ] = 0,
1491         },
1492  },
1493  [ C(DTLB) ] = {
1494         [ C(OP_READ) ] = {
1495                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
1496                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
1497         },
1498         [ C(OP_WRITE) ] = {
1499                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
1500                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
1501         },
1502         [ C(OP_PREFETCH) ] = {
1503                 [ C(RESULT_ACCESS) ] = 0,
1504                 [ C(RESULT_MISS)   ] = 0,
1505         },
1506  },
1507  [ C(ITLB) ] = {
1508         [ C(OP_READ) ] = {
1509                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1510                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
1511         },
1512         [ C(OP_WRITE) ] = {
1513                 [ C(RESULT_ACCESS) ] = -1,
1514                 [ C(RESULT_MISS)   ] = -1,
1515         },
1516         [ C(OP_PREFETCH) ] = {
1517                 [ C(RESULT_ACCESS) ] = -1,
1518                 [ C(RESULT_MISS)   ] = -1,
1519         },
1520  },
1521  [ C(BPU ) ] = {
1522         [ C(OP_READ) ] = {
1523                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1524                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1525         },
1526         [ C(OP_WRITE) ] = {
1527                 [ C(RESULT_ACCESS) ] = -1,
1528                 [ C(RESULT_MISS)   ] = -1,
1529         },
1530         [ C(OP_PREFETCH) ] = {
1531                 [ C(RESULT_ACCESS) ] = -1,
1532                 [ C(RESULT_MISS)   ] = -1,
1533         },
1534  },
1535 };
1536
1537 static __initconst const u64 atom_hw_cache_event_ids
1538                                 [PERF_COUNT_HW_CACHE_MAX]
1539                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1540                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1541 {
1542  [ C(L1D) ] = {
1543         [ C(OP_READ) ] = {
1544                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
1545                 [ C(RESULT_MISS)   ] = 0,
1546         },
1547         [ C(OP_WRITE) ] = {
1548                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
1549                 [ C(RESULT_MISS)   ] = 0,
1550         },
1551         [ C(OP_PREFETCH) ] = {
1552                 [ C(RESULT_ACCESS) ] = 0x0,
1553                 [ C(RESULT_MISS)   ] = 0,
1554         },
1555  },
1556  [ C(L1I ) ] = {
1557         [ C(OP_READ) ] = {
1558                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
1559                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
1560         },
1561         [ C(OP_WRITE) ] = {
1562                 [ C(RESULT_ACCESS) ] = -1,
1563                 [ C(RESULT_MISS)   ] = -1,
1564         },
1565         [ C(OP_PREFETCH) ] = {
1566                 [ C(RESULT_ACCESS) ] = 0,
1567                 [ C(RESULT_MISS)   ] = 0,
1568         },
1569  },
1570  [ C(LL  ) ] = {
1571         [ C(OP_READ) ] = {
1572                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
1573                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
1574         },
1575         [ C(OP_WRITE) ] = {
1576                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
1577                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
1578         },
1579         [ C(OP_PREFETCH) ] = {
1580                 [ C(RESULT_ACCESS) ] = 0,
1581                 [ C(RESULT_MISS)   ] = 0,
1582         },
1583  },
1584  [ C(DTLB) ] = {
1585         [ C(OP_READ) ] = {
1586                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
1587                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
1588         },
1589         [ C(OP_WRITE) ] = {
1590                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
1591                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
1592         },
1593         [ C(OP_PREFETCH) ] = {
1594                 [ C(RESULT_ACCESS) ] = 0,
1595                 [ C(RESULT_MISS)   ] = 0,
1596         },
1597  },
1598  [ C(ITLB) ] = {
1599         [ C(OP_READ) ] = {
1600                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
1601                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
1602         },
1603         [ C(OP_WRITE) ] = {
1604                 [ C(RESULT_ACCESS) ] = -1,
1605                 [ C(RESULT_MISS)   ] = -1,
1606         },
1607         [ C(OP_PREFETCH) ] = {
1608                 [ C(RESULT_ACCESS) ] = -1,
1609                 [ C(RESULT_MISS)   ] = -1,
1610         },
1611  },
1612  [ C(BPU ) ] = {
1613         [ C(OP_READ) ] = {
1614                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
1615                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
1616         },
1617         [ C(OP_WRITE) ] = {
1618                 [ C(RESULT_ACCESS) ] = -1,
1619                 [ C(RESULT_MISS)   ] = -1,
1620         },
1621         [ C(OP_PREFETCH) ] = {
1622                 [ C(RESULT_ACCESS) ] = -1,
1623                 [ C(RESULT_MISS)   ] = -1,
1624         },
1625  },
1626 };
1627
1628 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1629 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1630 /* no_alloc_cycles.not_delivered */
1631 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1632                "event=0xca,umask=0x50");
1633 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1634 /* uops_retired.all */
1635 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1636                "event=0xc2,umask=0x10");
1637 /* uops_retired.all */
1638 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1639                "event=0xc2,umask=0x10");
1640
1641 static struct attribute *slm_events_attrs[] = {
1642         EVENT_PTR(td_total_slots_slm),
1643         EVENT_PTR(td_total_slots_scale_slm),
1644         EVENT_PTR(td_fetch_bubbles_slm),
1645         EVENT_PTR(td_fetch_bubbles_scale_slm),
1646         EVENT_PTR(td_slots_issued_slm),
1647         EVENT_PTR(td_slots_retired_slm),
1648         NULL
1649 };
1650
1651 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1652 {
1653         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1654         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1655         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1656         EVENT_EXTRA_END
1657 };
1658
1659 #define SLM_DMND_READ           SNB_DMND_DATA_RD
1660 #define SLM_DMND_WRITE          SNB_DMND_RFO
1661 #define SLM_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
1662
1663 #define SLM_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1664 #define SLM_LLC_ACCESS          SNB_RESP_ANY
1665 #define SLM_LLC_MISS            (SLM_SNP_ANY|SNB_NON_DRAM)
1666
1667 static __initconst const u64 slm_hw_cache_extra_regs
1668                                 [PERF_COUNT_HW_CACHE_MAX]
1669                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1670                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1671 {
1672  [ C(LL  ) ] = {
1673         [ C(OP_READ) ] = {
1674                 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1675                 [ C(RESULT_MISS)   ] = 0,
1676         },
1677         [ C(OP_WRITE) ] = {
1678                 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1679                 [ C(RESULT_MISS)   ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1680         },
1681         [ C(OP_PREFETCH) ] = {
1682                 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1683                 [ C(RESULT_MISS)   ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1684         },
1685  },
1686 };
1687
1688 static __initconst const u64 slm_hw_cache_event_ids
1689                                 [PERF_COUNT_HW_CACHE_MAX]
1690                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1691                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1692 {
1693  [ C(L1D) ] = {
1694         [ C(OP_READ) ] = {
1695                 [ C(RESULT_ACCESS) ] = 0,
1696                 [ C(RESULT_MISS)   ] = 0x0104, /* LD_DCU_MISS */
1697         },
1698         [ C(OP_WRITE) ] = {
1699                 [ C(RESULT_ACCESS) ] = 0,
1700                 [ C(RESULT_MISS)   ] = 0,
1701         },
1702         [ C(OP_PREFETCH) ] = {
1703                 [ C(RESULT_ACCESS) ] = 0,
1704                 [ C(RESULT_MISS)   ] = 0,
1705         },
1706  },
1707  [ C(L1I ) ] = {
1708         [ C(OP_READ) ] = {
1709                 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1710                 [ C(RESULT_MISS)   ] = 0x0280, /* ICACGE.MISSES */
1711         },
1712         [ C(OP_WRITE) ] = {
1713                 [ C(RESULT_ACCESS) ] = -1,
1714                 [ C(RESULT_MISS)   ] = -1,
1715         },
1716         [ C(OP_PREFETCH) ] = {
1717                 [ C(RESULT_ACCESS) ] = 0,
1718                 [ C(RESULT_MISS)   ] = 0,
1719         },
1720  },
1721  [ C(LL  ) ] = {
1722         [ C(OP_READ) ] = {
1723                 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1724                 [ C(RESULT_ACCESS) ] = 0x01b7,
1725                 [ C(RESULT_MISS)   ] = 0,
1726         },
1727         [ C(OP_WRITE) ] = {
1728                 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1729                 [ C(RESULT_ACCESS) ] = 0x01b7,
1730                 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1731                 [ C(RESULT_MISS)   ] = 0x01b7,
1732         },
1733         [ C(OP_PREFETCH) ] = {
1734                 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1735                 [ C(RESULT_ACCESS) ] = 0x01b7,
1736                 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1737                 [ C(RESULT_MISS)   ] = 0x01b7,
1738         },
1739  },
1740  [ C(DTLB) ] = {
1741         [ C(OP_READ) ] = {
1742                 [ C(RESULT_ACCESS) ] = 0,
1743                 [ C(RESULT_MISS)   ] = 0x0804, /* LD_DTLB_MISS */
1744         },
1745         [ C(OP_WRITE) ] = {
1746                 [ C(RESULT_ACCESS) ] = 0,
1747                 [ C(RESULT_MISS)   ] = 0,
1748         },
1749         [ C(OP_PREFETCH) ] = {
1750                 [ C(RESULT_ACCESS) ] = 0,
1751                 [ C(RESULT_MISS)   ] = 0,
1752         },
1753  },
1754  [ C(ITLB) ] = {
1755         [ C(OP_READ) ] = {
1756                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1757                 [ C(RESULT_MISS)   ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1758         },
1759         [ C(OP_WRITE) ] = {
1760                 [ C(RESULT_ACCESS) ] = -1,
1761                 [ C(RESULT_MISS)   ] = -1,
1762         },
1763         [ C(OP_PREFETCH) ] = {
1764                 [ C(RESULT_ACCESS) ] = -1,
1765                 [ C(RESULT_MISS)   ] = -1,
1766         },
1767  },
1768  [ C(BPU ) ] = {
1769         [ C(OP_READ) ] = {
1770                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1771                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1772         },
1773         [ C(OP_WRITE) ] = {
1774                 [ C(RESULT_ACCESS) ] = -1,
1775                 [ C(RESULT_MISS)   ] = -1,
1776         },
1777         [ C(OP_PREFETCH) ] = {
1778                 [ C(RESULT_ACCESS) ] = -1,
1779                 [ C(RESULT_MISS)   ] = -1,
1780         },
1781  },
1782 };
1783
1784 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1785 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1786 /* UOPS_NOT_DELIVERED.ANY */
1787 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1788 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1789 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1790 /* UOPS_RETIRED.ANY */
1791 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1792 /* UOPS_ISSUED.ANY */
1793 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1794
1795 static struct attribute *glm_events_attrs[] = {
1796         EVENT_PTR(td_total_slots_glm),
1797         EVENT_PTR(td_total_slots_scale_glm),
1798         EVENT_PTR(td_fetch_bubbles_glm),
1799         EVENT_PTR(td_recovery_bubbles_glm),
1800         EVENT_PTR(td_slots_issued_glm),
1801         EVENT_PTR(td_slots_retired_glm),
1802         NULL
1803 };
1804
1805 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1806         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1807         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1808         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1809         EVENT_EXTRA_END
1810 };
1811
1812 #define GLM_DEMAND_DATA_RD              BIT_ULL(0)
1813 #define GLM_DEMAND_RFO                  BIT_ULL(1)
1814 #define GLM_ANY_RESPONSE                BIT_ULL(16)
1815 #define GLM_SNP_NONE_OR_MISS            BIT_ULL(33)
1816 #define GLM_DEMAND_READ                 GLM_DEMAND_DATA_RD
1817 #define GLM_DEMAND_WRITE                GLM_DEMAND_RFO
1818 #define GLM_DEMAND_PREFETCH             (SNB_PF_DATA_RD|SNB_PF_RFO)
1819 #define GLM_LLC_ACCESS                  GLM_ANY_RESPONSE
1820 #define GLM_SNP_ANY                     (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1821 #define GLM_LLC_MISS                    (GLM_SNP_ANY|SNB_NON_DRAM)
1822
1823 static __initconst const u64 glm_hw_cache_event_ids
1824                                 [PERF_COUNT_HW_CACHE_MAX]
1825                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1826                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1827         [C(L1D)] = {
1828                 [C(OP_READ)] = {
1829                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1830                         [C(RESULT_MISS)]        = 0x0,
1831                 },
1832                 [C(OP_WRITE)] = {
1833                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1834                         [C(RESULT_MISS)]        = 0x0,
1835                 },
1836                 [C(OP_PREFETCH)] = {
1837                         [C(RESULT_ACCESS)]      = 0x0,
1838                         [C(RESULT_MISS)]        = 0x0,
1839                 },
1840         },
1841         [C(L1I)] = {
1842                 [C(OP_READ)] = {
1843                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1844                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1845                 },
1846                 [C(OP_WRITE)] = {
1847                         [C(RESULT_ACCESS)]      = -1,
1848                         [C(RESULT_MISS)]        = -1,
1849                 },
1850                 [C(OP_PREFETCH)] = {
1851                         [C(RESULT_ACCESS)]      = 0x0,
1852                         [C(RESULT_MISS)]        = 0x0,
1853                 },
1854         },
1855         [C(LL)] = {
1856                 [C(OP_READ)] = {
1857                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1858                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1859                 },
1860                 [C(OP_WRITE)] = {
1861                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1862                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1863                 },
1864                 [C(OP_PREFETCH)] = {
1865                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1866                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1867                 },
1868         },
1869         [C(DTLB)] = {
1870                 [C(OP_READ)] = {
1871                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1872                         [C(RESULT_MISS)]        = 0x0,
1873                 },
1874                 [C(OP_WRITE)] = {
1875                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1876                         [C(RESULT_MISS)]        = 0x0,
1877                 },
1878                 [C(OP_PREFETCH)] = {
1879                         [C(RESULT_ACCESS)]      = 0x0,
1880                         [C(RESULT_MISS)]        = 0x0,
1881                 },
1882         },
1883         [C(ITLB)] = {
1884                 [C(OP_READ)] = {
1885                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
1886                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
1887                 },
1888                 [C(OP_WRITE)] = {
1889                         [C(RESULT_ACCESS)]      = -1,
1890                         [C(RESULT_MISS)]        = -1,
1891                 },
1892                 [C(OP_PREFETCH)] = {
1893                         [C(RESULT_ACCESS)]      = -1,
1894                         [C(RESULT_MISS)]        = -1,
1895                 },
1896         },
1897         [C(BPU)] = {
1898                 [C(OP_READ)] = {
1899                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
1900                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
1901                 },
1902                 [C(OP_WRITE)] = {
1903                         [C(RESULT_ACCESS)]      = -1,
1904                         [C(RESULT_MISS)]        = -1,
1905                 },
1906                 [C(OP_PREFETCH)] = {
1907                         [C(RESULT_ACCESS)]      = -1,
1908                         [C(RESULT_MISS)]        = -1,
1909                 },
1910         },
1911 };
1912
1913 static __initconst const u64 glm_hw_cache_extra_regs
1914                                 [PERF_COUNT_HW_CACHE_MAX]
1915                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1916                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1917         [C(LL)] = {
1918                 [C(OP_READ)] = {
1919                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
1920                                                   GLM_LLC_ACCESS,
1921                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
1922                                                   GLM_LLC_MISS,
1923                 },
1924                 [C(OP_WRITE)] = {
1925                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
1926                                                   GLM_LLC_ACCESS,
1927                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
1928                                                   GLM_LLC_MISS,
1929                 },
1930                 [C(OP_PREFETCH)] = {
1931                         [C(RESULT_ACCESS)]      = GLM_DEMAND_PREFETCH|
1932                                                   GLM_LLC_ACCESS,
1933                         [C(RESULT_MISS)]        = GLM_DEMAND_PREFETCH|
1934                                                   GLM_LLC_MISS,
1935                 },
1936         },
1937 };
1938
1939 static __initconst const u64 glp_hw_cache_event_ids
1940                                 [PERF_COUNT_HW_CACHE_MAX]
1941                                 [PERF_COUNT_HW_CACHE_OP_MAX]
1942                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1943         [C(L1D)] = {
1944                 [C(OP_READ)] = {
1945                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1946                         [C(RESULT_MISS)]        = 0x0,
1947                 },
1948                 [C(OP_WRITE)] = {
1949                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1950                         [C(RESULT_MISS)]        = 0x0,
1951                 },
1952                 [C(OP_PREFETCH)] = {
1953                         [C(RESULT_ACCESS)]      = 0x0,
1954                         [C(RESULT_MISS)]        = 0x0,
1955                 },
1956         },
1957         [C(L1I)] = {
1958                 [C(OP_READ)] = {
1959                         [C(RESULT_ACCESS)]      = 0x0380,       /* ICACHE.ACCESSES */
1960                         [C(RESULT_MISS)]        = 0x0280,       /* ICACHE.MISSES */
1961                 },
1962                 [C(OP_WRITE)] = {
1963                         [C(RESULT_ACCESS)]      = -1,
1964                         [C(RESULT_MISS)]        = -1,
1965                 },
1966                 [C(OP_PREFETCH)] = {
1967                         [C(RESULT_ACCESS)]      = 0x0,
1968                         [C(RESULT_MISS)]        = 0x0,
1969                 },
1970         },
1971         [C(LL)] = {
1972                 [C(OP_READ)] = {
1973                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1974                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1975                 },
1976                 [C(OP_WRITE)] = {
1977                         [C(RESULT_ACCESS)]      = 0x1b7,        /* OFFCORE_RESPONSE */
1978                         [C(RESULT_MISS)]        = 0x1b7,        /* OFFCORE_RESPONSE */
1979                 },
1980                 [C(OP_PREFETCH)] = {
1981                         [C(RESULT_ACCESS)]      = 0x0,
1982                         [C(RESULT_MISS)]        = 0x0,
1983                 },
1984         },
1985         [C(DTLB)] = {
1986                 [C(OP_READ)] = {
1987                         [C(RESULT_ACCESS)]      = 0x81d0,       /* MEM_UOPS_RETIRED.ALL_LOADS */
1988                         [C(RESULT_MISS)]        = 0xe08,        /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1989                 },
1990                 [C(OP_WRITE)] = {
1991                         [C(RESULT_ACCESS)]      = 0x82d0,       /* MEM_UOPS_RETIRED.ALL_STORES */
1992                         [C(RESULT_MISS)]        = 0xe49,        /* DTLB_STORE_MISSES.WALK_COMPLETED */
1993                 },
1994                 [C(OP_PREFETCH)] = {
1995                         [C(RESULT_ACCESS)]      = 0x0,
1996                         [C(RESULT_MISS)]        = 0x0,
1997                 },
1998         },
1999         [C(ITLB)] = {
2000                 [C(OP_READ)] = {
2001                         [C(RESULT_ACCESS)]      = 0x00c0,       /* INST_RETIRED.ANY_P */
2002                         [C(RESULT_MISS)]        = 0x0481,       /* ITLB.MISS */
2003                 },
2004                 [C(OP_WRITE)] = {
2005                         [C(RESULT_ACCESS)]      = -1,
2006                         [C(RESULT_MISS)]        = -1,
2007                 },
2008                 [C(OP_PREFETCH)] = {
2009                         [C(RESULT_ACCESS)]      = -1,
2010                         [C(RESULT_MISS)]        = -1,
2011                 },
2012         },
2013         [C(BPU)] = {
2014                 [C(OP_READ)] = {
2015                         [C(RESULT_ACCESS)]      = 0x00c4,       /* BR_INST_RETIRED.ALL_BRANCHES */
2016                         [C(RESULT_MISS)]        = 0x00c5,       /* BR_MISP_RETIRED.ALL_BRANCHES */
2017                 },
2018                 [C(OP_WRITE)] = {
2019                         [C(RESULT_ACCESS)]      = -1,
2020                         [C(RESULT_MISS)]        = -1,
2021                 },
2022                 [C(OP_PREFETCH)] = {
2023                         [C(RESULT_ACCESS)]      = -1,
2024                         [C(RESULT_MISS)]        = -1,
2025                 },
2026         },
2027 };
2028
2029 static __initconst const u64 glp_hw_cache_extra_regs
2030                                 [PERF_COUNT_HW_CACHE_MAX]
2031                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2032                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2033         [C(LL)] = {
2034                 [C(OP_READ)] = {
2035                         [C(RESULT_ACCESS)]      = GLM_DEMAND_READ|
2036                                                   GLM_LLC_ACCESS,
2037                         [C(RESULT_MISS)]        = GLM_DEMAND_READ|
2038                                                   GLM_LLC_MISS,
2039                 },
2040                 [C(OP_WRITE)] = {
2041                         [C(RESULT_ACCESS)]      = GLM_DEMAND_WRITE|
2042                                                   GLM_LLC_ACCESS,
2043                         [C(RESULT_MISS)]        = GLM_DEMAND_WRITE|
2044                                                   GLM_LLC_MISS,
2045                 },
2046                 [C(OP_PREFETCH)] = {
2047                         [C(RESULT_ACCESS)]      = 0x0,
2048                         [C(RESULT_MISS)]        = 0x0,
2049                 },
2050         },
2051 };
2052
2053 #define TNT_LOCAL_DRAM                  BIT_ULL(26)
2054 #define TNT_DEMAND_READ                 GLM_DEMAND_DATA_RD
2055 #define TNT_DEMAND_WRITE                GLM_DEMAND_RFO
2056 #define TNT_LLC_ACCESS                  GLM_ANY_RESPONSE
2057 #define TNT_SNP_ANY                     (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2058                                          SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2059 #define TNT_LLC_MISS                    (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2060
2061 static __initconst const u64 tnt_hw_cache_extra_regs
2062                                 [PERF_COUNT_HW_CACHE_MAX]
2063                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2064                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2065         [C(LL)] = {
2066                 [C(OP_READ)] = {
2067                         [C(RESULT_ACCESS)]      = TNT_DEMAND_READ|
2068                                                   TNT_LLC_ACCESS,
2069                         [C(RESULT_MISS)]        = TNT_DEMAND_READ|
2070                                                   TNT_LLC_MISS,
2071                 },
2072                 [C(OP_WRITE)] = {
2073                         [C(RESULT_ACCESS)]      = TNT_DEMAND_WRITE|
2074                                                   TNT_LLC_ACCESS,
2075                         [C(RESULT_MISS)]        = TNT_DEMAND_WRITE|
2076                                                   TNT_LLC_MISS,
2077                 },
2078                 [C(OP_PREFETCH)] = {
2079                         [C(RESULT_ACCESS)]      = 0x0,
2080                         [C(RESULT_MISS)]        = 0x0,
2081                 },
2082         },
2083 };
2084
2085 EVENT_ATTR_STR(topdown-fe-bound,       td_fe_bound_tnt,        "event=0x71,umask=0x0");
2086 EVENT_ATTR_STR(topdown-retiring,       td_retiring_tnt,        "event=0xc2,umask=0x0");
2087 EVENT_ATTR_STR(topdown-bad-spec,       td_bad_spec_tnt,        "event=0x73,umask=0x6");
2088 EVENT_ATTR_STR(topdown-be-bound,       td_be_bound_tnt,        "event=0x74,umask=0x0");
2089
2090 static struct attribute *tnt_events_attrs[] = {
2091         EVENT_PTR(td_fe_bound_tnt),
2092         EVENT_PTR(td_retiring_tnt),
2093         EVENT_PTR(td_bad_spec_tnt),
2094         EVENT_PTR(td_be_bound_tnt),
2095         NULL,
2096 };
2097
2098 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2099         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2100         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2101         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2102         EVENT_EXTRA_END
2103 };
2104
2105 EVENT_ATTR_STR(mem-loads,       mem_ld_grt,     "event=0xd0,umask=0x5,ldlat=3");
2106 EVENT_ATTR_STR(mem-stores,      mem_st_grt,     "event=0xd0,umask=0x6");
2107
2108 static struct attribute *grt_mem_attrs[] = {
2109         EVENT_PTR(mem_ld_grt),
2110         EVENT_PTR(mem_st_grt),
2111         NULL
2112 };
2113
2114 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2115         /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2116         INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2117         INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
2118         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2119         EVENT_EXTRA_END
2120 };
2121
2122 #define KNL_OT_L2_HITE          BIT_ULL(19) /* Other Tile L2 Hit */
2123 #define KNL_OT_L2_HITF          BIT_ULL(20) /* Other Tile L2 Hit */
2124 #define KNL_MCDRAM_LOCAL        BIT_ULL(21)
2125 #define KNL_MCDRAM_FAR          BIT_ULL(22)
2126 #define KNL_DDR_LOCAL           BIT_ULL(23)
2127 #define KNL_DDR_FAR             BIT_ULL(24)
2128 #define KNL_DRAM_ANY            (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2129                                     KNL_DDR_LOCAL | KNL_DDR_FAR)
2130 #define KNL_L2_READ             SLM_DMND_READ
2131 #define KNL_L2_WRITE            SLM_DMND_WRITE
2132 #define KNL_L2_PREFETCH         SLM_DMND_PREFETCH
2133 #define KNL_L2_ACCESS           SLM_LLC_ACCESS
2134 #define KNL_L2_MISS             (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2135                                    KNL_DRAM_ANY | SNB_SNP_ANY | \
2136                                                   SNB_NON_DRAM)
2137
2138 static __initconst const u64 knl_hw_cache_extra_regs
2139                                 [PERF_COUNT_HW_CACHE_MAX]
2140                                 [PERF_COUNT_HW_CACHE_OP_MAX]
2141                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2142         [C(LL)] = {
2143                 [C(OP_READ)] = {
2144                         [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2145                         [C(RESULT_MISS)]   = 0,
2146                 },
2147                 [C(OP_WRITE)] = {
2148                         [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2149                         [C(RESULT_MISS)]   = KNL_L2_WRITE | KNL_L2_MISS,
2150                 },
2151                 [C(OP_PREFETCH)] = {
2152                         [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2153                         [C(RESULT_MISS)]   = KNL_L2_PREFETCH | KNL_L2_MISS,
2154                 },
2155         },
2156 };
2157
2158 /*
2159  * Used from PMIs where the LBRs are already disabled.
2160  *
2161  * This function could be called consecutively. It is required to remain in
2162  * disabled state if called consecutively.
2163  *
2164  * During consecutive calls, the same disable value will be written to related
2165  * registers, so the PMU state remains unchanged.
2166  *
2167  * intel_bts events don't coexist with intel PMU's BTS events because of
2168  * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2169  * disabled around intel PMU's event batching etc, only inside the PMI handler.
2170  *
2171  * Avoid PEBS_ENABLE MSR access in PMIs.
2172  * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2173  * It doesn't matter if the PEBS is enabled or not.
2174  * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2175  * access PEBS_ENABLE MSR in disable_all()/enable_all().
2176  * However, there are some cases which may change PEBS status, e.g. PMI
2177  * throttle. The PEBS_ENABLE should be updated where the status changes.
2178  */
2179 static __always_inline void __intel_pmu_disable_all(bool bts)
2180 {
2181         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2182
2183         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2184
2185         if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2186                 intel_pmu_disable_bts();
2187 }
2188
2189 static __always_inline void intel_pmu_disable_all(void)
2190 {
2191         __intel_pmu_disable_all(true);
2192         intel_pmu_pebs_disable_all();
2193         intel_pmu_lbr_disable_all();
2194 }
2195
2196 static void __intel_pmu_enable_all(int added, bool pmi)
2197 {
2198         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2199         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2200
2201         intel_pmu_lbr_enable_all(pmi);
2202
2203         if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2204                 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2205                 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2206         }
2207
2208         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
2209                intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2210
2211         if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2212                 struct perf_event *event =
2213                         cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2214
2215                 if (WARN_ON_ONCE(!event))
2216                         return;
2217
2218                 intel_pmu_enable_bts(event->hw.config);
2219         }
2220 }
2221
2222 static void intel_pmu_enable_all(int added)
2223 {
2224         intel_pmu_pebs_enable_all();
2225         __intel_pmu_enable_all(added, false);
2226 }
2227
2228 static noinline int
2229 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2230                                   unsigned int cnt, unsigned long flags)
2231 {
2232         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2233
2234         intel_pmu_lbr_read();
2235         cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2236
2237         memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2238         intel_pmu_enable_all(0);
2239         local_irq_restore(flags);
2240         return cnt;
2241 }
2242
2243 static int
2244 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2245 {
2246         unsigned long flags;
2247
2248         /* must not have branches... */
2249         local_irq_save(flags);
2250         __intel_pmu_disable_all(false); /* we don't care about BTS */
2251         __intel_pmu_lbr_disable();
2252         /*            ... until here */
2253         return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2254 }
2255
2256 static int
2257 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2258 {
2259         unsigned long flags;
2260
2261         /* must not have branches... */
2262         local_irq_save(flags);
2263         __intel_pmu_disable_all(false); /* we don't care about BTS */
2264         __intel_pmu_arch_lbr_disable();
2265         /*            ... until here */
2266         return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2267 }
2268
2269 /*
2270  * Workaround for:
2271  *   Intel Errata AAK100 (model 26)
2272  *   Intel Errata AAP53  (model 30)
2273  *   Intel Errata BD53   (model 44)
2274  *
2275  * The official story:
2276  *   These chips need to be 'reset' when adding counters by programming the
2277  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2278  *   in sequence on the same PMC or on different PMCs.
2279  *
2280  * In practice it appears some of these events do in fact count, and
2281  * we need to program all 4 events.
2282  */
2283 static void intel_pmu_nhm_workaround(void)
2284 {
2285         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2286         static const unsigned long nhm_magic[4] = {
2287                 0x4300B5,
2288                 0x4300D2,
2289                 0x4300B1,
2290                 0x4300B1
2291         };
2292         struct perf_event *event;
2293         int i;
2294
2295         /*
2296          * The Errata requires below steps:
2297          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2298          * 2) Configure 4 PERFEVTSELx with the magic events and clear
2299          *    the corresponding PMCx;
2300          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2301          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2302          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2303          */
2304
2305         /*
2306          * The real steps we choose are a little different from above.
2307          * A) To reduce MSR operations, we don't run step 1) as they
2308          *    are already cleared before this function is called;
2309          * B) Call x86_perf_event_update to save PMCx before configuring
2310          *    PERFEVTSELx with magic number;
2311          * C) With step 5), we do clear only when the PERFEVTSELx is
2312          *    not used currently.
2313          * D) Call x86_perf_event_set_period to restore PMCx;
2314          */
2315
2316         /* We always operate 4 pairs of PERF Counters */
2317         for (i = 0; i < 4; i++) {
2318                 event = cpuc->events[i];
2319                 if (event)
2320                         static_call(x86_pmu_update)(event);
2321         }
2322
2323         for (i = 0; i < 4; i++) {
2324                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2325                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2326         }
2327
2328         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2329         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2330
2331         for (i = 0; i < 4; i++) {
2332                 event = cpuc->events[i];
2333
2334                 if (event) {
2335                         static_call(x86_pmu_set_period)(event);
2336                         __x86_pmu_enable_event(&event->hw,
2337                                         ARCH_PERFMON_EVENTSEL_ENABLE);
2338                 } else
2339                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2340         }
2341 }
2342
2343 static void intel_pmu_nhm_enable_all(int added)
2344 {
2345         if (added)
2346                 intel_pmu_nhm_workaround();
2347         intel_pmu_enable_all(added);
2348 }
2349
2350 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2351 {
2352         u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2353
2354         if (cpuc->tfa_shadow != val) {
2355                 cpuc->tfa_shadow = val;
2356                 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2357         }
2358 }
2359
2360 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2361 {
2362         /*
2363          * We're going to use PMC3, make sure TFA is set before we touch it.
2364          */
2365         if (cntr == 3)
2366                 intel_set_tfa(cpuc, true);
2367 }
2368
2369 static void intel_tfa_pmu_enable_all(int added)
2370 {
2371         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2372
2373         /*
2374          * If we find PMC3 is no longer used when we enable the PMU, we can
2375          * clear TFA.
2376          */
2377         if (!test_bit(3, cpuc->active_mask))
2378                 intel_set_tfa(cpuc, false);
2379
2380         intel_pmu_enable_all(added);
2381 }
2382
2383 static inline u64 intel_pmu_get_status(void)
2384 {
2385         u64 status;
2386
2387         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2388
2389         return status;
2390 }
2391
2392 static inline void intel_pmu_ack_status(u64 ack)
2393 {
2394         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2395 }
2396
2397 static inline bool event_is_checkpointed(struct perf_event *event)
2398 {
2399         return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2400 }
2401
2402 static inline void intel_set_masks(struct perf_event *event, int idx)
2403 {
2404         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2405
2406         if (event->attr.exclude_host)
2407                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2408         if (event->attr.exclude_guest)
2409                 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2410         if (event_is_checkpointed(event))
2411                 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2412 }
2413
2414 static inline void intel_clear_masks(struct perf_event *event, int idx)
2415 {
2416         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2417
2418         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2419         __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2420         __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2421 }
2422
2423 static void intel_pmu_disable_fixed(struct perf_event *event)
2424 {
2425         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2426         struct hw_perf_event *hwc = &event->hw;
2427         int idx = hwc->idx;
2428         u64 mask;
2429
2430         if (is_topdown_idx(idx)) {
2431                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2432
2433                 /*
2434                  * When there are other active TopDown events,
2435                  * don't disable the fixed counter 3.
2436                  */
2437                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2438                         return;
2439                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2440         }
2441
2442         intel_clear_masks(event, idx);
2443
2444         mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2445         cpuc->fixed_ctrl_val &= ~mask;
2446 }
2447
2448 static void intel_pmu_disable_event(struct perf_event *event)
2449 {
2450         struct hw_perf_event *hwc = &event->hw;
2451         int idx = hwc->idx;
2452
2453         switch (idx) {
2454         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2455                 intel_clear_masks(event, idx);
2456                 x86_pmu_disable_event(event);
2457                 break;
2458         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2459         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2460                 intel_pmu_disable_fixed(event);
2461                 break;
2462         case INTEL_PMC_IDX_FIXED_BTS:
2463                 intel_pmu_disable_bts();
2464                 intel_pmu_drain_bts_buffer();
2465                 return;
2466         case INTEL_PMC_IDX_FIXED_VLBR:
2467                 intel_clear_masks(event, idx);
2468                 break;
2469         default:
2470                 intel_clear_masks(event, idx);
2471                 pr_warn("Failed to disable the event with invalid index %d\n",
2472                         idx);
2473                 return;
2474         }
2475
2476         /*
2477          * Needs to be called after x86_pmu_disable_event,
2478          * so we don't trigger the event without PEBS bit set.
2479          */
2480         if (unlikely(event->attr.precise_ip))
2481                 intel_pmu_pebs_disable(event);
2482 }
2483
2484 static void intel_pmu_assign_event(struct perf_event *event, int idx)
2485 {
2486         if (is_pebs_pt(event))
2487                 perf_report_aux_output_id(event, idx);
2488 }
2489
2490 static void intel_pmu_del_event(struct perf_event *event)
2491 {
2492         if (needs_branch_stack(event))
2493                 intel_pmu_lbr_del(event);
2494         if (event->attr.precise_ip)
2495                 intel_pmu_pebs_del(event);
2496 }
2497
2498 static int icl_set_topdown_event_period(struct perf_event *event)
2499 {
2500         struct hw_perf_event *hwc = &event->hw;
2501         s64 left = local64_read(&hwc->period_left);
2502
2503         /*
2504          * The values in PERF_METRICS MSR are derived from fixed counter 3.
2505          * Software should start both registers, PERF_METRICS and fixed
2506          * counter 3, from zero.
2507          * Clear PERF_METRICS and Fixed counter 3 in initialization.
2508          * After that, both MSRs will be cleared for each read.
2509          * Don't need to clear them again.
2510          */
2511         if (left == x86_pmu.max_period) {
2512                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2513                 wrmsrl(MSR_PERF_METRICS, 0);
2514                 hwc->saved_slots = 0;
2515                 hwc->saved_metric = 0;
2516         }
2517
2518         if ((hwc->saved_slots) && is_slots_event(event)) {
2519                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2520                 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2521         }
2522
2523         perf_event_update_userpage(event);
2524
2525         return 0;
2526 }
2527
2528 static int adl_set_topdown_event_period(struct perf_event *event)
2529 {
2530         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2531
2532         if (pmu->cpu_type != hybrid_big)
2533                 return 0;
2534
2535         return icl_set_topdown_event_period(event);
2536 }
2537
2538 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
2539
2540 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2541 {
2542         u32 val;
2543
2544         /*
2545          * The metric is reported as an 8bit integer fraction
2546          * summing up to 0xff.
2547          * slots-in-metric = (Metric / 0xff) * slots
2548          */
2549         val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2550         return  mul_u64_u32_div(slots, val, 0xff);
2551 }
2552
2553 static u64 icl_get_topdown_value(struct perf_event *event,
2554                                        u64 slots, u64 metrics)
2555 {
2556         int idx = event->hw.idx;
2557         u64 delta;
2558
2559         if (is_metric_idx(idx))
2560                 delta = icl_get_metrics_event_value(metrics, slots, idx);
2561         else
2562                 delta = slots;
2563
2564         return delta;
2565 }
2566
2567 static void __icl_update_topdown_event(struct perf_event *event,
2568                                        u64 slots, u64 metrics,
2569                                        u64 last_slots, u64 last_metrics)
2570 {
2571         u64 delta, last = 0;
2572
2573         delta = icl_get_topdown_value(event, slots, metrics);
2574         if (last_slots)
2575                 last = icl_get_topdown_value(event, last_slots, last_metrics);
2576
2577         /*
2578          * The 8bit integer fraction of metric may be not accurate,
2579          * especially when the changes is very small.
2580          * For example, if only a few bad_spec happens, the fraction
2581          * may be reduced from 1 to 0. If so, the bad_spec event value
2582          * will be 0 which is definitely less than the last value.
2583          * Avoid update event->count for this case.
2584          */
2585         if (delta > last) {
2586                 delta -= last;
2587                 local64_add(delta, &event->count);
2588         }
2589 }
2590
2591 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
2592                                       u64 metrics, int metric_end)
2593 {
2594         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2595         struct perf_event *other;
2596         int idx;
2597
2598         event->hw.saved_slots = slots;
2599         event->hw.saved_metric = metrics;
2600
2601         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2602                 if (!is_topdown_idx(idx))
2603                         continue;
2604                 other = cpuc->events[idx];
2605                 other->hw.saved_slots = slots;
2606                 other->hw.saved_metric = metrics;
2607         }
2608 }
2609
2610 /*
2611  * Update all active Topdown events.
2612  *
2613  * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2614  * modify by a NMI. PMU has to be disabled before calling this function.
2615  */
2616
2617 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end)
2618 {
2619         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2620         struct perf_event *other;
2621         u64 slots, metrics;
2622         bool reset = true;
2623         int idx;
2624
2625         /* read Fixed counter 3 */
2626         rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2627         if (!slots)
2628                 return 0;
2629
2630         /* read PERF_METRICS */
2631         rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2632
2633         for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
2634                 if (!is_topdown_idx(idx))
2635                         continue;
2636                 other = cpuc->events[idx];
2637                 __icl_update_topdown_event(other, slots, metrics,
2638                                            event ? event->hw.saved_slots : 0,
2639                                            event ? event->hw.saved_metric : 0);
2640         }
2641
2642         /*
2643          * Check and update this event, which may have been cleared
2644          * in active_mask e.g. x86_pmu_stop()
2645          */
2646         if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2647                 __icl_update_topdown_event(event, slots, metrics,
2648                                            event->hw.saved_slots,
2649                                            event->hw.saved_metric);
2650
2651                 /*
2652                  * In x86_pmu_stop(), the event is cleared in active_mask first,
2653                  * then drain the delta, which indicates context switch for
2654                  * counting.
2655                  * Save metric and slots for context switch.
2656                  * Don't need to reset the PERF_METRICS and Fixed counter 3.
2657                  * Because the values will be restored in next schedule in.
2658                  */
2659                 update_saved_topdown_regs(event, slots, metrics, metric_end);
2660                 reset = false;
2661         }
2662
2663         if (reset) {
2664                 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2665                 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2666                 wrmsrl(MSR_PERF_METRICS, 0);
2667                 if (event)
2668                         update_saved_topdown_regs(event, 0, 0, metric_end);
2669         }
2670
2671         return slots;
2672 }
2673
2674 static u64 icl_update_topdown_event(struct perf_event *event)
2675 {
2676         return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
2677                                                  x86_pmu.num_topdown_events - 1);
2678 }
2679
2680 static u64 adl_update_topdown_event(struct perf_event *event)
2681 {
2682         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
2683
2684         if (pmu->cpu_type != hybrid_big)
2685                 return 0;
2686
2687         return icl_update_topdown_event(event);
2688 }
2689
2690 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, x86_perf_event_update);
2691
2692 static void intel_pmu_read_topdown_event(struct perf_event *event)
2693 {
2694         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2695
2696         /* Only need to call update_topdown_event() once for group read. */
2697         if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2698             !is_slots_event(event))
2699                 return;
2700
2701         perf_pmu_disable(event->pmu);
2702         static_call(intel_pmu_update_topdown_event)(event);
2703         perf_pmu_enable(event->pmu);
2704 }
2705
2706 static void intel_pmu_read_event(struct perf_event *event)
2707 {
2708         if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2709                 intel_pmu_auto_reload_read(event);
2710         else if (is_topdown_count(event))
2711                 intel_pmu_read_topdown_event(event);
2712         else
2713                 x86_perf_event_update(event);
2714 }
2715
2716 static void intel_pmu_enable_fixed(struct perf_event *event)
2717 {
2718         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2719         struct hw_perf_event *hwc = &event->hw;
2720         u64 mask, bits = 0;
2721         int idx = hwc->idx;
2722
2723         if (is_topdown_idx(idx)) {
2724                 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2725                 /*
2726                  * When there are other active TopDown events,
2727                  * don't enable the fixed counter 3 again.
2728                  */
2729                 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2730                         return;
2731
2732                 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2733         }
2734
2735         intel_set_masks(event, idx);
2736
2737         /*
2738          * Enable IRQ generation (0x8), if not PEBS,
2739          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2740          * if requested:
2741          */
2742         if (!event->attr.precise_ip)
2743                 bits |= 0x8;
2744         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2745                 bits |= 0x2;
2746         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2747                 bits |= 0x1;
2748
2749         /*
2750          * ANY bit is supported in v3 and up
2751          */
2752         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2753                 bits |= 0x4;
2754
2755         idx -= INTEL_PMC_IDX_FIXED;
2756         bits <<= (idx * 4);
2757         mask = 0xfULL << (idx * 4);
2758
2759         if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2760                 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2761                 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2762         }
2763
2764         cpuc->fixed_ctrl_val &= ~mask;
2765         cpuc->fixed_ctrl_val |= bits;
2766 }
2767
2768 static void intel_pmu_enable_event(struct perf_event *event)
2769 {
2770         struct hw_perf_event *hwc = &event->hw;
2771         int idx = hwc->idx;
2772
2773         if (unlikely(event->attr.precise_ip))
2774                 intel_pmu_pebs_enable(event);
2775
2776         switch (idx) {
2777         case 0 ... INTEL_PMC_IDX_FIXED - 1:
2778                 intel_set_masks(event, idx);
2779                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2780                 break;
2781         case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2782         case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2783                 intel_pmu_enable_fixed(event);
2784                 break;
2785         case INTEL_PMC_IDX_FIXED_BTS:
2786                 if (!__this_cpu_read(cpu_hw_events.enabled))
2787                         return;
2788                 intel_pmu_enable_bts(hwc->config);
2789                 break;
2790         case INTEL_PMC_IDX_FIXED_VLBR:
2791                 intel_set_masks(event, idx);
2792                 break;
2793         default:
2794                 pr_warn("Failed to enable the event with invalid index %d\n",
2795                         idx);
2796         }
2797 }
2798
2799 static void intel_pmu_add_event(struct perf_event *event)
2800 {
2801         if (event->attr.precise_ip)
2802                 intel_pmu_pebs_add(event);
2803         if (needs_branch_stack(event))
2804                 intel_pmu_lbr_add(event);
2805 }
2806
2807 /*
2808  * Save and restart an expired event. Called by NMI contexts,
2809  * so it has to be careful about preempting normal event ops:
2810  */
2811 int intel_pmu_save_and_restart(struct perf_event *event)
2812 {
2813         static_call(x86_pmu_update)(event);
2814         /*
2815          * For a checkpointed counter always reset back to 0.  This
2816          * avoids a situation where the counter overflows, aborts the
2817          * transaction and is then set back to shortly before the
2818          * overflow, and overflows and aborts again.
2819          */
2820         if (unlikely(event_is_checkpointed(event))) {
2821                 /* No race with NMIs because the counter should not be armed */
2822                 wrmsrl(event->hw.event_base, 0);
2823                 local64_set(&event->hw.prev_count, 0);
2824         }
2825         return static_call(x86_pmu_set_period)(event);
2826 }
2827
2828 static int intel_pmu_set_period(struct perf_event *event)
2829 {
2830         if (unlikely(is_topdown_count(event)))
2831                 return static_call(intel_pmu_set_topdown_event_period)(event);
2832
2833         return x86_perf_event_set_period(event);
2834 }
2835
2836 static u64 intel_pmu_update(struct perf_event *event)
2837 {
2838         if (unlikely(is_topdown_count(event)))
2839                 return static_call(intel_pmu_update_topdown_event)(event);
2840
2841         return x86_perf_event_update(event);
2842 }
2843
2844 static void intel_pmu_reset(void)
2845 {
2846         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2847         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2848         int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2849         int num_counters = hybrid(cpuc->pmu, num_counters);
2850         unsigned long flags;
2851         int idx;
2852
2853         if (!num_counters)
2854                 return;
2855
2856         local_irq_save(flags);
2857
2858         pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2859
2860         for (idx = 0; idx < num_counters; idx++) {
2861                 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2862                 wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
2863         }
2864         for (idx = 0; idx < num_counters_fixed; idx++) {
2865                 if (fixed_counter_disabled(idx, cpuc->pmu))
2866                         continue;
2867                 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2868         }
2869
2870         if (ds)
2871                 ds->bts_index = ds->bts_buffer_base;
2872
2873         /* Ack all overflows and disable fixed counters */
2874         if (x86_pmu.version >= 2) {
2875                 intel_pmu_ack_status(intel_pmu_get_status());
2876                 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2877         }
2878
2879         /* Reset LBRs and LBR freezing */
2880         if (x86_pmu.lbr_nr) {
2881                 update_debugctlmsr(get_debugctlmsr() &
2882                         ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2883         }
2884
2885         local_irq_restore(flags);
2886 }
2887
2888 /*
2889  * We may be running with guest PEBS events created by KVM, and the
2890  * PEBS records are logged into the guest's DS and invisible to host.
2891  *
2892  * In the case of guest PEBS overflow, we only trigger a fake event
2893  * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
2894  * The guest will then vm-entry and check the guest DS area to read
2895  * the guest PEBS records.
2896  *
2897  * The contents and other behavior of the guest event do not matter.
2898  */
2899 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
2900                                       struct perf_sample_data *data)
2901 {
2902         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2903         u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
2904         struct perf_event *event = NULL;
2905         int bit;
2906
2907         if (!unlikely(perf_guest_state()))
2908                 return;
2909
2910         if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
2911             !guest_pebs_idxs)
2912                 return;
2913
2914         for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs,
2915                          INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed) {
2916                 event = cpuc->events[bit];
2917                 if (!event->attr.precise_ip)
2918                         continue;
2919
2920                 perf_sample_data_init(data, 0, event->hw.last_period);
2921                 if (perf_event_overflow(event, data, regs))
2922                         x86_pmu_stop(event, 0);
2923
2924                 /* Inject one fake event is enough. */
2925                 break;
2926         }
2927 }
2928
2929 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2930 {
2931         struct perf_sample_data data;
2932         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2933         int bit;
2934         int handled = 0;
2935         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2936
2937         inc_irq_stat(apic_perf_irqs);
2938
2939         /*
2940          * Ignore a range of extra bits in status that do not indicate
2941          * overflow by themselves.
2942          */
2943         status &= ~(GLOBAL_STATUS_COND_CHG |
2944                     GLOBAL_STATUS_ASIF |
2945                     GLOBAL_STATUS_LBRS_FROZEN);
2946         if (!status)
2947                 return 0;
2948         /*
2949          * In case multiple PEBS events are sampled at the same time,
2950          * it is possible to have GLOBAL_STATUS bit 62 set indicating
2951          * PEBS buffer overflow and also seeing at most 3 PEBS counters
2952          * having their bits set in the status register. This is a sign
2953          * that there was at least one PEBS record pending at the time
2954          * of the PMU interrupt. PEBS counters must only be processed
2955          * via the drain_pebs() calls and not via the regular sample
2956          * processing loop coming after that the function, otherwise
2957          * phony regular samples may be generated in the sampling buffer
2958          * not marked with the EXACT tag. Another possibility is to have
2959          * one PEBS event and at least one non-PEBS event which overflows
2960          * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2961          * not be set, yet the overflow status bit for the PEBS counter will
2962          * be on Skylake.
2963          *
2964          * To avoid this problem, we systematically ignore the PEBS-enabled
2965          * counters from the GLOBAL_STATUS mask and we always process PEBS
2966          * events via drain_pebs().
2967          */
2968         status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
2969
2970         /*
2971          * PEBS overflow sets bit 62 in the global status register
2972          */
2973         if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2974                 u64 pebs_enabled = cpuc->pebs_enabled;
2975
2976                 handled++;
2977                 x86_pmu_handle_guest_pebs(regs, &data);
2978                 x86_pmu.drain_pebs(regs, &data);
2979                 status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2980
2981                 /*
2982                  * PMI throttle may be triggered, which stops the PEBS event.
2983                  * Although cpuc->pebs_enabled is updated accordingly, the
2984                  * MSR_IA32_PEBS_ENABLE is not updated. Because the
2985                  * cpuc->enabled has been forced to 0 in PMI.
2986                  * Update the MSR if pebs_enabled is changed.
2987                  */
2988                 if (pebs_enabled != cpuc->pebs_enabled)
2989                         wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2990         }
2991
2992         /*
2993          * Intel PT
2994          */
2995         if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2996                 handled++;
2997                 if (!perf_guest_handle_intel_pt_intr())
2998                         intel_pt_interrupt();
2999         }
3000
3001         /*
3002          * Intel Perf metrics
3003          */
3004         if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3005                 handled++;
3006                 static_call(intel_pmu_update_topdown_event)(NULL);
3007         }
3008
3009         /*
3010          * Checkpointed counters can lead to 'spurious' PMIs because the
3011          * rollback caused by the PMI will have cleared the overflow status
3012          * bit. Therefore always force probe these counters.
3013          */
3014         status |= cpuc->intel_cp_status;
3015
3016         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3017                 struct perf_event *event = cpuc->events[bit];
3018
3019                 handled++;
3020
3021                 if (!test_bit(bit, cpuc->active_mask))
3022                         continue;
3023
3024                 if (!intel_pmu_save_and_restart(event))
3025                         continue;
3026
3027                 perf_sample_data_init(&data, 0, event->hw.last_period);
3028
3029                 if (has_branch_stack(event)) {
3030                         data.br_stack = &cpuc->lbr_stack;
3031                         data.sample_flags |= PERF_SAMPLE_BRANCH_STACK;
3032                 }
3033
3034                 if (perf_event_overflow(event, &data, regs))
3035                         x86_pmu_stop(event, 0);
3036         }
3037
3038         return handled;
3039 }
3040
3041 /*
3042  * This handler is triggered by the local APIC, so the APIC IRQ handling
3043  * rules apply:
3044  */
3045 static int intel_pmu_handle_irq(struct pt_regs *regs)
3046 {
3047         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3048         bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3049         bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3050         int loops;
3051         u64 status;
3052         int handled;
3053         int pmu_enabled;
3054
3055         /*
3056          * Save the PMU state.
3057          * It needs to be restored when leaving the handler.
3058          */
3059         pmu_enabled = cpuc->enabled;
3060         /*
3061          * In general, the early ACK is only applied for old platforms.
3062          * For the big core starts from Haswell, the late ACK should be
3063          * applied.
3064          * For the small core after Tremont, we have to do the ACK right
3065          * before re-enabling counters, which is in the middle of the
3066          * NMI handler.
3067          */
3068         if (!late_ack && !mid_ack)
3069                 apic_write(APIC_LVTPC, APIC_DM_NMI);
3070         intel_bts_disable_local();
3071         cpuc->enabled = 0;
3072         __intel_pmu_disable_all(true);
3073         handled = intel_pmu_drain_bts_buffer();
3074         handled += intel_bts_interrupt();
3075         status = intel_pmu_get_status();
3076         if (!status)
3077                 goto done;
3078
3079         loops = 0;
3080 again:
3081         intel_pmu_lbr_read();
3082         intel_pmu_ack_status(status);
3083         if (++loops > 100) {
3084                 static bool warned;
3085
3086                 if (!warned) {
3087                         WARN(1, "perfevents: irq loop stuck!\n");
3088                         perf_event_print_debug();
3089                         warned = true;
3090                 }
3091                 intel_pmu_reset();
3092                 goto done;
3093         }
3094
3095         handled += handle_pmi_common(regs, status);
3096
3097         /*
3098          * Repeat if there is more work to be done:
3099          */
3100         status = intel_pmu_get_status();
3101         if (status)
3102                 goto again;
3103
3104 done:
3105         if (mid_ack)
3106                 apic_write(APIC_LVTPC, APIC_DM_NMI);
3107         /* Only restore PMU state when it's active. See x86_pmu_disable(). */
3108         cpuc->enabled = pmu_enabled;
3109         if (pmu_enabled)
3110                 __intel_pmu_enable_all(0, true);
3111         intel_bts_enable_local();
3112
3113         /*
3114          * Only unmask the NMI after the overflow counters
3115          * have been reset. This avoids spurious NMIs on
3116          * Haswell CPUs.
3117          */
3118         if (late_ack)
3119                 apic_write(APIC_LVTPC, APIC_DM_NMI);
3120         return handled;
3121 }
3122
3123 static struct event_constraint *
3124 intel_bts_constraints(struct perf_event *event)
3125 {
3126         if (unlikely(intel_pmu_has_bts(event)))
3127                 return &bts_constraint;
3128
3129         return NULL;
3130 }
3131
3132 /*
3133  * Note: matches a fake event, like Fixed2.
3134  */
3135 static struct event_constraint *
3136 intel_vlbr_constraints(struct perf_event *event)
3137 {
3138         struct event_constraint *c = &vlbr_constraint;
3139
3140         if (unlikely(constraint_match(c, event->hw.config))) {
3141                 event->hw.flags |= c->flags;
3142                 return c;
3143         }
3144
3145         return NULL;
3146 }
3147
3148 static int intel_alt_er(struct cpu_hw_events *cpuc,
3149                         int idx, u64 config)
3150 {
3151         struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
3152         int alt_idx = idx;
3153
3154         if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
3155                 return idx;
3156
3157         if (idx == EXTRA_REG_RSP_0)
3158                 alt_idx = EXTRA_REG_RSP_1;
3159
3160         if (idx == EXTRA_REG_RSP_1)
3161                 alt_idx = EXTRA_REG_RSP_0;
3162
3163         if (config & ~extra_regs[alt_idx].valid_mask)
3164                 return idx;
3165
3166         return alt_idx;
3167 }
3168
3169 static void intel_fixup_er(struct perf_event *event, int idx)
3170 {
3171         struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
3172         event->hw.extra_reg.idx = idx;
3173
3174         if (idx == EXTRA_REG_RSP_0) {
3175                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3176                 event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event;
3177                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
3178         } else if (idx == EXTRA_REG_RSP_1) {
3179                 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
3180                 event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event;
3181                 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
3182         }
3183 }
3184
3185 /*
3186  * manage allocation of shared extra msr for certain events
3187  *
3188  * sharing can be:
3189  * per-cpu: to be shared between the various events on a single PMU
3190  * per-core: per-cpu + shared by HT threads
3191  */
3192 static struct event_constraint *
3193 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
3194                                    struct perf_event *event,
3195                                    struct hw_perf_event_extra *reg)
3196 {
3197         struct event_constraint *c = &emptyconstraint;
3198         struct er_account *era;
3199         unsigned long flags;
3200         int idx = reg->idx;
3201
3202         /*
3203          * reg->alloc can be set due to existing state, so for fake cpuc we
3204          * need to ignore this, otherwise we might fail to allocate proper fake
3205          * state for this extra reg constraint. Also see the comment below.
3206          */
3207         if (reg->alloc && !cpuc->is_fake)
3208                 return NULL; /* call x86_get_event_constraint() */
3209
3210 again:
3211         era = &cpuc->shared_regs->regs[idx];
3212         /*
3213          * we use spin_lock_irqsave() to avoid lockdep issues when
3214          * passing a fake cpuc
3215          */
3216         raw_spin_lock_irqsave(&era->lock, flags);
3217
3218         if (!atomic_read(&era->ref) || era->config == reg->config) {
3219
3220                 /*
3221                  * If its a fake cpuc -- as per validate_{group,event}() we
3222                  * shouldn't touch event state and we can avoid doing so
3223                  * since both will only call get_event_constraints() once
3224                  * on each event, this avoids the need for reg->alloc.
3225                  *
3226                  * Not doing the ER fixup will only result in era->reg being
3227                  * wrong, but since we won't actually try and program hardware
3228                  * this isn't a problem either.
3229                  */
3230                 if (!cpuc->is_fake) {
3231                         if (idx != reg->idx)
3232                                 intel_fixup_er(event, idx);
3233
3234                         /*
3235                          * x86_schedule_events() can call get_event_constraints()
3236                          * multiple times on events in the case of incremental
3237                          * scheduling(). reg->alloc ensures we only do the ER
3238                          * allocation once.
3239                          */
3240                         reg->alloc = 1;
3241                 }
3242
3243                 /* lock in msr value */
3244                 era->config = reg->config;
3245                 era->reg = reg->reg;
3246
3247                 /* one more user */
3248                 atomic_inc(&era->ref);
3249
3250                 /*
3251                  * need to call x86_get_event_constraint()
3252                  * to check if associated event has constraints
3253                  */
3254                 c = NULL;
3255         } else {
3256                 idx = intel_alt_er(cpuc, idx, reg->config);
3257                 if (idx != reg->idx) {
3258                         raw_spin_unlock_irqrestore(&era->lock, flags);
3259                         goto again;
3260                 }
3261         }
3262         raw_spin_unlock_irqrestore(&era->lock, flags);
3263
3264         return c;
3265 }
3266
3267 static void
3268 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3269                                    struct hw_perf_event_extra *reg)
3270 {
3271         struct er_account *era;
3272
3273         /*
3274          * Only put constraint if extra reg was actually allocated. Also takes
3275          * care of event which do not use an extra shared reg.
3276          *
3277          * Also, if this is a fake cpuc we shouldn't touch any event state
3278          * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3279          * either since it'll be thrown out.
3280          */
3281         if (!reg->alloc || cpuc->is_fake)
3282                 return;
3283
3284         era = &cpuc->shared_regs->regs[reg->idx];
3285
3286         /* one fewer user */
3287         atomic_dec(&era->ref);
3288
3289         /* allocate again next time */
3290         reg->alloc = 0;
3291 }
3292
3293 static struct event_constraint *
3294 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3295                               struct perf_event *event)
3296 {
3297         struct event_constraint *c = NULL, *d;
3298         struct hw_perf_event_extra *xreg, *breg;
3299
3300         xreg = &event->hw.extra_reg;
3301         if (xreg->idx != EXTRA_REG_NONE) {
3302                 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3303                 if (c == &emptyconstraint)
3304                         return c;
3305         }
3306         breg = &event->hw.branch_reg;
3307         if (breg->idx != EXTRA_REG_NONE) {
3308                 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3309                 if (d == &emptyconstraint) {
3310                         __intel_shared_reg_put_constraints(cpuc, xreg);
3311                         c = d;
3312                 }
3313         }
3314         return c;
3315 }
3316
3317 struct event_constraint *
3318 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3319                           struct perf_event *event)
3320 {
3321         struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
3322         struct event_constraint *c;
3323
3324         if (event_constraints) {
3325                 for_each_event_constraint(c, event_constraints) {
3326                         if (constraint_match(c, event->hw.config)) {
3327                                 event->hw.flags |= c->flags;
3328                                 return c;
3329                         }
3330                 }
3331         }
3332
3333         return &hybrid_var(cpuc->pmu, unconstrained);
3334 }
3335
3336 static struct event_constraint *
3337 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3338                             struct perf_event *event)
3339 {
3340         struct event_constraint *c;
3341
3342         c = intel_vlbr_constraints(event);
3343         if (c)
3344                 return c;
3345
3346         c = intel_bts_constraints(event);
3347         if (c)
3348                 return c;
3349
3350         c = intel_shared_regs_constraints(cpuc, event);
3351         if (c)
3352                 return c;
3353
3354         c = intel_pebs_constraints(event);
3355         if (c)
3356                 return c;
3357
3358         return x86_get_event_constraints(cpuc, idx, event);
3359 }
3360
3361 static void
3362 intel_start_scheduling(struct cpu_hw_events *cpuc)
3363 {
3364         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3365         struct intel_excl_states *xl;
3366         int tid = cpuc->excl_thread_id;
3367
3368         /*
3369          * nothing needed if in group validation mode
3370          */
3371         if (cpuc->is_fake || !is_ht_workaround_enabled())
3372                 return;
3373
3374         /*
3375          * no exclusion needed
3376          */
3377         if (WARN_ON_ONCE(!excl_cntrs))
3378                 return;
3379
3380         xl = &excl_cntrs->states[tid];
3381
3382         xl->sched_started = true;
3383         /*
3384          * lock shared state until we are done scheduling
3385          * in stop_event_scheduling()
3386          * makes scheduling appear as a transaction
3387          */
3388         raw_spin_lock(&excl_cntrs->lock);
3389 }
3390
3391 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3392 {
3393         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3394         struct event_constraint *c = cpuc->event_constraint[idx];
3395         struct intel_excl_states *xl;
3396         int tid = cpuc->excl_thread_id;
3397
3398         if (cpuc->is_fake || !is_ht_workaround_enabled())
3399                 return;
3400
3401         if (WARN_ON_ONCE(!excl_cntrs))
3402                 return;
3403
3404         if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3405                 return;
3406
3407         xl = &excl_cntrs->states[tid];
3408
3409         lockdep_assert_held(&excl_cntrs->lock);
3410
3411         if (c->flags & PERF_X86_EVENT_EXCL)
3412                 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3413         else
3414                 xl->state[cntr] = INTEL_EXCL_SHARED;
3415 }
3416
3417 static void
3418 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3419 {
3420         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3421         struct intel_excl_states *xl;
3422         int tid = cpuc->excl_thread_id;
3423
3424         /*
3425          * nothing needed if in group validation mode
3426          */
3427         if (cpuc->is_fake || !is_ht_workaround_enabled())
3428                 return;
3429         /*
3430          * no exclusion needed
3431          */
3432         if (WARN_ON_ONCE(!excl_cntrs))
3433                 return;
3434
3435         xl = &excl_cntrs->states[tid];
3436
3437         xl->sched_started = false;
3438         /*
3439          * release shared state lock (acquired in intel_start_scheduling())
3440          */
3441         raw_spin_unlock(&excl_cntrs->lock);
3442 }
3443
3444 static struct event_constraint *
3445 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3446 {
3447         WARN_ON_ONCE(!cpuc->constraint_list);
3448
3449         if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3450                 struct event_constraint *cx;
3451
3452                 /*
3453                  * grab pre-allocated constraint entry
3454                  */
3455                 cx = &cpuc->constraint_list[idx];
3456
3457                 /*
3458                  * initialize dynamic constraint
3459                  * with static constraint
3460                  */
3461                 *cx = *c;
3462
3463                 /*
3464                  * mark constraint as dynamic
3465                  */
3466                 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3467                 c = cx;
3468         }
3469
3470         return c;
3471 }
3472
3473 static struct event_constraint *
3474 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3475                            int idx, struct event_constraint *c)
3476 {
3477         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3478         struct intel_excl_states *xlo;
3479         int tid = cpuc->excl_thread_id;
3480         int is_excl, i, w;
3481
3482         /*
3483          * validating a group does not require
3484          * enforcing cross-thread  exclusion
3485          */
3486         if (cpuc->is_fake || !is_ht_workaround_enabled())
3487                 return c;
3488
3489         /*
3490          * no exclusion needed
3491          */
3492         if (WARN_ON_ONCE(!excl_cntrs))
3493                 return c;
3494
3495         /*
3496          * because we modify the constraint, we need
3497          * to make a copy. Static constraints come
3498          * from static const tables.
3499          *
3500          * only needed when constraint has not yet
3501          * been cloned (marked dynamic)
3502          */
3503         c = dyn_constraint(cpuc, c, idx);
3504
3505         /*
3506          * From here on, the constraint is dynamic.
3507          * Either it was just allocated above, or it
3508          * was allocated during a earlier invocation
3509          * of this function
3510          */
3511
3512         /*
3513          * state of sibling HT
3514          */
3515         xlo = &excl_cntrs->states[tid ^ 1];
3516
3517         /*
3518          * event requires exclusive counter access
3519          * across HT threads
3520          */
3521         is_excl = c->flags & PERF_X86_EVENT_EXCL;
3522         if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3523                 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3524                 if (!cpuc->n_excl++)
3525                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3526         }
3527
3528         /*
3529          * Modify static constraint with current dynamic
3530          * state of thread
3531          *
3532          * EXCLUSIVE: sibling counter measuring exclusive event
3533          * SHARED   : sibling counter measuring non-exclusive event
3534          * UNUSED   : sibling counter unused
3535          */
3536         w = c->weight;
3537         for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3538                 /*
3539                  * exclusive event in sibling counter
3540                  * our corresponding counter cannot be used
3541                  * regardless of our event
3542                  */
3543                 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3544                         __clear_bit(i, c->idxmsk);
3545                         w--;
3546                         continue;
3547                 }
3548                 /*
3549                  * if measuring an exclusive event, sibling
3550                  * measuring non-exclusive, then counter cannot
3551                  * be used
3552                  */
3553                 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3554                         __clear_bit(i, c->idxmsk);
3555                         w--;
3556                         continue;
3557                 }
3558         }
3559
3560         /*
3561          * if we return an empty mask, then switch
3562          * back to static empty constraint to avoid
3563          * the cost of freeing later on
3564          */
3565         if (!w)
3566                 c = &emptyconstraint;
3567
3568         c->weight = w;
3569
3570         return c;
3571 }
3572
3573 static struct event_constraint *
3574 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3575                             struct perf_event *event)
3576 {
3577         struct event_constraint *c1, *c2;
3578
3579         c1 = cpuc->event_constraint[idx];
3580
3581         /*
3582          * first time only
3583          * - static constraint: no change across incremental scheduling calls
3584          * - dynamic constraint: handled by intel_get_excl_constraints()
3585          */
3586         c2 = __intel_get_event_constraints(cpuc, idx, event);
3587         if (c1) {
3588                 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3589                 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3590                 c1->weight = c2->weight;
3591                 c2 = c1;
3592         }
3593
3594         if (cpuc->excl_cntrs)
3595                 return intel_get_excl_constraints(cpuc, event, idx, c2);
3596
3597         return c2;
3598 }
3599
3600 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3601                 struct perf_event *event)
3602 {
3603         struct hw_perf_event *hwc = &event->hw;
3604         struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3605         int tid = cpuc->excl_thread_id;
3606         struct intel_excl_states *xl;
3607
3608         /*
3609          * nothing needed if in group validation mode
3610          */
3611         if (cpuc->is_fake)
3612                 return;
3613
3614         if (WARN_ON_ONCE(!excl_cntrs))
3615                 return;
3616
3617         if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3618                 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3619                 if (!--cpuc->n_excl)
3620                         WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3621         }
3622
3623         /*
3624          * If event was actually assigned, then mark the counter state as
3625          * unused now.
3626          */
3627         if (hwc->idx >= 0) {
3628                 xl = &excl_cntrs->states[tid];
3629
3630                 /*
3631                  * put_constraint may be called from x86_schedule_events()
3632                  * which already has the lock held so here make locking
3633                  * conditional.
3634                  */
3635                 if (!xl->sched_started)
3636                         raw_spin_lock(&excl_cntrs->lock);
3637
3638                 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3639
3640                 if (!xl->sched_started)
3641                         raw_spin_unlock(&excl_cntrs->lock);
3642         }
3643 }
3644
3645 static void
3646 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3647                                         struct perf_event *event)
3648 {
3649         struct hw_perf_event_extra *reg;
3650
3651         reg = &event->hw.extra_reg;
3652         if (reg->idx != EXTRA_REG_NONE)
3653                 __intel_shared_reg_put_constraints(cpuc, reg);
3654
3655         reg = &event->hw.branch_reg;
3656         if (reg->idx != EXTRA_REG_NONE)
3657                 __intel_shared_reg_put_constraints(cpuc, reg);
3658 }
3659
3660 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3661                                         struct perf_event *event)
3662 {
3663         intel_put_shared_regs_event_constraints(cpuc, event);
3664
3665         /*
3666          * is PMU has exclusive counter restrictions, then
3667          * all events are subject to and must call the
3668          * put_excl_constraints() routine
3669          */
3670         if (cpuc->excl_cntrs)
3671                 intel_put_excl_constraints(cpuc, event);
3672 }
3673
3674 static void intel_pebs_aliases_core2(struct perf_event *event)
3675 {
3676         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3677                 /*
3678                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3679                  * (0x003c) so that we can use it with PEBS.
3680                  *
3681                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3682                  * PEBS capable. However we can use INST_RETIRED.ANY_P
3683                  * (0x00c0), which is a PEBS capable event, to get the same
3684                  * count.
3685                  *
3686                  * INST_RETIRED.ANY_P counts the number of cycles that retires
3687                  * CNTMASK instructions. By setting CNTMASK to a value (16)
3688                  * larger than the maximum number of instructions that can be
3689                  * retired per cycle (4) and then inverting the condition, we
3690                  * count all cycles that retire 16 or less instructions, which
3691                  * is every cycle.
3692                  *
3693                  * Thereby we gain a PEBS capable cycle counter.
3694                  */
3695                 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3696
3697                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3698                 event->hw.config = alt_config;
3699         }
3700 }
3701
3702 static void intel_pebs_aliases_snb(struct perf_event *event)
3703 {
3704         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3705                 /*
3706                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3707                  * (0x003c) so that we can use it with PEBS.
3708                  *
3709                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3710                  * PEBS capable. However we can use UOPS_RETIRED.ALL
3711                  * (0x01c2), which is a PEBS capable event, to get the same
3712                  * count.
3713                  *
3714                  * UOPS_RETIRED.ALL counts the number of cycles that retires
3715                  * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3716                  * larger than the maximum number of micro-ops that can be
3717                  * retired per cycle (4) and then inverting the condition, we
3718                  * count all cycles that retire 16 or less micro-ops, which
3719                  * is every cycle.
3720                  *
3721                  * Thereby we gain a PEBS capable cycle counter.
3722                  */
3723                 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3724
3725                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3726                 event->hw.config = alt_config;
3727         }
3728 }
3729
3730 static void intel_pebs_aliases_precdist(struct perf_event *event)
3731 {
3732         if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3733                 /*
3734                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3735                  * (0x003c) so that we can use it with PEBS.
3736                  *
3737                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3738                  * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3739                  * (0x01c0), which is a PEBS capable event, to get the same
3740                  * count.
3741                  *
3742                  * The PREC_DIST event has special support to minimize sample
3743                  * shadowing effects. One drawback is that it can be
3744                  * only programmed on counter 1, but that seems like an
3745                  * acceptable trade off.
3746                  */
3747                 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3748
3749                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3750                 event->hw.config = alt_config;
3751         }
3752 }
3753
3754 static void intel_pebs_aliases_ivb(struct perf_event *event)
3755 {
3756         if (event->attr.precise_ip < 3)
3757                 return intel_pebs_aliases_snb(event);
3758         return intel_pebs_aliases_precdist(event);
3759 }
3760
3761 static void intel_pebs_aliases_skl(struct perf_event *event)
3762 {
3763         if (event->attr.precise_ip < 3)
3764                 return intel_pebs_aliases_core2(event);
3765         return intel_pebs_aliases_precdist(event);
3766 }
3767
3768 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3769 {
3770         unsigned long flags = x86_pmu.large_pebs_flags;
3771
3772         if (event->attr.use_clockid)
3773                 flags &= ~PERF_SAMPLE_TIME;
3774         if (!event->attr.exclude_kernel)
3775                 flags &= ~PERF_SAMPLE_REGS_USER;
3776         if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3777                 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3778         return flags;
3779 }
3780
3781 static int intel_pmu_bts_config(struct perf_event *event)
3782 {
3783         struct perf_event_attr *attr = &event->attr;
3784
3785         if (unlikely(intel_pmu_has_bts(event))) {
3786                 /* BTS is not supported by this architecture. */
3787                 if (!x86_pmu.bts_active)
3788                         return -EOPNOTSUPP;
3789
3790                 /* BTS is currently only allowed for user-mode. */
3791                 if (!attr->exclude_kernel)
3792                         return -EOPNOTSUPP;
3793
3794                 /* BTS is not allowed for precise events. */
3795                 if (attr->precise_ip)
3796                         return -EOPNOTSUPP;
3797
3798                 /* disallow bts if conflicting events are present */
3799                 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3800                         return -EBUSY;
3801
3802                 event->destroy = hw_perf_lbr_event_destroy;
3803         }
3804
3805         return 0;
3806 }
3807
3808 static int core_pmu_hw_config(struct perf_event *event)
3809 {
3810         int ret = x86_pmu_hw_config(event);
3811
3812         if (ret)
3813                 return ret;
3814
3815         return intel_pmu_bts_config(event);
3816 }
3817
3818 #define INTEL_TD_METRIC_AVAILABLE_MAX   (INTEL_TD_METRIC_RETIRING + \
3819                                          ((x86_pmu.num_topdown_events - 1) << 8))
3820
3821 static bool is_available_metric_event(struct perf_event *event)
3822 {
3823         return is_metric_event(event) &&
3824                 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
3825 }
3826
3827 static inline bool is_mem_loads_event(struct perf_event *event)
3828 {
3829         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
3830 }
3831
3832 static inline bool is_mem_loads_aux_event(struct perf_event *event)
3833 {
3834         return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
3835 }
3836
3837 static inline bool require_mem_loads_aux_event(struct perf_event *event)
3838 {
3839         if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
3840                 return false;
3841
3842         if (is_hybrid())
3843                 return hybrid_pmu(event->pmu)->cpu_type == hybrid_big;
3844
3845         return true;
3846 }
3847
3848 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
3849 {
3850         union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
3851
3852         return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
3853 }
3854
3855 static int intel_pmu_hw_config(struct perf_event *event)
3856 {
3857         int ret = x86_pmu_hw_config(event);
3858
3859         if (ret)
3860                 return ret;
3861
3862         ret = intel_pmu_bts_config(event);
3863         if (ret)
3864                 return ret;
3865
3866         if (event->attr.precise_ip) {
3867                 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
3868                         return -EINVAL;
3869
3870                 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3871                         event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3872                         if (!(event->attr.sample_type &
3873                               ~intel_pmu_large_pebs_flags(event))) {
3874                                 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3875                                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3876                         }
3877                 }
3878                 if (x86_pmu.pebs_aliases)
3879                         x86_pmu.pebs_aliases(event);
3880         }
3881
3882         if (needs_branch_stack(event)) {
3883                 ret = intel_pmu_setup_lbr_filter(event);
3884                 if (ret)
3885                         return ret;
3886                 event->attach_state |= PERF_ATTACH_SCHED_CB;
3887
3888                 /*
3889                  * BTS is set up earlier in this path, so don't account twice
3890                  */
3891                 if (!unlikely(intel_pmu_has_bts(event))) {
3892                         /* disallow lbr if conflicting events are present */
3893                         if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3894                                 return -EBUSY;
3895
3896                         event->destroy = hw_perf_lbr_event_destroy;
3897                 }
3898         }
3899
3900         if (event->attr.aux_output) {
3901                 if (!event->attr.precise_ip)
3902                         return -EINVAL;
3903
3904                 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3905         }
3906
3907         if ((event->attr.type == PERF_TYPE_HARDWARE) ||
3908             (event->attr.type == PERF_TYPE_HW_CACHE))
3909                 return 0;
3910
3911         /*
3912          * Config Topdown slots and metric events
3913          *
3914          * The slots event on Fixed Counter 3 can support sampling,
3915          * which will be handled normally in x86_perf_event_update().
3916          *
3917          * Metric events don't support sampling and require being paired
3918          * with a slots event as group leader. When the slots event
3919          * is used in a metrics group, it too cannot support sampling.
3920          */
3921         if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
3922                 if (event->attr.config1 || event->attr.config2)
3923                         return -EINVAL;
3924
3925                 /*
3926                  * The TopDown metrics events and slots event don't
3927                  * support any filters.
3928                  */
3929                 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3930                         return -EINVAL;
3931
3932                 if (is_available_metric_event(event)) {
3933                         struct perf_event *leader = event->group_leader;
3934
3935                         /* The metric events don't support sampling. */
3936                         if (is_sampling_event(event))
3937                                 return -EINVAL;
3938
3939                         /* The metric events require a slots group leader. */
3940                         if (!is_slots_event(leader))
3941                                 return -EINVAL;
3942
3943                         /*
3944                          * The leader/SLOTS must not be a sampling event for
3945                          * metric use; hardware requires it starts at 0 when used
3946                          * in conjunction with MSR_PERF_METRICS.
3947                          */
3948                         if (is_sampling_event(leader))
3949                                 return -EINVAL;
3950
3951                         event->event_caps |= PERF_EV_CAP_SIBLING;
3952                         /*
3953                          * Only once we have a METRICs sibling do we
3954                          * need TopDown magic.
3955                          */
3956                         leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3957                         event->hw.flags  |= PERF_X86_EVENT_TOPDOWN;
3958                 }
3959         }
3960
3961         /*
3962          * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
3963          * doesn't function quite right. As a work-around it needs to always be
3964          * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
3965          * The actual count of this second event is irrelevant it just needs
3966          * to be active to make the first event function correctly.
3967          *
3968          * In a group, the auxiliary event must be in front of the load latency
3969          * event. The rule is to simplify the implementation of the check.
3970          * That's because perf cannot have a complete group at the moment.
3971          */
3972         if (require_mem_loads_aux_event(event) &&
3973             (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
3974             is_mem_loads_event(event)) {
3975                 struct perf_event *leader = event->group_leader;
3976                 struct perf_event *sibling = NULL;
3977
3978                 if (!is_mem_loads_aux_event(leader)) {
3979                         for_each_sibling_event(sibling, leader) {
3980                                 if (is_mem_loads_aux_event(sibling))
3981                                         break;
3982                         }
3983                         if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
3984                                 return -ENODATA;
3985                 }
3986         }
3987
3988         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3989                 return 0;
3990
3991         if (x86_pmu.version < 3)
3992                 return -EINVAL;
3993
3994         ret = perf_allow_cpu(&event->attr);
3995         if (ret)
3996                 return ret;
3997
3998         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3999
4000         return 0;
4001 }
4002
4003 /*
4004  * Currently, the only caller of this function is the atomic_switch_perf_msrs().
4005  * The host perf conext helps to prepare the values of the real hardware for
4006  * a set of msrs that need to be switched atomically in a vmx transaction.
4007  *
4008  * For example, the pseudocode needed to add a new msr should look like:
4009  *
4010  * arr[(*nr)++] = (struct perf_guest_switch_msr){
4011  *      .msr = the hardware msr address,
4012  *      .host = the value the hardware has when it doesn't run a guest,
4013  *      .guest = the value the hardware has when it runs a guest,
4014  * };
4015  *
4016  * These values have nothing to do with the emulated values the guest sees
4017  * when it uses {RD,WR}MSR, which should be handled by the KVM context,
4018  * specifically in the intel_pmu_{get,set}_msr().
4019  */
4020 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
4021 {
4022         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4023         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4024         struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
4025         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
4026         u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
4027         int global_ctrl, pebs_enable;
4028
4029         *nr = 0;
4030         global_ctrl = (*nr)++;
4031         arr[global_ctrl] = (struct perf_guest_switch_msr){
4032                 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
4033                 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
4034                 .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask),
4035         };
4036
4037         if (!x86_pmu.pebs)
4038                 return arr;
4039
4040         /*
4041          * If PMU counter has PEBS enabled it is not enough to
4042          * disable counter on a guest entry since PEBS memory
4043          * write can overshoot guest entry and corrupt guest
4044          * memory. Disabling PEBS solves the problem.
4045          *
4046          * Don't do this if the CPU already enforces it.
4047          */
4048         if (x86_pmu.pebs_no_isolation) {
4049                 arr[(*nr)++] = (struct perf_guest_switch_msr){
4050                         .msr = MSR_IA32_PEBS_ENABLE,
4051                         .host = cpuc->pebs_enabled,
4052                         .guest = 0,
4053                 };
4054                 return arr;
4055         }
4056
4057         if (!kvm_pmu || !x86_pmu.pebs_ept)
4058                 return arr;
4059
4060         arr[(*nr)++] = (struct perf_guest_switch_msr){
4061                 .msr = MSR_IA32_DS_AREA,
4062                 .host = (unsigned long)cpuc->ds,
4063                 .guest = kvm_pmu->ds_area,
4064         };
4065
4066         if (x86_pmu.intel_cap.pebs_baseline) {
4067                 arr[(*nr)++] = (struct perf_guest_switch_msr){
4068                         .msr = MSR_PEBS_DATA_CFG,
4069                         .host = cpuc->pebs_data_cfg,
4070                         .guest = kvm_pmu->pebs_data_cfg,
4071                 };
4072         }
4073
4074         pebs_enable = (*nr)++;
4075         arr[pebs_enable] = (struct perf_guest_switch_msr){
4076                 .msr = MSR_IA32_PEBS_ENABLE,
4077                 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
4078                 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
4079         };
4080
4081         if (arr[pebs_enable].host) {
4082                 /* Disable guest PEBS if host PEBS is enabled. */
4083                 arr[pebs_enable].guest = 0;
4084         } else {
4085                 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
4086                 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
4087                 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
4088                 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
4089                 arr[global_ctrl].guest |= arr[pebs_enable].guest;
4090         }
4091
4092         return arr;
4093 }
4094
4095 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
4096 {
4097         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4098         struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
4099         int idx;
4100
4101         for (idx = 0; idx < x86_pmu.num_counters; idx++)  {
4102                 struct perf_event *event = cpuc->events[idx];
4103
4104                 arr[idx].msr = x86_pmu_config_addr(idx);
4105                 arr[idx].host = arr[idx].guest = 0;
4106
4107                 if (!test_bit(idx, cpuc->active_mask))
4108                         continue;
4109
4110                 arr[idx].host = arr[idx].guest =
4111                         event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
4112
4113                 if (event->attr.exclude_host)
4114                         arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4115                 else if (event->attr.exclude_guest)
4116                         arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
4117         }
4118
4119         *nr = x86_pmu.num_counters;
4120         return arr;
4121 }
4122
4123 static void core_pmu_enable_event(struct perf_event *event)
4124 {
4125         if (!event->attr.exclude_host)
4126                 x86_pmu_enable_event(event);
4127 }
4128
4129 static void core_pmu_enable_all(int added)
4130 {
4131         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4132         int idx;
4133
4134         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
4135                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
4136
4137                 if (!test_bit(idx, cpuc->active_mask) ||
4138                                 cpuc->events[idx]->attr.exclude_host)
4139                         continue;
4140
4141                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
4142         }
4143 }
4144
4145 static int hsw_hw_config(struct perf_event *event)
4146 {
4147         int ret = intel_pmu_hw_config(event);
4148
4149         if (ret)
4150                 return ret;
4151         if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
4152                 return 0;
4153         event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
4154
4155         /*
4156          * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
4157          * PEBS or in ANY thread mode. Since the results are non-sensical forbid
4158          * this combination.
4159          */
4160         if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
4161              ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
4162               event->attr.precise_ip > 0))
4163                 return -EOPNOTSUPP;
4164
4165         if (event_is_checkpointed(event)) {
4166                 /*
4167                  * Sampling of checkpointed events can cause situations where
4168                  * the CPU constantly aborts because of a overflow, which is
4169                  * then checkpointed back and ignored. Forbid checkpointing
4170                  * for sampling.
4171                  *
4172                  * But still allow a long sampling period, so that perf stat
4173                  * from KVM works.
4174                  */
4175                 if (event->attr.sample_period > 0 &&
4176                     event->attr.sample_period < 0x7fffffff)
4177                         return -EOPNOTSUPP;
4178         }
4179         return 0;
4180 }
4181
4182 static struct event_constraint counter0_constraint =
4183                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
4184
4185 static struct event_constraint counter2_constraint =
4186                         EVENT_CONSTRAINT(0, 0x4, 0);
4187
4188 static struct event_constraint fixed0_constraint =
4189                         FIXED_EVENT_CONSTRAINT(0x00c0, 0);
4190
4191 static struct event_constraint fixed0_counter0_constraint =
4192                         INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
4193
4194 static struct event_constraint *
4195 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4196                           struct perf_event *event)
4197 {
4198         struct event_constraint *c;
4199
4200         c = intel_get_event_constraints(cpuc, idx, event);
4201
4202         /* Handle special quirk on in_tx_checkpointed only in counter 2 */
4203         if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
4204                 if (c->idxmsk64 & (1U << 2))
4205                         return &counter2_constraint;
4206                 return &emptyconstraint;
4207         }
4208
4209         return c;
4210 }
4211
4212 static struct event_constraint *
4213 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4214                           struct perf_event *event)
4215 {
4216         /*
4217          * Fixed counter 0 has less skid.
4218          * Force instruction:ppp in Fixed counter 0
4219          */
4220         if ((event->attr.precise_ip == 3) &&
4221             constraint_match(&fixed0_constraint, event->hw.config))
4222                 return &fixed0_constraint;
4223
4224         return hsw_get_event_constraints(cpuc, idx, event);
4225 }
4226
4227 static struct event_constraint *
4228 spr_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4229                           struct perf_event *event)
4230 {
4231         struct event_constraint *c;
4232
4233         c = icl_get_event_constraints(cpuc, idx, event);
4234
4235         /*
4236          * The :ppp indicates the Precise Distribution (PDist) facility, which
4237          * is only supported on the GP counter 0. If a :ppp event which is not
4238          * available on the GP counter 0, error out.
4239          * Exception: Instruction PDIR is only available on the fixed counter 0.
4240          */
4241         if ((event->attr.precise_ip == 3) &&
4242             !constraint_match(&fixed0_constraint, event->hw.config)) {
4243                 if (c->idxmsk64 & BIT_ULL(0))
4244                         return &counter0_constraint;
4245
4246                 return &emptyconstraint;
4247         }
4248
4249         return c;
4250 }
4251
4252 static struct event_constraint *
4253 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4254                           struct perf_event *event)
4255 {
4256         struct event_constraint *c;
4257
4258         /* :ppp means to do reduced skid PEBS which is PMC0 only. */
4259         if (event->attr.precise_ip == 3)
4260                 return &counter0_constraint;
4261
4262         c = intel_get_event_constraints(cpuc, idx, event);
4263
4264         return c;
4265 }
4266
4267 static struct event_constraint *
4268 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4269                           struct perf_event *event)
4270 {
4271         struct event_constraint *c;
4272
4273         c = intel_get_event_constraints(cpuc, idx, event);
4274
4275         /*
4276          * :ppp means to do reduced skid PEBS,
4277          * which is available on PMC0 and fixed counter 0.
4278          */
4279         if (event->attr.precise_ip == 3) {
4280                 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
4281                 if (constraint_match(&fixed0_constraint, event->hw.config))
4282                         return &fixed0_counter0_constraint;
4283
4284                 return &counter0_constraint;
4285         }
4286
4287         return c;
4288 }
4289
4290 static bool allow_tsx_force_abort = true;
4291
4292 static struct event_constraint *
4293 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4294                           struct perf_event *event)
4295 {
4296         struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
4297
4298         /*
4299          * Without TFA we must not use PMC3.
4300          */
4301         if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
4302                 c = dyn_constraint(cpuc, c, idx);
4303                 c->idxmsk64 &= ~(1ULL << 3);
4304                 c->weight--;
4305         }
4306
4307         return c;
4308 }
4309
4310 static struct event_constraint *
4311 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4312                           struct perf_event *event)
4313 {
4314         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4315
4316         if (pmu->cpu_type == hybrid_big)
4317                 return spr_get_event_constraints(cpuc, idx, event);
4318         else if (pmu->cpu_type == hybrid_small)
4319                 return tnt_get_event_constraints(cpuc, idx, event);
4320
4321         WARN_ON(1);
4322         return &emptyconstraint;
4323 }
4324
4325 static int adl_hw_config(struct perf_event *event)
4326 {
4327         struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
4328
4329         if (pmu->cpu_type == hybrid_big)
4330                 return hsw_hw_config(event);
4331         else if (pmu->cpu_type == hybrid_small)
4332                 return intel_pmu_hw_config(event);
4333
4334         WARN_ON(1);
4335         return -EOPNOTSUPP;
4336 }
4337
4338 static u8 adl_get_hybrid_cpu_type(void)
4339 {
4340         return hybrid_big;
4341 }
4342
4343 /*
4344  * Broadwell:
4345  *
4346  * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
4347  * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
4348  * the two to enforce a minimum period of 128 (the smallest value that has bits
4349  * 0-5 cleared and >= 100).
4350  *
4351  * Because of how the code in x86_perf_event_set_period() works, the truncation
4352  * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
4353  * to make up for the 'lost' events due to carrying the 'error' in period_left.
4354  *
4355  * Therefore the effective (average) period matches the requested period,
4356  * despite coarser hardware granularity.
4357  */
4358 static void bdw_limit_period(struct perf_event *event, s64 *left)
4359 {
4360         if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
4361                         X86_CONFIG(.event=0xc0, .umask=0x01)) {
4362                 if (*left < 128)
4363                         *left = 128;
4364                 *left &= ~0x3fULL;
4365         }
4366 }
4367
4368 static void nhm_limit_period(struct perf_event *event, s64 *left)
4369 {
4370         *left = max(*left, 32LL);
4371 }
4372
4373 static void spr_limit_period(struct perf_event *event, s64 *left)
4374 {
4375         if (event->attr.precise_ip == 3)
4376                 *left = max(*left, 128LL);
4377 }
4378
4379 PMU_FORMAT_ATTR(event,  "config:0-7"    );
4380 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
4381 PMU_FORMAT_ATTR(edge,   "config:18"     );
4382 PMU_FORMAT_ATTR(pc,     "config:19"     );
4383 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
4384 PMU_FORMAT_ATTR(inv,    "config:23"     );
4385 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
4386 PMU_FORMAT_ATTR(in_tx,  "config:32");
4387 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
4388
4389 static struct attribute *intel_arch_formats_attr[] = {
4390         &format_attr_event.attr,
4391         &format_attr_umask.attr,
4392         &format_attr_edge.attr,
4393         &format_attr_pc.attr,
4394         &format_attr_inv.attr,
4395         &format_attr_cmask.attr,
4396         NULL,
4397 };
4398
4399 ssize_t intel_event_sysfs_show(char *page, u64 config)
4400 {
4401         u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
4402
4403         return x86_event_sysfs_show(page, config, event);
4404 }
4405
4406 static struct intel_shared_regs *allocate_shared_regs(int cpu)
4407 {
4408         struct intel_shared_regs *regs;
4409         int i;
4410
4411         regs = kzalloc_node(sizeof(struct intel_shared_regs),
4412                             GFP_KERNEL, cpu_to_node(cpu));
4413         if (regs) {
4414                 /*
4415                  * initialize the locks to keep lockdep happy
4416                  */
4417                 for (i = 0; i < EXTRA_REG_MAX; i++)
4418                         raw_spin_lock_init(&regs->regs[i].lock);
4419
4420                 regs->core_id = -1;
4421         }
4422         return regs;
4423 }
4424
4425 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
4426 {
4427         struct intel_excl_cntrs *c;
4428
4429         c = kzalloc_node(sizeof(struct intel_excl_cntrs),
4430                          GFP_KERNEL, cpu_to_node(cpu));
4431         if (c) {
4432                 raw_spin_lock_init(&c->lock);
4433                 c->core_id = -1;
4434         }
4435         return c;
4436 }
4437
4438
4439 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4440 {
4441         cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4442
4443         if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4444                 cpuc->shared_regs = allocate_shared_regs(cpu);
4445                 if (!cpuc->shared_regs)
4446                         goto err;
4447         }
4448
4449         if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4450                 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4451
4452                 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4453                 if (!cpuc->constraint_list)
4454                         goto err_shared_regs;
4455         }
4456
4457         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4458                 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4459                 if (!cpuc->excl_cntrs)
4460                         goto err_constraint_list;
4461
4462                 cpuc->excl_thread_id = 0;
4463         }
4464
4465         return 0;
4466
4467 err_constraint_list:
4468         kfree(cpuc->constraint_list);
4469         cpuc->constraint_list = NULL;
4470
4471 err_shared_regs:
4472         kfree(cpuc->shared_regs);
4473         cpuc->shared_regs = NULL;
4474
4475 err:
4476         return -ENOMEM;
4477 }
4478
4479 static int intel_pmu_cpu_prepare(int cpu)
4480 {
4481         return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4482 }
4483
4484 static void flip_smm_bit(void *data)
4485 {
4486         unsigned long set = *(unsigned long *)data;
4487
4488         if (set > 0) {
4489                 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4490                             DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4491         } else {
4492                 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4493                               DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4494         }
4495 }
4496
4497 static bool init_hybrid_pmu(int cpu)
4498 {
4499         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4500         u8 cpu_type = get_this_hybrid_cpu_type();
4501         struct x86_hybrid_pmu *pmu = NULL;
4502         int i;
4503
4504         if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
4505                 cpu_type = x86_pmu.get_hybrid_cpu_type();
4506
4507         for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
4508                 if (x86_pmu.hybrid_pmu[i].cpu_type == cpu_type) {
4509                         pmu = &x86_pmu.hybrid_pmu[i];
4510                         break;
4511                 }
4512         }
4513         if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
4514                 cpuc->pmu = NULL;
4515                 return false;
4516         }
4517
4518         /* Only check and dump the PMU information for the first CPU */
4519         if (!cpumask_empty(&pmu->supported_cpus))
4520                 goto end;
4521
4522         if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed))
4523                 return false;
4524
4525         pr_info("%s PMU driver: ", pmu->name);
4526
4527         if (pmu->intel_cap.pebs_output_pt_available)
4528                 pr_cont("PEBS-via-PT ");
4529
4530         pr_cont("\n");
4531
4532         x86_pmu_show_pmu_cap(pmu->num_counters, pmu->num_counters_fixed,
4533                              pmu->intel_ctrl);
4534
4535 end:
4536         cpumask_set_cpu(cpu, &pmu->supported_cpus);
4537         cpuc->pmu = &pmu->pmu;
4538
4539         return true;
4540 }
4541
4542 static void intel_pmu_cpu_starting(int cpu)
4543 {
4544         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4545         int core_id = topology_core_id(cpu);
4546         int i;
4547
4548         if (is_hybrid() && !init_hybrid_pmu(cpu))
4549                 return;
4550
4551         init_debug_store_on_cpu(cpu);
4552         /*
4553          * Deal with CPUs that don't clear their LBRs on power-up.
4554          */
4555         intel_pmu_lbr_reset();
4556
4557         cpuc->lbr_sel = NULL;
4558
4559         if (x86_pmu.flags & PMU_FL_TFA) {
4560                 WARN_ON_ONCE(cpuc->tfa_shadow);
4561                 cpuc->tfa_shadow = ~0ULL;
4562                 intel_set_tfa(cpuc, false);
4563         }
4564
4565         if (x86_pmu.version > 1)
4566                 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4567
4568         /*
4569          * Disable perf metrics if any added CPU doesn't support it.
4570          *
4571          * Turn off the check for a hybrid architecture, because the
4572          * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
4573          * the architecture features. The perf metrics is a model-specific
4574          * feature for now. The corresponding bit should always be 0 on
4575          * a hybrid platform, e.g., Alder Lake.
4576          */
4577         if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
4578                 union perf_capabilities perf_cap;
4579
4580                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4581                 if (!perf_cap.perf_metrics) {
4582                         x86_pmu.intel_cap.perf_metrics = 0;
4583                         x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4584                 }
4585         }
4586
4587         if (!cpuc->shared_regs)
4588                 return;
4589
4590         if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4591                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4592                         struct intel_shared_regs *pc;
4593
4594                         pc = per_cpu(cpu_hw_events, i).shared_regs;
4595                         if (pc && pc->core_id == core_id) {
4596                                 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4597                                 cpuc->shared_regs = pc;
4598                                 break;
4599                         }
4600                 }
4601                 cpuc->shared_regs->core_id = core_id;
4602                 cpuc->shared_regs->refcnt++;
4603         }
4604
4605         if (x86_pmu.lbr_sel_map)
4606                 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4607
4608         if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4609                 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4610                         struct cpu_hw_events *sibling;
4611                         struct intel_excl_cntrs *c;
4612
4613                         sibling = &per_cpu(cpu_hw_events, i);
4614                         c = sibling->excl_cntrs;
4615                         if (c && c->core_id == core_id) {
4616                                 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4617                                 cpuc->excl_cntrs = c;
4618                                 if (!sibling->excl_thread_id)
4619                                         cpuc->excl_thread_id = 1;
4620                                 break;
4621                         }
4622                 }
4623                 cpuc->excl_cntrs->core_id = core_id;
4624                 cpuc->excl_cntrs->refcnt++;
4625         }
4626 }
4627
4628 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4629 {
4630         struct intel_excl_cntrs *c;
4631
4632         c = cpuc->excl_cntrs;
4633         if (c) {
4634                 if (c->core_id == -1 || --c->refcnt == 0)
4635                         kfree(c);
4636                 cpuc->excl_cntrs = NULL;
4637         }
4638
4639         kfree(cpuc->constraint_list);
4640         cpuc->constraint_list = NULL;
4641 }
4642
4643 static void intel_pmu_cpu_dying(int cpu)
4644 {
4645         fini_debug_store_on_cpu(cpu);
4646 }
4647
4648 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4649 {
4650         struct intel_shared_regs *pc;
4651
4652         pc = cpuc->shared_regs;
4653         if (pc) {
4654                 if (pc->core_id == -1 || --pc->refcnt == 0)
4655                         kfree(pc);
4656                 cpuc->shared_regs = NULL;
4657         }
4658
4659         free_excl_cntrs(cpuc);
4660 }
4661
4662 static void intel_pmu_cpu_dead(int cpu)
4663 {
4664         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4665
4666         intel_cpuc_finish(cpuc);
4667
4668         if (is_hybrid() && cpuc->pmu)
4669                 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
4670 }
4671
4672 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
4673                                  bool sched_in)
4674 {
4675         intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
4676         intel_pmu_lbr_sched_task(pmu_ctx, sched_in);
4677 }
4678
4679 static void intel_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc,
4680                                     struct perf_event_pmu_context *next_epc)
4681 {
4682         intel_pmu_lbr_swap_task_ctx(prev_epc, next_epc);
4683 }
4684
4685 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4686 {
4687         return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4688 }
4689
4690 static void intel_aux_output_init(void)
4691 {
4692         /* Refer also intel_pmu_aux_output_match() */
4693         if (x86_pmu.intel_cap.pebs_output_pt_available)
4694                 x86_pmu.assign = intel_pmu_assign_event;
4695 }
4696
4697 static int intel_pmu_aux_output_match(struct perf_event *event)
4698 {
4699         /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
4700         if (!x86_pmu.intel_cap.pebs_output_pt_available)
4701                 return 0;
4702
4703         return is_intel_pt_event(event);
4704 }
4705
4706 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
4707 {
4708         struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
4709
4710         *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
4711 }
4712
4713 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4714
4715 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4716
4717 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4718
4719 static struct attribute *intel_arch3_formats_attr[] = {
4720         &format_attr_event.attr,
4721         &format_attr_umask.attr,
4722         &format_attr_edge.attr,
4723         &format_attr_pc.attr,
4724         &format_attr_any.attr,
4725         &format_attr_inv.attr,
4726         &format_attr_cmask.attr,
4727         NULL,
4728 };
4729
4730 static struct attribute *hsw_format_attr[] = {
4731         &format_attr_in_tx.attr,
4732         &format_attr_in_tx_cp.attr,
4733         &format_attr_offcore_rsp.attr,
4734         &format_attr_ldlat.attr,
4735         NULL
4736 };
4737
4738 static struct attribute *nhm_format_attr[] = {
4739         &format_attr_offcore_rsp.attr,
4740         &format_attr_ldlat.attr,
4741         NULL
4742 };
4743
4744 static struct attribute *slm_format_attr[] = {
4745         &format_attr_offcore_rsp.attr,
4746         NULL
4747 };
4748
4749 static struct attribute *skl_format_attr[] = {
4750         &format_attr_frontend.attr,
4751         NULL,
4752 };
4753
4754 static __initconst const struct x86_pmu core_pmu = {
4755         .name                   = "core",
4756         .handle_irq             = x86_pmu_handle_irq,
4757         .disable_all            = x86_pmu_disable_all,
4758         .enable_all             = core_pmu_enable_all,
4759         .enable                 = core_pmu_enable_event,
4760         .disable                = x86_pmu_disable_event,
4761         .hw_config              = core_pmu_hw_config,
4762         .schedule_events        = x86_schedule_events,
4763         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4764         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4765         .event_map              = intel_pmu_event_map,
4766         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4767         .apic                   = 1,
4768         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4769
4770         /*
4771          * Intel PMCs cannot be accessed sanely above 32-bit width,
4772          * so we install an artificial 1<<31 period regardless of
4773          * the generic event period:
4774          */
4775         .max_period             = (1ULL<<31) - 1,
4776         .get_event_constraints  = intel_get_event_constraints,
4777         .put_event_constraints  = intel_put_event_constraints,
4778         .event_constraints      = intel_core_event_constraints,
4779         .guest_get_msrs         = core_guest_get_msrs,
4780         .format_attrs           = intel_arch_formats_attr,
4781         .events_sysfs_show      = intel_event_sysfs_show,
4782
4783         /*
4784          * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4785          * together with PMU version 1 and thus be using core_pmu with
4786          * shared_regs. We need following callbacks here to allocate
4787          * it properly.
4788          */
4789         .cpu_prepare            = intel_pmu_cpu_prepare,
4790         .cpu_starting           = intel_pmu_cpu_starting,
4791         .cpu_dying              = intel_pmu_cpu_dying,
4792         .cpu_dead               = intel_pmu_cpu_dead,
4793
4794         .check_period           = intel_pmu_check_period,
4795
4796         .lbr_reset              = intel_pmu_lbr_reset_64,
4797         .lbr_read               = intel_pmu_lbr_read_64,
4798         .lbr_save               = intel_pmu_lbr_save,
4799         .lbr_restore            = intel_pmu_lbr_restore,
4800 };
4801
4802 static __initconst const struct x86_pmu intel_pmu = {
4803         .name                   = "Intel",
4804         .handle_irq             = intel_pmu_handle_irq,
4805         .disable_all            = intel_pmu_disable_all,
4806         .enable_all             = intel_pmu_enable_all,
4807         .enable                 = intel_pmu_enable_event,
4808         .disable                = intel_pmu_disable_event,
4809         .add                    = intel_pmu_add_event,
4810         .del                    = intel_pmu_del_event,
4811         .read                   = intel_pmu_read_event,
4812         .set_period             = intel_pmu_set_period,
4813         .update                 = intel_pmu_update,
4814         .hw_config              = intel_pmu_hw_config,
4815         .schedule_events        = x86_schedule_events,
4816         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
4817         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
4818         .event_map              = intel_pmu_event_map,
4819         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
4820         .apic                   = 1,
4821         .large_pebs_flags       = LARGE_PEBS_FLAGS,
4822         /*
4823          * Intel PMCs cannot be accessed sanely above 32 bit width,
4824          * so we install an artificial 1<<31 period regardless of
4825          * the generic event period:
4826          */
4827         .max_period             = (1ULL << 31) - 1,
4828         .get_event_constraints  = intel_get_event_constraints,
4829         .put_event_constraints  = intel_put_event_constraints,
4830         .pebs_aliases           = intel_pebs_aliases_core2,
4831
4832         .format_attrs           = intel_arch3_formats_attr,
4833         .events_sysfs_show      = intel_event_sysfs_show,
4834
4835         .cpu_prepare            = intel_pmu_cpu_prepare,
4836         .cpu_starting           = intel_pmu_cpu_starting,
4837         .cpu_dying              = intel_pmu_cpu_dying,
4838         .cpu_dead               = intel_pmu_cpu_dead,
4839
4840         .guest_get_msrs         = intel_guest_get_msrs,
4841         .sched_task             = intel_pmu_sched_task,
4842         .swap_task_ctx          = intel_pmu_swap_task_ctx,
4843
4844         .check_period           = intel_pmu_check_period,
4845
4846         .aux_output_match       = intel_pmu_aux_output_match,
4847
4848         .lbr_reset              = intel_pmu_lbr_reset_64,
4849         .lbr_read               = intel_pmu_lbr_read_64,
4850         .lbr_save               = intel_pmu_lbr_save,
4851         .lbr_restore            = intel_pmu_lbr_restore,
4852
4853         /*
4854          * SMM has access to all 4 rings and while traditionally SMM code only
4855          * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
4856          *
4857          * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
4858          * between SMM or not, this results in what should be pure userspace
4859          * counters including SMM data.
4860          *
4861          * This is a clear privilege issue, therefore globally disable
4862          * counting SMM by default.
4863          */
4864         .attr_freeze_on_smi     = 1,
4865 };
4866
4867 static __init void intel_clovertown_quirk(void)
4868 {
4869         /*
4870          * PEBS is unreliable due to:
4871          *
4872          *   AJ67  - PEBS may experience CPL leaks
4873          *   AJ68  - PEBS PMI may be delayed by one event
4874          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4875          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4876          *
4877          * AJ67 could be worked around by restricting the OS/USR flags.
4878          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4879          *
4880          * AJ106 could possibly be worked around by not allowing LBR
4881          *       usage from PEBS, including the fixup.
4882          * AJ68  could possibly be worked around by always programming
4883          *       a pebs_event_reset[0] value and coping with the lost events.
4884          *
4885          * But taken together it might just make sense to not enable PEBS on
4886          * these chips.
4887          */
4888         pr_warn("PEBS disabled due to CPU errata\n");
4889         x86_pmu.pebs = 0;
4890         x86_pmu.pebs_constraints = NULL;
4891 }
4892
4893 static const struct x86_cpu_desc isolation_ucodes[] = {
4894         INTEL_CPU_DESC(INTEL_FAM6_HASWELL,               3, 0x0000001f),
4895         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,             1, 0x0000001e),
4896         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,             1, 0x00000015),
4897         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             2, 0x00000037),
4898         INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,             4, 0x0000000a),
4899         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,             4, 0x00000023),
4900         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,           1, 0x00000014),
4901         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           2, 0x00000010),
4902         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           3, 0x07000009),
4903         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           4, 0x0f000009),
4904         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,           5, 0x0e000002),
4905         INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,           1, 0x0b000014),
4906         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             3, 0x00000021),
4907         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             4, 0x00000000),
4908         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             5, 0x00000000),
4909         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             6, 0x00000000),
4910         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,             7, 0x00000000),
4911         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,            11, 0x00000000),
4912         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L,             3, 0x0000007c),
4913         INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE,               3, 0x0000007c),
4914         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,              9, 0x0000004e),
4915         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,            9, 0x0000004e),
4916         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           10, 0x0000004e),
4917         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           11, 0x0000004e),
4918         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,           12, 0x0000004e),
4919         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             10, 0x0000004e),
4920         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             11, 0x0000004e),
4921         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             12, 0x0000004e),
4922         INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,             13, 0x0000004e),
4923         {}
4924 };
4925
4926 static void intel_check_pebs_isolation(void)
4927 {
4928         x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4929 }
4930
4931 static __init void intel_pebs_isolation_quirk(void)
4932 {
4933         WARN_ON_ONCE(x86_pmu.check_microcode);
4934         x86_pmu.check_microcode = intel_check_pebs_isolation;
4935         intel_check_pebs_isolation();
4936 }
4937
4938 static const struct x86_cpu_desc pebs_ucodes[] = {
4939         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE,          7, 0x00000028),
4940         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        6, 0x00000618),
4941         INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,        7, 0x0000070c),
4942         {}
4943 };
4944
4945 static bool intel_snb_pebs_broken(void)
4946 {
4947         return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4948 }
4949
4950 static void intel_snb_check_microcode(void)
4951 {
4952         if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4953                 return;
4954
4955         /*
4956          * Serialized by the microcode lock..
4957          */
4958         if (x86_pmu.pebs_broken) {
4959                 pr_info("PEBS enabled due to microcode update\n");
4960                 x86_pmu.pebs_broken = 0;
4961         } else {
4962                 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4963                 x86_pmu.pebs_broken = 1;
4964         }
4965 }
4966
4967 static bool is_lbr_from(unsigned long msr)
4968 {
4969         unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4970
4971         return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4972 }
4973
4974 /*
4975  * Under certain circumstances, access certain MSR may cause #GP.
4976  * The function tests if the input MSR can be safely accessed.
4977  */
4978 static bool check_msr(unsigned long msr, u64 mask)
4979 {
4980         u64 val_old, val_new, val_tmp;
4981
4982         /*
4983          * Disable the check for real HW, so we don't
4984          * mess with potentially enabled registers:
4985          */
4986         if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4987                 return true;
4988
4989         /*
4990          * Read the current value, change it and read it back to see if it
4991          * matches, this is needed to detect certain hardware emulators
4992          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4993          */
4994         if (rdmsrl_safe(msr, &val_old))
4995                 return false;
4996
4997         /*
4998          * Only change the bits which can be updated by wrmsrl.
4999          */
5000         val_tmp = val_old ^ mask;
5001
5002         if (is_lbr_from(msr))
5003                 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
5004
5005         if (wrmsrl_safe(msr, val_tmp) ||
5006             rdmsrl_safe(msr, &val_new))
5007                 return false;
5008
5009         /*
5010          * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
5011          * should equal rdmsrl()'s even with the quirk.
5012          */
5013         if (val_new != val_tmp)
5014                 return false;
5015
5016         if (is_lbr_from(msr))
5017                 val_old = lbr_from_signext_quirk_wr(val_old);
5018
5019         /* Here it's sure that the MSR can be safely accessed.
5020          * Restore the old value and return.
5021          */
5022         wrmsrl(msr, val_old);
5023
5024         return true;
5025 }
5026
5027 static __init void intel_sandybridge_quirk(void)
5028 {
5029         x86_pmu.check_microcode = intel_snb_check_microcode;
5030         cpus_read_lock();
5031         intel_snb_check_microcode();
5032         cpus_read_unlock();
5033 }
5034
5035 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
5036         { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
5037         { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
5038         { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
5039         { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
5040         { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
5041         { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
5042         { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
5043 };
5044
5045 static __init void intel_arch_events_quirk(void)
5046 {
5047         int bit;
5048
5049         /* disable event that reported as not present by cpuid */
5050         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
5051                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
5052                 pr_warn("CPUID marked event: \'%s\' unavailable\n",
5053                         intel_arch_events_map[bit].name);
5054         }
5055 }
5056
5057 static __init void intel_nehalem_quirk(void)
5058 {
5059         union cpuid10_ebx ebx;
5060
5061         ebx.full = x86_pmu.events_maskl;
5062         if (ebx.split.no_branch_misses_retired) {
5063                 /*
5064                  * Erratum AAJ80 detected, we work it around by using
5065                  * the BR_MISP_EXEC.ANY event. This will over-count
5066                  * branch-misses, but it's still much better than the
5067                  * architectural event which is often completely bogus:
5068                  */
5069                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
5070                 ebx.split.no_branch_misses_retired = 0;
5071                 x86_pmu.events_maskl = ebx.full;
5072                 pr_info("CPU erratum AAJ80 worked around\n");
5073         }
5074 }
5075
5076 /*
5077  * enable software workaround for errata:
5078  * SNB: BJ122
5079  * IVB: BV98
5080  * HSW: HSD29
5081  *
5082  * Only needed when HT is enabled. However detecting
5083  * if HT is enabled is difficult (model specific). So instead,
5084  * we enable the workaround in the early boot, and verify if
5085  * it is needed in a later initcall phase once we have valid
5086  * topology information to check if HT is actually enabled
5087  */
5088 static __init void intel_ht_bug(void)
5089 {
5090         x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
5091
5092         x86_pmu.start_scheduling = intel_start_scheduling;
5093         x86_pmu.commit_scheduling = intel_commit_scheduling;
5094         x86_pmu.stop_scheduling = intel_stop_scheduling;
5095 }
5096
5097 EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
5098 EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
5099
5100 /* Haswell special events */
5101 EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
5102 EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
5103 EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
5104 EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
5105 EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
5106 EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
5107 EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
5108 EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
5109 EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
5110 EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
5111 EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
5112 EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
5113
5114 static struct attribute *hsw_events_attrs[] = {
5115         EVENT_PTR(td_slots_issued),
5116         EVENT_PTR(td_slots_retired),
5117         EVENT_PTR(td_fetch_bubbles),
5118         EVENT_PTR(td_total_slots),
5119         EVENT_PTR(td_total_slots_scale),
5120         EVENT_PTR(td_recovery_bubbles),
5121         EVENT_PTR(td_recovery_bubbles_scale),
5122         NULL
5123 };
5124
5125 static struct attribute *hsw_mem_events_attrs[] = {
5126         EVENT_PTR(mem_ld_hsw),
5127         EVENT_PTR(mem_st_hsw),
5128         NULL,
5129 };
5130
5131 static struct attribute *hsw_tsx_events_attrs[] = {
5132         EVENT_PTR(tx_start),
5133         EVENT_PTR(tx_commit),
5134         EVENT_PTR(tx_abort),
5135         EVENT_PTR(tx_capacity),
5136         EVENT_PTR(tx_conflict),
5137         EVENT_PTR(el_start),
5138         EVENT_PTR(el_commit),
5139         EVENT_PTR(el_abort),
5140         EVENT_PTR(el_capacity),
5141         EVENT_PTR(el_conflict),
5142         EVENT_PTR(cycles_t),
5143         EVENT_PTR(cycles_ct),
5144         NULL
5145 };
5146
5147 EVENT_ATTR_STR(tx-capacity-read,  tx_capacity_read,  "event=0x54,umask=0x80");
5148 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
5149 EVENT_ATTR_STR(el-capacity-read,  el_capacity_read,  "event=0x54,umask=0x80");
5150 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
5151
5152 static struct attribute *icl_events_attrs[] = {
5153         EVENT_PTR(mem_ld_hsw),
5154         EVENT_PTR(mem_st_hsw),
5155         NULL,
5156 };
5157
5158 static struct attribute *icl_td_events_attrs[] = {
5159         EVENT_PTR(slots),
5160         EVENT_PTR(td_retiring),
5161         EVENT_PTR(td_bad_spec),
5162         EVENT_PTR(td_fe_bound),
5163         EVENT_PTR(td_be_bound),
5164         NULL,
5165 };
5166
5167 static struct attribute *icl_tsx_events_attrs[] = {
5168         EVENT_PTR(tx_start),
5169         EVENT_PTR(tx_abort),
5170         EVENT_PTR(tx_commit),
5171         EVENT_PTR(tx_capacity_read),
5172         EVENT_PTR(tx_capacity_write),
5173         EVENT_PTR(tx_conflict),
5174         EVENT_PTR(el_start),
5175         EVENT_PTR(el_abort),
5176         EVENT_PTR(el_commit),
5177         EVENT_PTR(el_capacity_read),
5178         EVENT_PTR(el_capacity_write),
5179         EVENT_PTR(el_conflict),
5180         EVENT_PTR(cycles_t),
5181         EVENT_PTR(cycles_ct),
5182         NULL,
5183 };
5184
5185
5186 EVENT_ATTR_STR(mem-stores,      mem_st_spr,     "event=0xcd,umask=0x2");
5187 EVENT_ATTR_STR(mem-loads-aux,   mem_ld_aux,     "event=0x03,umask=0x82");
5188
5189 static struct attribute *spr_events_attrs[] = {
5190         EVENT_PTR(mem_ld_hsw),
5191         EVENT_PTR(mem_st_spr),
5192         EVENT_PTR(mem_ld_aux),
5193         NULL,
5194 };
5195
5196 static struct attribute *spr_td_events_attrs[] = {
5197         EVENT_PTR(slots),
5198         EVENT_PTR(td_retiring),
5199         EVENT_PTR(td_bad_spec),
5200         EVENT_PTR(td_fe_bound),
5201         EVENT_PTR(td_be_bound),
5202         EVENT_PTR(td_heavy_ops),
5203         EVENT_PTR(td_br_mispredict),
5204         EVENT_PTR(td_fetch_lat),
5205         EVENT_PTR(td_mem_bound),
5206         NULL,
5207 };
5208
5209 static struct attribute *spr_tsx_events_attrs[] = {
5210         EVENT_PTR(tx_start),
5211         EVENT_PTR(tx_abort),
5212         EVENT_PTR(tx_commit),
5213         EVENT_PTR(tx_capacity_read),
5214         EVENT_PTR(tx_capacity_write),
5215         EVENT_PTR(tx_conflict),
5216         EVENT_PTR(cycles_t),
5217         EVENT_PTR(cycles_ct),
5218         NULL,
5219 };
5220
5221 static ssize_t freeze_on_smi_show(struct device *cdev,
5222                                   struct device_attribute *attr,
5223                                   char *buf)
5224 {
5225         return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
5226 }
5227
5228 static DEFINE_MUTEX(freeze_on_smi_mutex);
5229
5230 static ssize_t freeze_on_smi_store(struct device *cdev,
5231                                    struct device_attribute *attr,
5232                                    const char *buf, size_t count)
5233 {
5234         unsigned long val;
5235         ssize_t ret;
5236
5237         ret = kstrtoul(buf, 0, &val);
5238         if (ret)
5239                 return ret;
5240
5241         if (val > 1)
5242                 return -EINVAL;
5243
5244         mutex_lock(&freeze_on_smi_mutex);
5245
5246         if (x86_pmu.attr_freeze_on_smi == val)
5247                 goto done;
5248
5249         x86_pmu.attr_freeze_on_smi = val;
5250
5251         cpus_read_lock();
5252         on_each_cpu(flip_smm_bit, &val, 1);
5253         cpus_read_unlock();
5254 done:
5255         mutex_unlock(&freeze_on_smi_mutex);
5256
5257         return count;
5258 }
5259
5260 static void update_tfa_sched(void *ignored)
5261 {
5262         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5263
5264         /*
5265          * check if PMC3 is used
5266          * and if so force schedule out for all event types all contexts
5267          */
5268         if (test_bit(3, cpuc->active_mask))
5269                 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
5270 }
5271
5272 static ssize_t show_sysctl_tfa(struct device *cdev,
5273                               struct device_attribute *attr,
5274                               char *buf)
5275 {
5276         return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
5277 }
5278
5279 static ssize_t set_sysctl_tfa(struct device *cdev,
5280                               struct device_attribute *attr,
5281                               const char *buf, size_t count)
5282 {
5283         bool val;
5284         ssize_t ret;
5285
5286         ret = kstrtobool(buf, &val);
5287         if (ret)
5288                 return ret;
5289
5290         /* no change */
5291         if (val == allow_tsx_force_abort)
5292                 return count;
5293
5294         allow_tsx_force_abort = val;
5295
5296         cpus_read_lock();
5297         on_each_cpu(update_tfa_sched, NULL, 1);
5298         cpus_read_unlock();
5299
5300         return count;
5301 }
5302
5303
5304 static DEVICE_ATTR_RW(freeze_on_smi);
5305
5306 static ssize_t branches_show(struct device *cdev,
5307                              struct device_attribute *attr,
5308                              char *buf)
5309 {
5310         return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
5311 }
5312
5313 static DEVICE_ATTR_RO(branches);
5314
5315 static struct attribute *lbr_attrs[] = {
5316         &dev_attr_branches.attr,
5317         NULL
5318 };
5319
5320 static char pmu_name_str[30];
5321
5322 static ssize_t pmu_name_show(struct device *cdev,
5323                              struct device_attribute *attr,
5324                              char *buf)
5325 {
5326         return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
5327 }
5328
5329 static DEVICE_ATTR_RO(pmu_name);
5330
5331 static struct attribute *intel_pmu_caps_attrs[] = {
5332        &dev_attr_pmu_name.attr,
5333        NULL
5334 };
5335
5336 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
5337                    show_sysctl_tfa,
5338                    set_sysctl_tfa);
5339
5340 static struct attribute *intel_pmu_attrs[] = {
5341         &dev_attr_freeze_on_smi.attr,
5342         &dev_attr_allow_tsx_force_abort.attr,
5343         NULL,
5344 };
5345
5346 static umode_t
5347 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5348 {
5349         return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
5350 }
5351
5352 static umode_t
5353 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5354 {
5355         return x86_pmu.pebs ? attr->mode : 0;
5356 }
5357
5358 static umode_t
5359 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5360 {
5361         return x86_pmu.lbr_nr ? attr->mode : 0;
5362 }
5363
5364 static umode_t
5365 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5366 {
5367         return x86_pmu.version >= 2 ? attr->mode : 0;
5368 }
5369
5370 static umode_t
5371 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5372 {
5373         if (attr == &dev_attr_allow_tsx_force_abort.attr)
5374                 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
5375
5376         return attr->mode;
5377 }
5378
5379 static struct attribute_group group_events_td  = {
5380         .name = "events",
5381 };
5382
5383 static struct attribute_group group_events_mem = {
5384         .name       = "events",
5385         .is_visible = pebs_is_visible,
5386 };
5387
5388 static struct attribute_group group_events_tsx = {
5389         .name       = "events",
5390         .is_visible = tsx_is_visible,
5391 };
5392
5393 static struct attribute_group group_caps_gen = {
5394         .name  = "caps",
5395         .attrs = intel_pmu_caps_attrs,
5396 };
5397
5398 static struct attribute_group group_caps_lbr = {
5399         .name       = "caps",
5400         .attrs      = lbr_attrs,
5401         .is_visible = lbr_is_visible,
5402 };
5403
5404 static struct attribute_group group_format_extra = {
5405         .name       = "format",
5406         .is_visible = exra_is_visible,
5407 };
5408
5409 static struct attribute_group group_format_extra_skl = {
5410         .name       = "format",
5411         .is_visible = exra_is_visible,
5412 };
5413
5414 static struct attribute_group group_default = {
5415         .attrs      = intel_pmu_attrs,
5416         .is_visible = default_is_visible,
5417 };
5418
5419 static const struct attribute_group *attr_update[] = {
5420         &group_events_td,
5421         &group_events_mem,
5422         &group_events_tsx,
5423         &group_caps_gen,
5424         &group_caps_lbr,
5425         &group_format_extra,
5426         &group_format_extra_skl,
5427         &group_default,
5428         NULL,
5429 };
5430
5431 EVENT_ATTR_STR_HYBRID(slots,                 slots_adl,        "event=0x00,umask=0x4",                       hybrid_big);
5432 EVENT_ATTR_STR_HYBRID(topdown-retiring,      td_retiring_adl,  "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
5433 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,      td_bad_spec_adl,  "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
5434 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,      td_fe_bound_adl,  "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
5435 EVENT_ATTR_STR_HYBRID(topdown-be-bound,      td_be_bound_adl,  "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
5436 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops,     td_heavy_ops_adl, "event=0x00,umask=0x84",                      hybrid_big);
5437 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl,    "event=0x00,umask=0x85",                      hybrid_big);
5438 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat,     td_fetch_lat_adl, "event=0x00,umask=0x86",                      hybrid_big);
5439 EVENT_ATTR_STR_HYBRID(topdown-mem-bound,     td_mem_bound_adl, "event=0x00,umask=0x87",                      hybrid_big);
5440
5441 static struct attribute *adl_hybrid_events_attrs[] = {
5442         EVENT_PTR(slots_adl),
5443         EVENT_PTR(td_retiring_adl),
5444         EVENT_PTR(td_bad_spec_adl),
5445         EVENT_PTR(td_fe_bound_adl),
5446         EVENT_PTR(td_be_bound_adl),
5447         EVENT_PTR(td_heavy_ops_adl),
5448         EVENT_PTR(td_br_mis_adl),
5449         EVENT_PTR(td_fetch_lat_adl),
5450         EVENT_PTR(td_mem_bound_adl),
5451         NULL,
5452 };
5453
5454 /* Must be in IDX order */
5455 EVENT_ATTR_STR_HYBRID(mem-loads,     mem_ld_adl,     "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
5456 EVENT_ATTR_STR_HYBRID(mem-stores,    mem_st_adl,     "event=0xd0,umask=0x6;event=0xcd,umask=0x2",                 hybrid_big_small);
5457 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82",                                     hybrid_big);
5458
5459 static struct attribute *adl_hybrid_mem_attrs[] = {
5460         EVENT_PTR(mem_ld_adl),
5461         EVENT_PTR(mem_st_adl),
5462         EVENT_PTR(mem_ld_aux_adl),
5463         NULL,
5464 };
5465
5466 EVENT_ATTR_STR_HYBRID(tx-start,          tx_start_adl,          "event=0xc9,umask=0x1",          hybrid_big);
5467 EVENT_ATTR_STR_HYBRID(tx-commit,         tx_commit_adl,         "event=0xc9,umask=0x2",          hybrid_big);
5468 EVENT_ATTR_STR_HYBRID(tx-abort,          tx_abort_adl,          "event=0xc9,umask=0x4",          hybrid_big);
5469 EVENT_ATTR_STR_HYBRID(tx-conflict,       tx_conflict_adl,       "event=0x54,umask=0x1",          hybrid_big);
5470 EVENT_ATTR_STR_HYBRID(cycles-t,          cycles_t_adl,          "event=0x3c,in_tx=1",            hybrid_big);
5471 EVENT_ATTR_STR_HYBRID(cycles-ct,         cycles_ct_adl,         "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
5472 EVENT_ATTR_STR_HYBRID(tx-capacity-read,  tx_capacity_read_adl,  "event=0x54,umask=0x80",         hybrid_big);
5473 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2",          hybrid_big);
5474
5475 static struct attribute *adl_hybrid_tsx_attrs[] = {
5476         EVENT_PTR(tx_start_adl),
5477         EVENT_PTR(tx_abort_adl),
5478         EVENT_PTR(tx_commit_adl),
5479         EVENT_PTR(tx_capacity_read_adl),
5480         EVENT_PTR(tx_capacity_write_adl),
5481         EVENT_PTR(tx_conflict_adl),
5482         EVENT_PTR(cycles_t_adl),
5483         EVENT_PTR(cycles_ct_adl),
5484         NULL,
5485 };
5486
5487 FORMAT_ATTR_HYBRID(in_tx,       hybrid_big);
5488 FORMAT_ATTR_HYBRID(in_tx_cp,    hybrid_big);
5489 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small);
5490 FORMAT_ATTR_HYBRID(ldlat,       hybrid_big_small);
5491 FORMAT_ATTR_HYBRID(frontend,    hybrid_big);
5492
5493 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
5494         FORMAT_HYBRID_PTR(in_tx),
5495         FORMAT_HYBRID_PTR(in_tx_cp),
5496         FORMAT_HYBRID_PTR(offcore_rsp),
5497         FORMAT_HYBRID_PTR(ldlat),
5498         FORMAT_HYBRID_PTR(frontend),
5499         NULL,
5500 };
5501
5502 static struct attribute *adl_hybrid_extra_attr[] = {
5503         FORMAT_HYBRID_PTR(offcore_rsp),
5504         FORMAT_HYBRID_PTR(ldlat),
5505         FORMAT_HYBRID_PTR(frontend),
5506         NULL,
5507 };
5508
5509 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
5510 {
5511         struct device *dev = kobj_to_dev(kobj);
5512         struct x86_hybrid_pmu *pmu =
5513                 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5514         struct perf_pmu_events_hybrid_attr *pmu_attr =
5515                 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
5516
5517         return pmu->cpu_type & pmu_attr->pmu_type;
5518 }
5519
5520 static umode_t hybrid_events_is_visible(struct kobject *kobj,
5521                                         struct attribute *attr, int i)
5522 {
5523         return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
5524 }
5525
5526 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
5527 {
5528         int cpu = cpumask_first(&pmu->supported_cpus);
5529
5530         return (cpu >= nr_cpu_ids) ? -1 : cpu;
5531 }
5532
5533 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
5534                                      struct attribute *attr, int i)
5535 {
5536         struct device *dev = kobj_to_dev(kobj);
5537         struct x86_hybrid_pmu *pmu =
5538                  container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5539         int cpu = hybrid_find_supported_cpu(pmu);
5540
5541         return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
5542 }
5543
5544 static umode_t hybrid_format_is_visible(struct kobject *kobj,
5545                                         struct attribute *attr, int i)
5546 {
5547         struct device *dev = kobj_to_dev(kobj);
5548         struct x86_hybrid_pmu *pmu =
5549                 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5550         struct perf_pmu_format_hybrid_attr *pmu_attr =
5551                 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
5552         int cpu = hybrid_find_supported_cpu(pmu);
5553
5554         return (cpu >= 0) && (pmu->cpu_type & pmu_attr->pmu_type) ? attr->mode : 0;
5555 }
5556
5557 static struct attribute_group hybrid_group_events_td  = {
5558         .name           = "events",
5559         .is_visible     = hybrid_events_is_visible,
5560 };
5561
5562 static struct attribute_group hybrid_group_events_mem = {
5563         .name           = "events",
5564         .is_visible     = hybrid_events_is_visible,
5565 };
5566
5567 static struct attribute_group hybrid_group_events_tsx = {
5568         .name           = "events",
5569         .is_visible     = hybrid_tsx_is_visible,
5570 };
5571
5572 static struct attribute_group hybrid_group_format_extra = {
5573         .name           = "format",
5574         .is_visible     = hybrid_format_is_visible,
5575 };
5576
5577 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
5578                                           struct device_attribute *attr,
5579                                           char *buf)
5580 {
5581         struct x86_hybrid_pmu *pmu =
5582                 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
5583
5584         return cpumap_print_to_pagebuf(true, buf, &pmu->supported_cpus);
5585 }
5586
5587 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
5588 static struct attribute *intel_hybrid_cpus_attrs[] = {
5589         &dev_attr_cpus.attr,
5590         NULL,
5591 };
5592
5593 static struct attribute_group hybrid_group_cpus = {
5594         .attrs          = intel_hybrid_cpus_attrs,
5595 };
5596
5597 static const struct attribute_group *hybrid_attr_update[] = {
5598         &hybrid_group_events_td,
5599         &hybrid_group_events_mem,
5600         &hybrid_group_events_tsx,
5601         &group_caps_gen,
5602         &group_caps_lbr,
5603         &hybrid_group_format_extra,
5604         &group_default,
5605         &hybrid_group_cpus,
5606         NULL,
5607 };
5608
5609 static struct attribute *empty_attrs;
5610
5611 static void intel_pmu_check_num_counters(int *num_counters,
5612                                          int *num_counters_fixed,
5613                                          u64 *intel_ctrl, u64 fixed_mask)
5614 {
5615         if (*num_counters > INTEL_PMC_MAX_GENERIC) {
5616                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5617                      *num_counters, INTEL_PMC_MAX_GENERIC);
5618                 *num_counters = INTEL_PMC_MAX_GENERIC;
5619         }
5620         *intel_ctrl = (1ULL << *num_counters) - 1;
5621
5622         if (*num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5623                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5624                      *num_counters_fixed, INTEL_PMC_MAX_FIXED);
5625                 *num_counters_fixed = INTEL_PMC_MAX_FIXED;
5626         }
5627
5628         *intel_ctrl |= fixed_mask << INTEL_PMC_IDX_FIXED;
5629 }
5630
5631 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5632                                               int num_counters,
5633                                               int num_counters_fixed,
5634                                               u64 intel_ctrl)
5635 {
5636         struct event_constraint *c;
5637
5638         if (!event_constraints)
5639                 return;
5640
5641         /*
5642          * event on fixed counter2 (REF_CYCLES) only works on this
5643          * counter, so do not extend mask to generic counters
5644          */
5645         for_each_event_constraint(c, event_constraints) {
5646                 /*
5647                  * Don't extend the topdown slots and metrics
5648                  * events to the generic counters.
5649                  */
5650                 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5651                         /*
5652                          * Disable topdown slots and metrics events,
5653                          * if slots event is not in CPUID.
5654                          */
5655                         if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
5656                                 c->idxmsk64 = 0;
5657                         c->weight = hweight64(c->idxmsk64);
5658                         continue;
5659                 }
5660
5661                 if (c->cmask == FIXED_EVENT_FLAGS) {
5662                         /* Disabled fixed counters which are not in CPUID */
5663                         c->idxmsk64 &= intel_ctrl;
5664
5665                         /*
5666                          * Don't extend the pseudo-encoding to the
5667                          * generic counters
5668                          */
5669                         if (!use_fixed_pseudo_encoding(c->code))
5670                                 c->idxmsk64 |= (1ULL << num_counters) - 1;
5671                 }
5672                 c->idxmsk64 &=
5673                         ~(~0ULL << (INTEL_PMC_IDX_FIXED + num_counters_fixed));
5674                 c->weight = hweight64(c->idxmsk64);
5675         }
5676 }
5677
5678 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
5679 {
5680         struct extra_reg *er;
5681
5682         /*
5683          * Access extra MSR may cause #GP under certain circumstances.
5684          * E.g. KVM doesn't support offcore event
5685          * Check all extra_regs here.
5686          */
5687         if (!extra_regs)
5688                 return;
5689
5690         for (er = extra_regs; er->msr; er++) {
5691                 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5692                 /* Disable LBR select mapping */
5693                 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5694                         x86_pmu.lbr_sel_map = NULL;
5695         }
5696 }
5697
5698 static void intel_pmu_check_hybrid_pmus(u64 fixed_mask)
5699 {
5700         struct x86_hybrid_pmu *pmu;
5701         int i;
5702
5703         for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
5704                 pmu = &x86_pmu.hybrid_pmu[i];
5705
5706                 intel_pmu_check_num_counters(&pmu->num_counters,
5707                                              &pmu->num_counters_fixed,
5708                                              &pmu->intel_ctrl,
5709                                              fixed_mask);
5710
5711                 if (pmu->intel_cap.perf_metrics) {
5712                         pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5713                         pmu->intel_ctrl |= INTEL_PMC_MSK_FIXED_SLOTS;
5714                 }
5715
5716                 if (pmu->intel_cap.pebs_output_pt_available)
5717                         pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
5718
5719                 intel_pmu_check_event_constraints(pmu->event_constraints,
5720                                                   pmu->num_counters,
5721                                                   pmu->num_counters_fixed,
5722                                                   pmu->intel_ctrl);
5723
5724                 intel_pmu_check_extra_regs(pmu->extra_regs);
5725         }
5726 }
5727
5728 __init int intel_pmu_init(void)
5729 {
5730         struct attribute **extra_skl_attr = &empty_attrs;
5731         struct attribute **extra_attr = &empty_attrs;
5732         struct attribute **td_attr    = &empty_attrs;
5733         struct attribute **mem_attr   = &empty_attrs;
5734         struct attribute **tsx_attr   = &empty_attrs;
5735         union cpuid10_edx edx;
5736         union cpuid10_eax eax;
5737         union cpuid10_ebx ebx;
5738         unsigned int fixed_mask;
5739         bool pmem = false;
5740         int version, i;
5741         char *name;
5742         struct x86_hybrid_pmu *pmu;
5743
5744         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
5745                 switch (boot_cpu_data.x86) {
5746                 case 0x6:
5747                         return p6_pmu_init();
5748                 case 0xb:
5749                         return knc_pmu_init();
5750                 case 0xf:
5751                         return p4_pmu_init();
5752                 }
5753                 return -ENODEV;
5754         }
5755
5756         /*
5757          * Check whether the Architectural PerfMon supports
5758          * Branch Misses Retired hw_event or not.
5759          */
5760         cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
5761         if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
5762                 return -ENODEV;
5763
5764         version = eax.split.version_id;
5765         if (version < 2)
5766                 x86_pmu = core_pmu;
5767         else
5768                 x86_pmu = intel_pmu;
5769
5770         x86_pmu.version                 = version;
5771         x86_pmu.num_counters            = eax.split.num_counters;
5772         x86_pmu.cntval_bits             = eax.split.bit_width;
5773         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
5774
5775         x86_pmu.events_maskl            = ebx.full;
5776         x86_pmu.events_mask_len         = eax.split.mask_length;
5777
5778         x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
5779         x86_pmu.pebs_capable            = PEBS_COUNTER_MASK;
5780
5781         /*
5782          * Quirk: v2 perfmon does not report fixed-purpose events, so
5783          * assume at least 3 events, when not running in a hypervisor:
5784          */
5785         if (version > 1 && version < 5) {
5786                 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
5787
5788                 x86_pmu.num_counters_fixed =
5789                         max((int)edx.split.num_counters_fixed, assume);
5790
5791                 fixed_mask = (1L << x86_pmu.num_counters_fixed) - 1;
5792         } else if (version >= 5)
5793                 x86_pmu.num_counters_fixed = fls(fixed_mask);
5794
5795         if (boot_cpu_has(X86_FEATURE_PDCM)) {
5796                 u64 capabilities;
5797
5798                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
5799                 x86_pmu.intel_cap.capabilities = capabilities;
5800         }
5801
5802         if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
5803                 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
5804                 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
5805         }
5806
5807         if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
5808                 intel_pmu_arch_lbr_init();
5809
5810         intel_ds_init();
5811
5812         x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
5813
5814         if (version >= 5) {
5815                 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
5816                 if (x86_pmu.intel_cap.anythread_deprecated)
5817                         pr_cont(" AnyThread deprecated, ");
5818         }
5819
5820         /*
5821          * Install the hw-cache-events table:
5822          */
5823         switch (boot_cpu_data.x86_model) {
5824         case INTEL_FAM6_CORE_YONAH:
5825                 pr_cont("Core events, ");
5826                 name = "core";
5827                 break;
5828
5829         case INTEL_FAM6_CORE2_MEROM:
5830                 x86_add_quirk(intel_clovertown_quirk);
5831                 fallthrough;
5832
5833         case INTEL_FAM6_CORE2_MEROM_L:
5834         case INTEL_FAM6_CORE2_PENRYN:
5835         case INTEL_FAM6_CORE2_DUNNINGTON:
5836                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5837                        sizeof(hw_cache_event_ids));
5838
5839                 intel_pmu_lbr_init_core();
5840
5841                 x86_pmu.event_constraints = intel_core2_event_constraints;
5842                 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5843                 pr_cont("Core2 events, ");
5844                 name = "core2";
5845                 break;
5846
5847         case INTEL_FAM6_NEHALEM:
5848         case INTEL_FAM6_NEHALEM_EP:
5849         case INTEL_FAM6_NEHALEM_EX:
5850                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5851                        sizeof(hw_cache_event_ids));
5852                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5853                        sizeof(hw_cache_extra_regs));
5854
5855                 intel_pmu_lbr_init_nhm();
5856
5857                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5858                 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5859                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5860                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5861                 x86_pmu.limit_period = nhm_limit_period;
5862
5863                 mem_attr = nhm_mem_events_attrs;
5864
5865                 /* UOPS_ISSUED.STALLED_CYCLES */
5866                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5867                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5868                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5869                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5870                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5871
5872                 intel_pmu_pebs_data_source_nhm();
5873                 x86_add_quirk(intel_nehalem_quirk);
5874                 x86_pmu.pebs_no_tlb = 1;
5875                 extra_attr = nhm_format_attr;
5876
5877                 pr_cont("Nehalem events, ");
5878                 name = "nehalem";
5879                 break;
5880
5881         case INTEL_FAM6_ATOM_BONNELL:
5882         case INTEL_FAM6_ATOM_BONNELL_MID:
5883         case INTEL_FAM6_ATOM_SALTWELL:
5884         case INTEL_FAM6_ATOM_SALTWELL_MID:
5885         case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5886                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5887                        sizeof(hw_cache_event_ids));
5888
5889                 intel_pmu_lbr_init_atom();
5890
5891                 x86_pmu.event_constraints = intel_gen_event_constraints;
5892                 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5893                 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5894                 pr_cont("Atom events, ");
5895                 name = "bonnell";
5896                 break;
5897
5898         case INTEL_FAM6_ATOM_SILVERMONT:
5899         case INTEL_FAM6_ATOM_SILVERMONT_D:
5900         case INTEL_FAM6_ATOM_SILVERMONT_MID:
5901         case INTEL_FAM6_ATOM_AIRMONT:
5902         case INTEL_FAM6_ATOM_AIRMONT_MID:
5903                 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5904                         sizeof(hw_cache_event_ids));
5905                 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5906                        sizeof(hw_cache_extra_regs));
5907
5908                 intel_pmu_lbr_init_slm();
5909
5910                 x86_pmu.event_constraints = intel_slm_event_constraints;
5911                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5912                 x86_pmu.extra_regs = intel_slm_extra_regs;
5913                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5914                 td_attr = slm_events_attrs;
5915                 extra_attr = slm_format_attr;
5916                 pr_cont("Silvermont events, ");
5917                 name = "silvermont";
5918                 break;
5919
5920         case INTEL_FAM6_ATOM_GOLDMONT:
5921         case INTEL_FAM6_ATOM_GOLDMONT_D:
5922                 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5923                        sizeof(hw_cache_event_ids));
5924                 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5925                        sizeof(hw_cache_extra_regs));
5926
5927                 intel_pmu_lbr_init_skl();
5928
5929                 x86_pmu.event_constraints = intel_slm_event_constraints;
5930                 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5931                 x86_pmu.extra_regs = intel_glm_extra_regs;
5932                 /*
5933                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5934                  * for precise cycles.
5935                  * :pp is identical to :ppp
5936                  */
5937                 x86_pmu.pebs_aliases = NULL;
5938                 x86_pmu.pebs_prec_dist = true;
5939                 x86_pmu.lbr_pt_coexist = true;
5940                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5941                 td_attr = glm_events_attrs;
5942                 extra_attr = slm_format_attr;
5943                 pr_cont("Goldmont events, ");
5944                 name = "goldmont";
5945                 break;
5946
5947         case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5948                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5949                        sizeof(hw_cache_event_ids));
5950                 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5951                        sizeof(hw_cache_extra_regs));
5952
5953                 intel_pmu_lbr_init_skl();
5954
5955                 x86_pmu.event_constraints = intel_slm_event_constraints;
5956                 x86_pmu.extra_regs = intel_glm_extra_regs;
5957                 /*
5958                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5959                  * for precise cycles.
5960                  */
5961                 x86_pmu.pebs_aliases = NULL;
5962                 x86_pmu.pebs_prec_dist = true;
5963                 x86_pmu.lbr_pt_coexist = true;
5964                 x86_pmu.pebs_capable = ~0ULL;
5965                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5966                 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5967                 x86_pmu.get_event_constraints = glp_get_event_constraints;
5968                 td_attr = glm_events_attrs;
5969                 /* Goldmont Plus has 4-wide pipeline */
5970                 event_attr_td_total_slots_scale_glm.event_str = "4";
5971                 extra_attr = slm_format_attr;
5972                 pr_cont("Goldmont plus events, ");
5973                 name = "goldmont_plus";
5974                 break;
5975
5976         case INTEL_FAM6_ATOM_TREMONT_D:
5977         case INTEL_FAM6_ATOM_TREMONT:
5978         case INTEL_FAM6_ATOM_TREMONT_L:
5979                 x86_pmu.late_ack = true;
5980                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5981                        sizeof(hw_cache_event_ids));
5982                 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5983                        sizeof(hw_cache_extra_regs));
5984                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5985
5986                 intel_pmu_lbr_init_skl();
5987
5988                 x86_pmu.event_constraints = intel_slm_event_constraints;
5989                 x86_pmu.extra_regs = intel_tnt_extra_regs;
5990                 /*
5991                  * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5992                  * for precise cycles.
5993                  */
5994                 x86_pmu.pebs_aliases = NULL;
5995                 x86_pmu.pebs_prec_dist = true;
5996                 x86_pmu.lbr_pt_coexist = true;
5997                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5998                 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5999                 td_attr = tnt_events_attrs;
6000                 extra_attr = slm_format_attr;
6001                 pr_cont("Tremont events, ");
6002                 name = "Tremont";
6003                 break;
6004
6005         case INTEL_FAM6_ALDERLAKE_N:
6006                 x86_pmu.mid_ack = true;
6007                 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
6008                        sizeof(hw_cache_event_ids));
6009                 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
6010                        sizeof(hw_cache_extra_regs));
6011                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6012
6013                 x86_pmu.event_constraints = intel_slm_event_constraints;
6014                 x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints;
6015                 x86_pmu.extra_regs = intel_grt_extra_regs;
6016
6017                 x86_pmu.pebs_aliases = NULL;
6018                 x86_pmu.pebs_prec_dist = true;
6019                 x86_pmu.pebs_block = true;
6020                 x86_pmu.lbr_pt_coexist = true;
6021                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6022                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6023
6024                 intel_pmu_pebs_data_source_grt();
6025                 x86_pmu.pebs_latency_data = adl_latency_data_small;
6026                 x86_pmu.get_event_constraints = tnt_get_event_constraints;
6027                 x86_pmu.limit_period = spr_limit_period;
6028                 td_attr = tnt_events_attrs;
6029                 mem_attr = grt_mem_attrs;
6030                 extra_attr = nhm_format_attr;
6031                 pr_cont("Gracemont events, ");
6032                 name = "gracemont";
6033                 break;
6034
6035         case INTEL_FAM6_WESTMERE:
6036         case INTEL_FAM6_WESTMERE_EP:
6037         case INTEL_FAM6_WESTMERE_EX:
6038                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
6039                        sizeof(hw_cache_event_ids));
6040                 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
6041                        sizeof(hw_cache_extra_regs));
6042
6043                 intel_pmu_lbr_init_nhm();
6044
6045                 x86_pmu.event_constraints = intel_westmere_event_constraints;
6046                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
6047                 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
6048                 x86_pmu.extra_regs = intel_westmere_extra_regs;
6049                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6050
6051                 mem_attr = nhm_mem_events_attrs;
6052
6053                 /* UOPS_ISSUED.STALLED_CYCLES */
6054                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6055                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6056                 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
6057                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6058                         X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
6059
6060                 intel_pmu_pebs_data_source_nhm();
6061                 extra_attr = nhm_format_attr;
6062                 pr_cont("Westmere events, ");
6063                 name = "westmere";
6064                 break;
6065
6066         case INTEL_FAM6_SANDYBRIDGE:
6067         case INTEL_FAM6_SANDYBRIDGE_X:
6068                 x86_add_quirk(intel_sandybridge_quirk);
6069                 x86_add_quirk(intel_ht_bug);
6070                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6071                        sizeof(hw_cache_event_ids));
6072                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6073                        sizeof(hw_cache_extra_regs));
6074
6075                 intel_pmu_lbr_init_snb();
6076
6077                 x86_pmu.event_constraints = intel_snb_event_constraints;
6078                 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
6079                 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
6080                 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
6081                         x86_pmu.extra_regs = intel_snbep_extra_regs;
6082                 else
6083                         x86_pmu.extra_regs = intel_snb_extra_regs;
6084
6085
6086                 /* all extra regs are per-cpu when HT is on */
6087                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6088                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6089
6090                 td_attr  = snb_events_attrs;
6091                 mem_attr = snb_mem_events_attrs;
6092
6093                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6094                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6095                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6096                 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
6097                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
6098                         X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
6099
6100                 extra_attr = nhm_format_attr;
6101
6102                 pr_cont("SandyBridge events, ");
6103                 name = "sandybridge";
6104                 break;
6105
6106         case INTEL_FAM6_IVYBRIDGE:
6107         case INTEL_FAM6_IVYBRIDGE_X:
6108                 x86_add_quirk(intel_ht_bug);
6109                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
6110                        sizeof(hw_cache_event_ids));
6111                 /* dTLB-load-misses on IVB is different than SNB */
6112                 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
6113
6114                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
6115                        sizeof(hw_cache_extra_regs));
6116
6117                 intel_pmu_lbr_init_snb();
6118
6119                 x86_pmu.event_constraints = intel_ivb_event_constraints;
6120                 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
6121                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6122                 x86_pmu.pebs_prec_dist = true;
6123                 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
6124                         x86_pmu.extra_regs = intel_snbep_extra_regs;
6125                 else
6126                         x86_pmu.extra_regs = intel_snb_extra_regs;
6127                 /* all extra regs are per-cpu when HT is on */
6128                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6129                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6130
6131                 td_attr  = snb_events_attrs;
6132                 mem_attr = snb_mem_events_attrs;
6133
6134                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
6135                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
6136                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
6137
6138                 extra_attr = nhm_format_attr;
6139
6140                 pr_cont("IvyBridge events, ");
6141                 name = "ivybridge";
6142                 break;
6143
6144
6145         case INTEL_FAM6_HASWELL:
6146         case INTEL_FAM6_HASWELL_X:
6147         case INTEL_FAM6_HASWELL_L:
6148         case INTEL_FAM6_HASWELL_G:
6149                 x86_add_quirk(intel_ht_bug);
6150                 x86_add_quirk(intel_pebs_isolation_quirk);
6151                 x86_pmu.late_ack = true;
6152                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6153                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6154
6155                 intel_pmu_lbr_init_hsw();
6156
6157                 x86_pmu.event_constraints = intel_hsw_event_constraints;
6158                 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
6159                 x86_pmu.extra_regs = intel_snbep_extra_regs;
6160                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6161                 x86_pmu.pebs_prec_dist = true;
6162                 /* all extra regs are per-cpu when HT is on */
6163                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6164                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6165
6166                 x86_pmu.hw_config = hsw_hw_config;
6167                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6168                 x86_pmu.lbr_double_abort = true;
6169                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6170                         hsw_format_attr : nhm_format_attr;
6171                 td_attr  = hsw_events_attrs;
6172                 mem_attr = hsw_mem_events_attrs;
6173                 tsx_attr = hsw_tsx_events_attrs;
6174                 pr_cont("Haswell events, ");
6175                 name = "haswell";
6176                 break;
6177
6178         case INTEL_FAM6_BROADWELL:
6179         case INTEL_FAM6_BROADWELL_D:
6180         case INTEL_FAM6_BROADWELL_G:
6181         case INTEL_FAM6_BROADWELL_X:
6182                 x86_add_quirk(intel_pebs_isolation_quirk);
6183                 x86_pmu.late_ack = true;
6184                 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6185                 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6186
6187                 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
6188                 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
6189                                                                          BDW_L3_MISS|HSW_SNOOP_DRAM;
6190                 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
6191                                                                           HSW_SNOOP_DRAM;
6192                 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
6193                                                                              BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6194                 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
6195                                                                               BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
6196
6197                 intel_pmu_lbr_init_hsw();
6198
6199                 x86_pmu.event_constraints = intel_bdw_event_constraints;
6200                 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
6201                 x86_pmu.extra_regs = intel_snbep_extra_regs;
6202                 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
6203                 x86_pmu.pebs_prec_dist = true;
6204                 /* all extra regs are per-cpu when HT is on */
6205                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6206                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6207
6208                 x86_pmu.hw_config = hsw_hw_config;
6209                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6210                 x86_pmu.limit_period = bdw_limit_period;
6211                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6212                         hsw_format_attr : nhm_format_attr;
6213                 td_attr  = hsw_events_attrs;
6214                 mem_attr = hsw_mem_events_attrs;
6215                 tsx_attr = hsw_tsx_events_attrs;
6216                 pr_cont("Broadwell events, ");
6217                 name = "broadwell";
6218                 break;
6219
6220         case INTEL_FAM6_XEON_PHI_KNL:
6221         case INTEL_FAM6_XEON_PHI_KNM:
6222                 memcpy(hw_cache_event_ids,
6223                        slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6224                 memcpy(hw_cache_extra_regs,
6225                        knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6226                 intel_pmu_lbr_init_knl();
6227
6228                 x86_pmu.event_constraints = intel_slm_event_constraints;
6229                 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
6230                 x86_pmu.extra_regs = intel_knl_extra_regs;
6231
6232                 /* all extra regs are per-cpu when HT is on */
6233                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6234                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6235                 extra_attr = slm_format_attr;
6236                 pr_cont("Knights Landing/Mill events, ");
6237                 name = "knights-landing";
6238                 break;
6239
6240         case INTEL_FAM6_SKYLAKE_X:
6241                 pmem = true;
6242                 fallthrough;
6243         case INTEL_FAM6_SKYLAKE_L:
6244         case INTEL_FAM6_SKYLAKE:
6245         case INTEL_FAM6_KABYLAKE_L:
6246         case INTEL_FAM6_KABYLAKE:
6247         case INTEL_FAM6_COMETLAKE_L:
6248         case INTEL_FAM6_COMETLAKE:
6249                 x86_add_quirk(intel_pebs_isolation_quirk);
6250                 x86_pmu.late_ack = true;
6251                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6252                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6253                 intel_pmu_lbr_init_skl();
6254
6255                 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
6256                 event_attr_td_recovery_bubbles.event_str_noht =
6257                         "event=0xd,umask=0x1,cmask=1";
6258                 event_attr_td_recovery_bubbles.event_str_ht =
6259                         "event=0xd,umask=0x1,cmask=1,any=1";
6260
6261                 x86_pmu.event_constraints = intel_skl_event_constraints;
6262                 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
6263                 x86_pmu.extra_regs = intel_skl_extra_regs;
6264                 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
6265                 x86_pmu.pebs_prec_dist = true;
6266                 /* all extra regs are per-cpu when HT is on */
6267                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6268                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6269
6270                 x86_pmu.hw_config = hsw_hw_config;
6271                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
6272                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6273                         hsw_format_attr : nhm_format_attr;
6274                 extra_skl_attr = skl_format_attr;
6275                 td_attr  = hsw_events_attrs;
6276                 mem_attr = hsw_mem_events_attrs;
6277                 tsx_attr = hsw_tsx_events_attrs;
6278                 intel_pmu_pebs_data_source_skl(pmem);
6279
6280                 /*
6281                  * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
6282                  * TSX force abort hooks are not required on these systems. Only deploy
6283                  * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
6284                  */
6285                 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
6286                    !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
6287                         x86_pmu.flags |= PMU_FL_TFA;
6288                         x86_pmu.get_event_constraints = tfa_get_event_constraints;
6289                         x86_pmu.enable_all = intel_tfa_pmu_enable_all;
6290                         x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
6291                 }
6292
6293                 pr_cont("Skylake events, ");
6294                 name = "skylake";
6295                 break;
6296
6297         case INTEL_FAM6_ICELAKE_X:
6298         case INTEL_FAM6_ICELAKE_D:
6299                 x86_pmu.pebs_ept = 1;
6300                 pmem = true;
6301                 fallthrough;
6302         case INTEL_FAM6_ICELAKE_L:
6303         case INTEL_FAM6_ICELAKE:
6304         case INTEL_FAM6_TIGERLAKE_L:
6305         case INTEL_FAM6_TIGERLAKE:
6306         case INTEL_FAM6_ROCKETLAKE:
6307                 x86_pmu.late_ack = true;
6308                 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6309                 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6310                 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6311                 intel_pmu_lbr_init_skl();
6312
6313                 x86_pmu.event_constraints = intel_icl_event_constraints;
6314                 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
6315                 x86_pmu.extra_regs = intel_icl_extra_regs;
6316                 x86_pmu.pebs_aliases = NULL;
6317                 x86_pmu.pebs_prec_dist = true;
6318                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6319                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6320
6321                 x86_pmu.hw_config = hsw_hw_config;
6322                 x86_pmu.get_event_constraints = icl_get_event_constraints;
6323                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6324                         hsw_format_attr : nhm_format_attr;
6325                 extra_skl_attr = skl_format_attr;
6326                 mem_attr = icl_events_attrs;
6327                 td_attr = icl_td_events_attrs;
6328                 tsx_attr = icl_tsx_events_attrs;
6329                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6330                 x86_pmu.lbr_pt_coexist = true;
6331                 intel_pmu_pebs_data_source_skl(pmem);
6332                 x86_pmu.num_topdown_events = 4;
6333                 static_call_update(intel_pmu_update_topdown_event,
6334                                    &icl_update_topdown_event);
6335                 static_call_update(intel_pmu_set_topdown_event_period,
6336                                    &icl_set_topdown_event_period);
6337                 pr_cont("Icelake events, ");
6338                 name = "icelake";
6339                 break;
6340
6341         case INTEL_FAM6_SAPPHIRERAPIDS_X:
6342         case INTEL_FAM6_EMERALDRAPIDS_X:
6343                 pmem = true;
6344                 x86_pmu.late_ack = true;
6345                 memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
6346                 memcpy(hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
6347
6348                 x86_pmu.event_constraints = intel_spr_event_constraints;
6349                 x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
6350                 x86_pmu.extra_regs = intel_spr_extra_regs;
6351                 x86_pmu.limit_period = spr_limit_period;
6352                 x86_pmu.pebs_aliases = NULL;
6353                 x86_pmu.pebs_prec_dist = true;
6354                 x86_pmu.pebs_block = true;
6355                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6356                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6357                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6358                 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6359
6360                 x86_pmu.hw_config = hsw_hw_config;
6361                 x86_pmu.get_event_constraints = spr_get_event_constraints;
6362                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6363                         hsw_format_attr : nhm_format_attr;
6364                 extra_skl_attr = skl_format_attr;
6365                 mem_attr = spr_events_attrs;
6366                 td_attr = spr_td_events_attrs;
6367                 tsx_attr = spr_tsx_events_attrs;
6368                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6369                 x86_pmu.lbr_pt_coexist = true;
6370                 intel_pmu_pebs_data_source_skl(pmem);
6371                 x86_pmu.num_topdown_events = 8;
6372                 static_call_update(intel_pmu_update_topdown_event,
6373                                    &icl_update_topdown_event);
6374                 static_call_update(intel_pmu_set_topdown_event_period,
6375                                    &icl_set_topdown_event_period);
6376                 pr_cont("Sapphire Rapids events, ");
6377                 name = "sapphire_rapids";
6378                 break;
6379
6380         case INTEL_FAM6_ALDERLAKE:
6381         case INTEL_FAM6_ALDERLAKE_L:
6382         case INTEL_FAM6_RAPTORLAKE:
6383         case INTEL_FAM6_RAPTORLAKE_P:
6384         case INTEL_FAM6_RAPTORLAKE_S:
6385                 /*
6386                  * Alder Lake has 2 types of CPU, core and atom.
6387                  *
6388                  * Initialize the common PerfMon capabilities here.
6389                  */
6390                 x86_pmu.hybrid_pmu = kcalloc(X86_HYBRID_NUM_PMUS,
6391                                              sizeof(struct x86_hybrid_pmu),
6392                                              GFP_KERNEL);
6393                 if (!x86_pmu.hybrid_pmu)
6394                         return -ENOMEM;
6395                 static_branch_enable(&perf_is_hybrid);
6396                 x86_pmu.num_hybrid_pmus = X86_HYBRID_NUM_PMUS;
6397
6398                 x86_pmu.pebs_aliases = NULL;
6399                 x86_pmu.pebs_prec_dist = true;
6400                 x86_pmu.pebs_block = true;
6401                 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6402                 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
6403                 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6404                 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
6405                 x86_pmu.lbr_pt_coexist = true;
6406                 intel_pmu_pebs_data_source_adl();
6407                 x86_pmu.pebs_latency_data = adl_latency_data_small;
6408                 x86_pmu.num_topdown_events = 8;
6409                 static_call_update(intel_pmu_update_topdown_event,
6410                                    &adl_update_topdown_event);
6411                 static_call_update(intel_pmu_set_topdown_event_period,
6412                                    &adl_set_topdown_event_period);
6413
6414                 x86_pmu.filter = intel_pmu_filter;
6415                 x86_pmu.get_event_constraints = adl_get_event_constraints;
6416                 x86_pmu.hw_config = adl_hw_config;
6417                 x86_pmu.limit_period = spr_limit_period;
6418                 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
6419                 /*
6420                  * The rtm_abort_event is used to check whether to enable GPRs
6421                  * for the RTM abort event. Atom doesn't have the RTM abort
6422                  * event. There is no harmful to set it in the common
6423                  * x86_pmu.rtm_abort_event.
6424                  */
6425                 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
6426
6427                 td_attr = adl_hybrid_events_attrs;
6428                 mem_attr = adl_hybrid_mem_attrs;
6429                 tsx_attr = adl_hybrid_tsx_attrs;
6430                 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
6431                         adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
6432
6433                 /* Initialize big core specific PerfMon capabilities.*/
6434                 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
6435                 pmu->name = "cpu_core";
6436                 pmu->cpu_type = hybrid_big;
6437                 pmu->late_ack = true;
6438                 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
6439                         pmu->num_counters = x86_pmu.num_counters + 2;
6440                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed + 1;
6441                 } else {
6442                         pmu->num_counters = x86_pmu.num_counters;
6443                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6444                 }
6445
6446                 /*
6447                  * Quirk: For some Alder Lake machine, when all E-cores are disabled in
6448                  * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
6449                  * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
6450                  * mistakenly add extra counters for P-cores. Correct the number of
6451                  * counters here.
6452                  */
6453                 if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) {
6454                         pmu->num_counters = x86_pmu.num_counters;
6455                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6456                 }
6457
6458                 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
6459                 pmu->unconstrained = (struct event_constraint)
6460                                         __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6461                                                            0, pmu->num_counters, 0, 0);
6462                 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6463                 pmu->intel_cap.perf_metrics = 1;
6464                 pmu->intel_cap.pebs_output_pt_available = 0;
6465
6466                 memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6467                 memcpy(pmu->hw_cache_extra_regs, spr_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6468                 pmu->event_constraints = intel_spr_event_constraints;
6469                 pmu->pebs_constraints = intel_spr_pebs_event_constraints;
6470                 pmu->extra_regs = intel_spr_extra_regs;
6471
6472                 /* Initialize Atom core specific PerfMon capabilities.*/
6473                 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
6474                 pmu->name = "cpu_atom";
6475                 pmu->cpu_type = hybrid_small;
6476                 pmu->mid_ack = true;
6477                 pmu->num_counters = x86_pmu.num_counters;
6478                 pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
6479                 pmu->max_pebs_events = x86_pmu.max_pebs_events;
6480                 pmu->unconstrained = (struct event_constraint)
6481                                         __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
6482                                                            0, pmu->num_counters, 0, 0);
6483                 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
6484                 pmu->intel_cap.perf_metrics = 0;
6485                 pmu->intel_cap.pebs_output_pt_available = 1;
6486
6487                 memcpy(pmu->hw_cache_event_ids, glp_hw_cache_event_ids, sizeof(pmu->hw_cache_event_ids));
6488                 memcpy(pmu->hw_cache_extra_regs, tnt_hw_cache_extra_regs, sizeof(pmu->hw_cache_extra_regs));
6489                 pmu->hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
6490                 pmu->event_constraints = intel_slm_event_constraints;
6491                 pmu->pebs_constraints = intel_grt_pebs_event_constraints;
6492                 pmu->extra_regs = intel_grt_extra_regs;
6493                 pr_cont("Alderlake Hybrid events, ");
6494                 name = "alderlake_hybrid";
6495                 break;
6496
6497         default:
6498                 switch (x86_pmu.version) {
6499                 case 1:
6500                         x86_pmu.event_constraints = intel_v1_event_constraints;
6501                         pr_cont("generic architected perfmon v1, ");
6502                         name = "generic_arch_v1";
6503                         break;
6504                 case 2:
6505                 case 3:
6506                 case 4:
6507                         /*
6508                          * default constraints for v2 and up
6509                          */
6510                         x86_pmu.event_constraints = intel_gen_event_constraints;
6511                         pr_cont("generic architected perfmon, ");
6512                         name = "generic_arch_v2+";
6513                         break;
6514                 default:
6515                         /*
6516                          * The default constraints for v5 and up can support up to
6517                          * 16 fixed counters. For the fixed counters 4 and later,
6518                          * the pseudo-encoding is applied.
6519                          * The constraints may be cut according to the CPUID enumeration
6520                          * by inserting the EVENT_CONSTRAINT_END.
6521                          */
6522                         if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED)
6523                                 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
6524                         intel_v5_gen_event_constraints[x86_pmu.num_counters_fixed].weight = -1;
6525                         x86_pmu.event_constraints = intel_v5_gen_event_constraints;
6526                         pr_cont("generic architected perfmon, ");
6527                         name = "generic_arch_v5+";
6528                         break;
6529                 }
6530         }
6531
6532         snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
6533
6534         if (!is_hybrid()) {
6535                 group_events_td.attrs  = td_attr;
6536                 group_events_mem.attrs = mem_attr;
6537                 group_events_tsx.attrs = tsx_attr;
6538                 group_format_extra.attrs = extra_attr;
6539                 group_format_extra_skl.attrs = extra_skl_attr;
6540
6541                 x86_pmu.attr_update = attr_update;
6542         } else {
6543                 hybrid_group_events_td.attrs  = td_attr;
6544                 hybrid_group_events_mem.attrs = mem_attr;
6545                 hybrid_group_events_tsx.attrs = tsx_attr;
6546                 hybrid_group_format_extra.attrs = extra_attr;
6547
6548                 x86_pmu.attr_update = hybrid_attr_update;
6549         }
6550
6551         intel_pmu_check_num_counters(&x86_pmu.num_counters,
6552                                      &x86_pmu.num_counters_fixed,
6553                                      &x86_pmu.intel_ctrl,
6554                                      (u64)fixed_mask);
6555
6556         /* AnyThread may be deprecated on arch perfmon v5 or later */
6557         if (x86_pmu.intel_cap.anythread_deprecated)
6558                 x86_pmu.format_attrs = intel_arch_formats_attr;
6559
6560         intel_pmu_check_event_constraints(x86_pmu.event_constraints,
6561                                           x86_pmu.num_counters,
6562                                           x86_pmu.num_counters_fixed,
6563                                           x86_pmu.intel_ctrl);
6564         /*
6565          * Access LBR MSR may cause #GP under certain circumstances.
6566          * Check all LBR MSR here.
6567          * Disable LBR access if any LBR MSRs can not be accessed.
6568          */
6569         if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
6570                 x86_pmu.lbr_nr = 0;
6571         for (i = 0; i < x86_pmu.lbr_nr; i++) {
6572                 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
6573                       check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
6574                         x86_pmu.lbr_nr = 0;
6575         }
6576
6577         if (x86_pmu.lbr_nr) {
6578                 intel_pmu_lbr_init();
6579
6580                 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
6581
6582                 /* only support branch_stack snapshot for perfmon >= v2 */
6583                 if (x86_pmu.disable_all == intel_pmu_disable_all) {
6584                         if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
6585                                 static_call_update(perf_snapshot_branch_stack,
6586                                                    intel_pmu_snapshot_arch_branch_stack);
6587                         } else {
6588                                 static_call_update(perf_snapshot_branch_stack,
6589                                                    intel_pmu_snapshot_branch_stack);
6590                         }
6591                 }
6592         }
6593
6594         intel_pmu_check_extra_regs(x86_pmu.extra_regs);
6595
6596         /* Support full width counters using alternative MSR range */
6597         if (x86_pmu.intel_cap.full_width_write) {
6598                 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
6599                 x86_pmu.perfctr = MSR_IA32_PMC0;
6600                 pr_cont("full-width counters, ");
6601         }
6602
6603         if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
6604                 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
6605
6606         if (is_hybrid())
6607                 intel_pmu_check_hybrid_pmus((u64)fixed_mask);
6608
6609         intel_aux_output_init();
6610
6611         return 0;
6612 }
6613
6614 /*
6615  * HT bug: phase 2 init
6616  * Called once we have valid topology information to check
6617  * whether or not HT is enabled
6618  * If HT is off, then we disable the workaround
6619  */
6620 static __init int fixup_ht_bug(void)
6621 {
6622         int c;
6623         /*
6624          * problem not present on this CPU model, nothing to do
6625          */
6626         if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
6627                 return 0;
6628
6629         if (topology_max_smt_threads() > 1) {
6630                 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
6631                 return 0;
6632         }
6633
6634         cpus_read_lock();
6635
6636         hardlockup_detector_perf_stop();
6637
6638         x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
6639
6640         x86_pmu.start_scheduling = NULL;
6641         x86_pmu.commit_scheduling = NULL;
6642         x86_pmu.stop_scheduling = NULL;
6643
6644         hardlockup_detector_perf_restart();
6645
6646         for_each_online_cpu(c)
6647                 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
6648
6649         cpus_read_unlock();
6650         pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
6651         return 0;
6652 }
6653 subsys_initcall(fixup_ht_bug)